STL8N10LF3 N-channel 100 V, 25 mΩ typ., 7.8 A STripFET™ III Power MOSFET in a PowerFLAT™ 5x6 package Datasheet — production data Features Order code VDS RDS(on) max ID STL8N10LF3 100 V 35 mΩ 7.8 A (1) 1. The value is rated according to Rthj-pcb 1 ■ Logic level VGS(th) ■ 175 °C maximum junction temperature ■ 100% avalanche rated 2 3 4 PowerFLAT™ 5x6 Applications ■ Switching applications ■ Automotive Figure 1. Description Internal schematic diagram $ This device is an N-channel enhancement mode Power MOSFET produced using STMicroelectronics’ STripFET™ III technology, which is specifically designed to minimize onresistance and gate charge to provide superior switching performance. ' 3 !-V Table 1. Device summary Order code Marking Package Packaging STL8N10LF3 8N10LF3 PowerFLAT™ 5x6 Tape and reel January 2013 This is information on a product in full production. Doc ID 023977 Rev 1 1/13 www.st.com 13 Contents STL8N10LF3 Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 .............................................. 8 Doc ID 023977 Rev 1 STL8N10LF3 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage ±20 V ID(1),(2) Drain current (continuous) at TC = 25 °C 20 A ID Drain current (continuous) at TC = 100 °C 20 A ID (4) Drain current (continuous) at Tpcb = 25 °C 7.8 A ID (4) Drain current (continuous) at Tpcb=100 °C 5.5 A Drain current (pulsed) 31.2 A Total dissipation at TC = 25°C 70 W Total dissipation at Tpcb = 25°C 4.3 W Not-repetitive avalanche current 7.8 A Single pulse avalanche energy 190 mJ Operating junction temperature Storage temperature -55 to 175 °C IDM (3),(4) PTOT (4) PTOT IAV EAS (5) TJ Tstg 1. Specified by design. Not subject to production test. 2. Current is limited by bonding, with an RthJC = 2.1 °C/W the chip is able to carry 32 A at 25 °C. 3. Pulse width limited by safe operating area. 4. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec 5. Starting TJ= 25 °C, ID= 7.8 A, VDD= 25 V. Table 3. Thermal resistance Symbol Parameter Rthj-case Rthj-pcb (1) Value Unit Thermal resistance junction-case 2.1 °C/W Thermal resistance junction-pcb 35 °C/W 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec Doc ID 023977 Rev 1 3/13 Electrical characteristics 2 STL8N10LF3 Electrical characteristics (TCASE = 25 °C unless otherwise specified) Table 4. Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown voltage (VGS= 0) ID = 250 µA IDSS Zero gate voltage drain current (VGS = 0) VDS = 100 V 1 µA IGSS Gate body leakage current (VDS = 0) VGS = ±20 V ±100 nA VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA 3 V RDS(on) Static drain-source onresistance VGS= 10 V, ID= 4 A VGS= 5 V, ID= 4 A 25 40 35 50 mΩ mΩ Min. Typ. Max. Unit V(BR)DSS Table 5. Symbol 100 V 1 Dynamic Parameter Test conditions Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS =25 V, f=1 MHz, VGS=0 - 970 115 11.5 - pF pF pF Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD=50 V, ID = 7.8 A VGS =10 V Figure 13 - 20.5 4 5 - nC nC nC RG Intrinsic gate resistance f=1 MHz open drain Table 6. Symbol td(on) tr td(off) tf 4/13 On/off states Ω 3.65 Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD=50 V, ID= 7.8 A, RG=4.7 Ω, VGS=10 V Figure 12 Doc ID 023977 Rev 1 Min. Typ. - 8.7 9.6 50.6 5.2 Max. Unit - ns ns ns ns STL8N10LF3 Electrical characteristics Table 7. Symbol Parameter Test conditions Min Typ. Max Unit Source-drain current - 7.8 A (1) Source-drain current (pulsed) - 31.2 A (2) Forward on voltage ISD = 7.8 A, VGS=0 - 1.3 V Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 7.8 A, di/dt = 100 A/µs, VDD=48 V, Tj=150 °C - ISD ISDM VSD Source drain diode trr Qrr IRRM 42.5 87 4.08 ns nC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration= 300 µs, duty cycle 1.5% Doc ID 023977 Rev 1 5/13 Electrical characteristics STL8N10LF3 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM13017v1 ID (A) ea n) ar is DS(o th in ax R ion y m at er d b p O ite Lim 10 Zth_AM13007v1 K is δ=0.5 0.2 0.1 -1 10 0.05 0.02 10ms 0.01 100ms 1s 1 -2 10 Tj=175°C Tc=25°C Single pulse Single pulse -3 0.1 0.1 Figure 4. 10 10 1 VDS(V) Output characteristics VGS=10V 25 4V AM13019v1 VDS=4V 15 10 5 5 1 2 3 4 VDS(V) Normalized VDS vs temperature AM13010v1 VDS (norm) ID=1mA 6/13 tp (s) 10 10 Transfer characteristics ID (A) 10 0 0 Figure 7. 25.4 1.06 25.2 1.02 25.0 0.98 24.8 0.94 24.6 24.4 -25 25 75 125 1 TJ(°C) Doc ID 023977 Rev 1 2 4 3 VGS(V) Static drain-source on-resistance AM13020v1 RDS(on) (mΩ) 1.10 0.90 -75 1 0 10 20 15 Figure 6. -1 10 25 5V 20 0 0 -2 -3 10 Figure 5. AM13018v1 ID (A) -4 10 2 VGS=10V 3 4 5 6 7 ID(A) STL8N10LF3 Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. AM13021v1 VGS (V) Capacitance variations C (pF) AM13022v1 1000 Ciss VDD=50V ID=7.8A 10 8 6 100 4 Coss 2 Crss 0 0 5 10 15 20 Qg(nC) Figure 10. Normalized gate threshold voltage vs temperature AM13014v1 VGS(th) ID=250µA (norm) 10 0 20 40 60 80 VDS(V) Figure 11. Normalized on-resistance vs temperature AM13015v1 RDS(on) ID=4A VGS=10V (norm) 2.0 1.2 1.6 1.0 1.2 0.8 0.8 0.6 0.4 -75 0.4 0 -25 25 75 125 TJ(°C) Doc ID 023977 Rev 1 -75 -25 25 75 125 TJ(°C) 7/13 Test circuits 3 STL8N10LF3 Test circuits Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test switching and diode recovery times circuit A A D.U.T. FAST DIODE B B L A D G VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 Figure 16. Unclamped inductive waveform AM01471v1 Figure 17. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDD VDS 90% VGS AM01472v1 8/13 0 Doc ID 023977 Rev 1 10% AM01473v1 STL8N10LF3 4 Package mechanical data Package mechanical data Table 8. PowerFLAT 5x6 type S-R mechanical data mm Dim. Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 A2 0.25 b 0.30 D 5.00 5.20 5.40 E 5.95 6.15 6.35 D2 4.11 4.31 E2 3.50 3.70 e 0.50 1.27 L 0.60 0.80 K 1.275 1.575 Doc ID 023977 Rev 1 9/13 Package mechanical data STL8N10LF3 Figure 18. PowerFLAT 5x6 type S-R drawing Bottom View Side View Top View 8231817_Rev.F_Ribbon type S-R 10/13 Doc ID 023977 Rev 1 STL8N10LF3 Package mechanical data Figure 19. PowerFLAT 5x6 recommended footprint (dimensions are in mm) Footprint Doc ID 023977 Rev 1 11/13 Revision history 5 STL8N10LF3 Revision history Table 9. 12/13 Document revision history Date Revision 17-Jan-2013 1 Changes First release. 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