### FAIRCHILD AN-5046

```Fairchild Semiconductor
Application Note
August 2002
Revised August 2002
Abstract
Failsafe biasing of an LVDS data line receiver establishes a
know state under certain fault conditions. Typically these
devices are designed with integrated failsafe biasing resistors. This paper will discuss how to add additional external
failsafe biasing resistor networks to increase noise immunity in a system and improve the reliability of failsafe operation within a specific application. An application example
will be discussed and calculations for resistor values will
also be provided.
External “Assist”
Failsafe Resistors
resistors should be considered. The resistor values should
be specified to overcome the differential noise and have
minimal impact on the driver current. Figure 1 illustrates a
typical differential input voltage verses the logic output
The amount of differential noise anticipated should be
measured and resistor values chosen to overcome this
noise. The VFSB is the offset voltage is generated across
the Rt resistor and the external resistor values should be
enough to overcome the differential noise. Making VFSB
too large will counter with the driver loop current impacting
the signal integrity of the signal. Note using shielded cable
can reduce differential noise.
Certain applications (especially noisy environments) may
external failsafe resistors may be justified to create a larger
noise margin beyond what is provided by the receiver.
Selecting external failsafe resistors can be done to protect
against differential noise and have minimal impact on the
signal integrity of the LVDS signal. Additional failsafe current will tend to “unbalance” the symmetry of the LVDS signal which should not be an issue at low data rates,
however could be aggravated at higher data rates.
Once the amount of differential noise at the receiver input
has been determined (under worse case conditions), the
following formulas are provided to assist the designer in
calculating the resistor values.
What Resistor Values
Should Be Used?
VFSB
= Rpu / (Rpu + Rt + Rpd)*VCC
IFSB
= VCC / (Rpu + Rt + Rpd)
VCM
= (Rup + Rt/2) / (Rpu + Rt + Rpd)*VCC
Rt
= (Rt* (Rpu + Rpd)) /(Rpu + Rt + Rpd)
(IFSB < 0.1*ILOOP)
(Ideal VCM ≅ 1.2V)
(match Rt to ZODIFF)
For Fairchild LVDS receivers designed with an internal failsafe bias, they typically will have an internal bias voltage of
≅ 20 to 35mV (Figure 1). In a cable application where the
receiver will not always be driven by the transmitter and
there is a potential for the presence of more than 20mV of
The external failsafe “Assist” resistors may change the termination resistance, thus adjust the Rt value to match
within 10% of the characteristic impedance of the transmission line.
FIGURE 1. Differential Input Voltage verses Receiver Output Voltage
AN500799
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AN-5046 LVDS Receiver Failsafe Biasing Networks
AN-5046
AN-5046
What Resistor Values Should Be Used?
(Continued)
FIGURE 2. Simplified Schematic of Internal Failsafe Circuitry with External “Assist” Failsafe Resistors
Point-to-Point Application Example
Failsafe circuitry internal to the receiver is designed to
source/sink a small amount of current, providing failsafe
protection for floating receiver inputs, shorted inputs and
terminated inputs. However, an application environment
and certain conditions potentially create differential noise
that causes the receiver to oscillate and not maintain a
known failsafe state. External failsafe resistors may be
needed to increase or improve noise margins to insure reliable failsafe operation under all fault conditions. Refer to
Figure 3 as an example of an external failsafe bias resistor
network.
System problems can impact proper “Failsafe” operation
with LVDS receivers in an application involving communication between equipment racks within the same cabinet
typically found in telecom equipment. Potentially receiver
outputs will not assert “failsafe” (Logic High) under specific
failsafe conditions within a system environment due to the
presence of system noise or other circuitry (such as ESD
protection diodes) which could impede the effectiveness of
the integrated failsafe feature.
FIGURE 3. Point-to-Point Circuit Application with External Failsafe Resistors and ESD Protection Diodes
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1. Reviewing the circuit in Figure 1, with the driver card
powered down (VCC = 0V), the ESD protection diode
network on the driver card is forward biased. This
results in a clamping action of the diodes providing an
alternate current path reducing the offset voltage created across the termination. The diodes forward bias
causing an approximate worst case clamping of the
line at ≅ 0.3V with respect to ground.
3. The suggested resistor network should provide reliable
failsafe operation and improved differential noise
immunity during a failsafe event.
4. The additional resistor network has been confirmed to
have no impact on the signal integrity in our lab setup.
For certain cable point-to-point applications where data
rates are in the low MHz range, additional failsafe protection may be needed to improve noise margins and increase
the reliability of failsafe operation. The following section
discusses and illustrates resistor networks that could be
considered for additional failsafe bias resistors yielding
increased noise margins.
2. Series resistors Rsp and Rsm work to counter the
effects of the clamping action of the diodes providing
assert a logic high on the output.
Suggested Failsafe Resistor Values for FIN1032
Rpu
Resistor Pull Up
Rsp
Resistor Series Plus
Rt
Resistor Termination
Rsm
Resistor Series Minus
Rpd
Resistor Pull Down
IFS
Failsafe Bias Current
VFSB Failsafe Bias Voltage
VCM Common Mode Voltage
FIN1032 F/S Bias Voltage and Current Calculations
Without Rsp & Rsm Resistors
With Rsp & Rsm Resistors
IFS ≅ 3.3V/16.2KΩ = 0.205mA
IFS ≅ 3.3V/16.3KΩ = 0.202mA
VCM ≅ 0.205mA*6.05KΩ ≅ 1.24V
VCM ≅ 0.2mA*6.15KΩ ≅ 1.23V
VFSB ≅ IFS*100Ω ≅ 21mV
VFSB ≅ IFS*300Ω ≅ 60mV
Note: An additional failsafe bias voltage of ≅40mV can be attained with the series resistors.
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AN-5046
Worse Case Failsafe Conditions
AN-5046 LVDS Receiver Failsafe Biasing Networks
Suggested Failsafe Resistor Values for FIN1532
Rpu
Resistor Pull Up
Rsp
Resistor Series Plus
Rt
Resistor Termination
Rsm
Resistor Series Minus
Rpd
Resistor Pull Down
IFS
Failsafe Bias Current
VFSB Failsafe Bias Voltage
VCM Common Mode Voltage
FIN1532 F/S Bias Voltage and Current Calculations
Without Rsp & Rsm Resistors
With Rsp & Rsm Resistors
IFS ≅ 5V/20.1KΩ = 0.249mA
IFS ≅ 5V/20.25KΩ = 0.25mA
VCM ≅ 0.249mA*5.050KΩ ≅ 1.26V
VCM ≅ 0.25mA*5.125KΩ ≅ 1.26V
VFSB ≅ IFS*100Ω ≅ 25mV
VFSB ≅ IFS*250Ω ≅ 62mV
Note: An additional failsafe bias voltage of ≅40mV can be attained with the series resistors.
Summary and Conclusions
LVDS translators are supplied with internal failsafe bias
protection. Depending on the system noise environment, it
may be necessary to implement an external FS bias resistor network to insure reliable failsafe operation. Other circuitry in a system such as ESD protection networks may
impede or counter the effectiveness of the integrated
receiver failsafe bias circuit. This paper provided an example of a system that had ESD diode networks employed on
the driver and receiver cards. The specific application environment and failsafe requirements will ultimately dictate the
optimum failsafe solution.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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