RX IF/BBA WITH GPS S1M8662A (Preliminary) INTRODUCTION 32-BCC++-5.0×5.0 S1M8662A is CDMA/PCS/GPS Triple Mode IF/ baseband IC which is divided into three main parts - IF frequency processing, basband processing , and digital interface. The receiver IC (S1M8662A)and transmitter IC (S1M8657) are provided as a KIT. S1M8662A is a receiver IC, installed with a Rx AGC, Baseband Converter, Baseband analog filter, and A-D Converter. It can send a digital baseband signal to the digital baseband IC. S1M8662A is fabricated on the Samsung's 0.5um high-speed, high frequency BICMOS processing and can achieve superior high frequency and low power digital operations. Its operating voltage is 2.7 to 3.3V, and operating temperature -30 to +85°C . FEATURES • Cellular CDMA/PCS/GPS Triple Mode • AGC input signal range : 90dB • QPSK Baseband Converter • Built-in I ,Q Baseband signal extractor LPF • Built-in 4-bit ADC for converting I and Q CDMA analog baseband signals to digital baseband signals • Built-in VCO for baseband conversion • Built-in Modem PDM control circuit to compensate the I and Q offsets • Built-in TCXO output ON/OFF • 3-Line Serial Port Interface (SPI) • Operating Voltage : 2.7 to 3.3V • 32BCC++(5mm * 5mm * 0.8mm) Package ORDERING INFORMATION Device Package Operating Temperature ++ S1M8662AX01-F0T0 32-BCC++-5.0×5.0 -30 to +85°C ++ : Under Development 1 S1M8662A (Preliminary) RX IF/BBA WITH GPS BLOCK DIAGRAM RXVCO_OUT1,2 RXVCO_T1 RXVCO_T2 I_OFS CDMA LPF Div. N SW N=2,3,4,6 90 Offset Control TCXO_out TCXO_in CHIPX8 CDMA LPF 4-Bit ADC GPS LPF Q_OFS 2 RXID[0] - [3] X1 0 GRX_IF1 GRX_IF2 4-Bit ADC GPS LPF CRX_IF1 CRX_IF2 RAGC_CONT CLOCK DATA STROBE SPI Control VCO RXQD[0] - [3] RX IF/BBA WITH GPS S1M8662A (Preliminary) SPI_DATA 21 20 RXVCO_OUT2 SPI_CLK 22 RXVCO_OUT1 TCXO_in 23 18 CHIPX8 24 SPI_STB RXQD[3] 25 19 RXQD[2] PIN CONFIGURATION 17 RXQD[1] 26 16 VDDA RXQD[0] 27 15 RXVCO_T2 VDDM 28 14 RXVCO_T1 RXID[3] 29 13 I_OFS RXID[2] 30 12 Q_OFS RXID[1] 31 11 VDDA RXID[0] 32 GND SLUG 10 VDDA S1M8662A 6 7 8 CRX_IF2 VDDA TCXO_out 4 GRX_IF1 9 CRX_IF1 3 RAGC_CONT 5 2 VDDA GRX_IF2 1 VDDD (Top View) 3 S1M8662A (Preliminary) RX IF/BBA WITH GPS PIN DESCRIPTION 4 Pin No Symbol I/O 1 VDDD P Power for the digital logic. 2 VDDA P Power input terminal for the analog circuit. 3 RAGC_CONT AI AGC gain control input. The input voltage is allowed up to VDDA. It remains at High impedance during SLEEP. 4 AI 5 GRX_IF1 GRX_IF2 GPS IF input terminals, which have an input impedance of about 865W; generally, the GPS IF SAW filter is connected to them. When these terminals are not used, they remain at High impedance. 6 CRX_IF1 AI 7 CRX_IF2 CDMA IF input terminals, which have an input impedance of about 865Ω; generally, the CDMA IF SAW filter is connected to them. When these terminals are not used, they remain at High impedance. 8 VDDA P Power input terminal for the analog circuit. 9 TCXO_out DO 10 VDDA P Power input terminal for the analog circuit. 11 VDDA P Power input terminal for the analog circuit. 12 13 Q_OFS I_OFS AI Control DC input for removing the DC offset generated in the S1M8662A and system during CDMA and GPS Mode. The control DC is generated in the modem in PDM form, passes through the R-C filter and is converted to DC, which is sent to this input terminal. 14 15 RXVCO_T1 AI Very sensitive terminal, which is connected to the oscillation L-C resonance circuit. Their impedance are about 2kΩ 16 VDDA P Power input terminal for the analog circuit. 17 18 RXVCO_OUT1 RXVCO_OUT2 AO Output for the PLL, able to output about -12dBm. When this is not used, it remains at high impedance. 19 SPI_STB DI 3-Line serial control. Strobe input port. If this pin is opened, it remains at Low. 20 SPI_DATA BI 3-Line serial control. DATA input/output port. If this pin is opened, it remains at Low. 21 SPI_CLK DI 3-Line serial control. CLOCK input/output port. If this pin is opened, it remains at Low. 22 TCXO_in AI/DI 23 CHIPx8 DI RXVCO_T2 Description TCXO Clock output. division ratio : 1 Reference frequency input terminal connected to the VCTCXO output. When this pin stops, only DC bias is delivered to maintain the DC charge value of the capacitor connected externally CHIPx8 Clock input port. CDMA/GPS ADC sampling clock from the MSM. RX IF/BBA WITH GPS S1M8662A (Preliminary) PIN DESCRIPTION (Continued) Pin No Symbol I/O Description 24 25 26 27 RXQD3 RXQD2 RXQD1 RXQD0 DO Q Channel 4-bit A-D Converter's digital outputs, which are connected to the modem data input pins. These data are synchronized at CHIP×8's rising edge and output. Because they are valid at the falling edge, the data are latched at the falling edge in the modem. 28 VDDM DI Power source for a logic circuit ,related to the digital input /output, connected to an external digital logic such as the modem. 29 30 31 32 RXQD3 RXQD2 RXQD1 RXQD0 DO I Channel 4-bit A-D Converter's digital outputs, which are connected to the modem data input pins. These data are synchronized at CHIP×8's rising edge and output. Because they are valid at the falling edge, the data are latched at the falling edge in the modem. Table 1. S1M8660A and S1M8662A Function & Control Content Comparison Function / Mode Control Operation Modes CDMA (Cellular CDMA, PCS) AMPS (FM) Global Positioning System (GPS) IF AGC 90dB Range CDMA (Cellular CDMA, PCS) AMPS (FM) Global Positioning System (GPS) IF to Analog Baseband Quadrature Down-Conversion CDMA (Cellular CDMA, PCS) AMPS (FM) Global Positioning System (GPS) Low Pass Baseband I/Q Filtering with Mode Specific Performance CDMA (Cellular CDMA, PCS) AMPS (FM) Global Positioning System (GPS) 4-bit I/Q Analog to Digital Converters, Parallel Outputs CDMA (Cellular CDMA, PCS) Global Positioning System (GPS) 8-bit I/Q Analog to Digital Converters, Serial Outputs AMPS (FM) Rx Slotting Operation for Saving Current Consumption Clock Generation TCXO/N Output Configurable CHIPx8 as Input or Output VCO for Generation the Rx IF LO Analog Baseband Amplifiers with I/Q Offset Controls S1M8660A S1M8662A • • • • • • • • • • • • • • • • • • • • • • • • • • • ∆ (N=1) ∆ (Input) • • • • • • 5 S1M8662A (Preliminary) RX IF/BBA WITH GPS ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Power supply VCC -0.5 to 3.6V Storage temperature TSTG -55 to +125°C Operating temperature TOPR -30 to +85°C Storage temperature HBM TBD Electrostatic discharge rating MM TBD Symbol Value VDDA, VDDD 2.7 to 3.3V VDDM 2.4 to 3.3V Ta -30 to +85°C RECOMMENDED OPERATING CONDITIONS Characteristic Power supply Ambient operating temperature ELECTRICAL CHARACTERISTICS Electrical Characteristics(VCC = 3.3V, Ta = 25°°C) Characteristic Test Conditions Symbol Min Typ Max Units Current consumption CDMA idle mode ICRX - 23 30 mA Current consumption CDMA sleep mode ICSLP - 300 650 uA Current consumption CDMA slot mode ICSLT - 5 7 mA Current consumption GPS idle mode IGPS - 24 31 mA Logic high input VIH VDDM-0.4 - - V Logic low input VIL - - 0.4 V Logic high output VOH VDDM-0.4 - - V Logic low output VOL - - 0.4 V Digital input capacitance CDI - - 5 pF CDOL - - 10 pF Attach C = 2pF ZTCXO 10 - - kΩ VCO input resistance IF VCO differential RVCO - 2.0 - kΩ VCO input capacitance IF VCO differential CVCO - - 2 pF Digital output load capacitance TCXO input impedance 6 RX IF/BBA WITH GPS S1M8662A (Preliminary) AC Characteristics Characteristic Test Conditions Symbol Min Typ Max Unit CDMA Performance Input sensitivity Maximum AGC gain. Control input signal so that output corresponding to 3LSB is output from ADC. VCSEN -102 - - dBm Maximum input signal Minimum AGC gain. Control input signal so that output corresponding to 3LSB is output from ADC. VCMAX - - -12 dBm AGC gain slope PDM 3.3V Mode GS LOPE 43 50 57 dB/V AGC gain error over temperature -30 to +85°C. GVAR -3 - 3 dB IF input frequency range Cin < 2pF Fin - - 250 MHz Zin 0.8 1.0 1.2 kΩ Input power = -102dBm NFmin - - 7 dB Input power = -75dBm NFmid - - 20 dB Input power = -25dBm NFmax - - 72 dB AGC gain Max. IIP3max -53 - - dBm AGC gain Min. IIP3min -10 - - dBm IF input Impedance Noise figure IIP3 Spurious contents ADC generated harmonic frequency component. Two signals in the in-band are each mixed with signals which will allow ADC to produce -7dB output signals. The harmonic and non-harmonic components of the ADC output signals between 1kHz to 20MHz are extracted and added. The AGC control voltage is controlled so that ADC output is full scale when the input signal is -80dBm. TSpur - - -25 dBc Spurious content related to jammer In-band spurious peak value produced by IMD based on 2 jammer signals. One in-band signal(@50kHz,0.5*F/S) and two jammers(@900kHz, 22dB*F/S and @1.7MHz, 21dB*F/S)are simultaneously input. AGC control voltage is controlled so that ADC output is F/S when the input signal is -80dBm. Jspur - - -18.4 dBc 7 S1M8662A (Preliminary) RX IF/BBA WITH GPS AC Characteristics (Continued) Characteristic Test Conditions Symbol Min Typ Max Unit - 1.0 dB Single-tone jammer desense Overall gain reduction due to one jammer. The in-band signal at -97dBm (control the AGC control voltage to 0.5*F/S)and the jammer signal at 900kHz and -57dBm are simultaneously input. Jdsen - Residual Sideband 1 + k 2 + 2 k cosθ RSB = 20 log 1 + k 2 − 2 k cosθ RSB 22 GOFS - 250 - %FS/V Zoff 100 - - kΩ dB k : Linear Gain Mismatch θ : Phase Mismatch in Deg. Offset gain slope Amount of code change of the voltage ADC output at the I/Q offset control Offset adjust input impedance - Out-band ≥ 900kHz ATC9 46 - - dB attenuation ≥ 1.2MHz ATC12 48 - - dB Gain flatness Amount of gain change along I and Q paths between 1kHz to 615kHz Gft -1 1 dB IF VCO pertormance 8 VCO and buffered output Frequency range VCO external time constant and PLL value Fvco - 170 500 MHz VCO phase noise Tank LC's Q value should be above 20. Measure @100kHz away from the midfrequency. Pvco - - 104 dBc/Hz RXVCO_OUT output power Select a VCO buffer output value reduced by -2dB. Connect output load to 50Ω. Ovco -15 - - dBm RX IF/BBA WITH GPS S1M8662A (Preliminary) AC Characteristics (Continued) Characteristic Test Conditions Symbol Min Typ Max Unit GPS Performance Input sensitivity Maximum AGC gain. Control input signal so that ADC outputs 0.5*F/S. VCSEN -102 - - dBm Maximum input signal Minimum AGC gain Control input signal so that ADC outputs 0.5*F/S. VCMAX - - -12 dBm AGC gain slope PDM 3.3V Mode GSLOPE 43 50 57 dB/V AGC gain error over temperature -30°C to +85°C. GVAR -3 - 3 dB IF input frequency range Cin < 2pF Fin - - 250 MHz Zin 0.8 1.0 1.2 kΩ Input power = -98dBm NFmin - - 7 dB Input power = -75dBm NFmid - - 12 dB Input power = -25dBm NFmax - - 58 dB AGC gain Max. IIP3max -53 - - dBm AGC gain Min. IIP3min -25 - - dBm Offset gain slope Amount of code change of the voltage ADC output at the I/Q offset control GOFS Offset adjust input impedance - Out-band IF input Impedance Noise figure IIP3 250 %FS/ V Zoff 100 - - kΩ ≥ 1.3MHz ATC13 46 - - dB attenuation ≥ 1.7MHz ATC17 48 - - dB Residual Sideband 1 + k 2 + 2 k cosθ RSB = 20 log 1 + k 2 − 2 k cosθ RSB 22 - - dB Gft -1.5 - 1.5 dB k : Linear Gain Mismatch θ : Phase Mismatch in Deg. Gain flatness Amount of gain change along I and Q paths between 1kHz to 800kHz 9 S1M8662A (Preliminary) RX IF/BBA WITH GPS TIMING DIAGRAMS 101.7ns (9.8304MHz) 50.9 +10ns 3 - 12ns 50.9 +10ns 3 - 12ns 90% 10% 15ns over Valid Data Valid Data Valid Data 20ns over Figure 1. CDMA Receive ADC Timing 122.2ns (8.184MHz) 61.1ns 3 - 12ns 3 - 12ns 61.1ns 90% 10% 15ns over Valid Data Valid Data Valid Data 20ns over Figure 2. GPS Receive ADC Timing SPI_STB 50ns over 50ns over SPI_STROBE Setup Time SPI_STROBE Hold Time 0.6 - 10us SPI_CLK SPI_DATA 50ns over Clock Duty : 35 - 65% Rising Time 25ns under Falling Time 25ns under 50ns over SPI_DATA Hold Time SPI_DATA Hold Time Valid Data Figure 3. 3-Line Serial Port Interface Timing 10 RX IF/BBA WITH GPS S1M8662A (Preliminary) FUNCTIONAL DESCRIPTION S1M8662A is a CDMA/GPS receive-only baseband analog IC, located between the RF mid-frequency processing terminal and baseband processing terminal. The RF analog mid-frequency signal terminal(IF SAW filter output), directly connected to the S1M8662A mid-frequency input pin, converts and processes the baseband signal and sends the corresponding digital signal to the modem IC. Baseband analog processing uses QPSK modulation, LPF, and A-D converter and the modem IC performs digital CDMA /GPS baseband modulation on the digitalized analog baseband signal it receives. An on-chip VCO creates a multiple frequency(x2, x3, x4, x6) LO signal. S1M8662A uses a 0.5um BiCMOS, equipped with high-frequency bipolar and low power standardized CMOS logic, to operate safely in the low power range, consisting of power voltage between 2.7 to 3.3V and operating temperature between -30 to +85°C. CDMA Receive Signal Path The receive circuit of S1M8662A has the Rx AGC, an automatic gain controller, and baseband LPF and output terminal with the A-D converter, and VCO and mixer etc. The input signal is received as a differential signal, which is modulated to 1.23 MHz spread-spectrum for CDMA. The mid-frequency is 220.38MHz for Korea-PCS, 1.23MHz for US-PCS, and 85.38MHz for cellular; they are set based on the time constants of the components involved with the external VCO and external Rx PLL. Rx AGC , connected to both the IF SAW filter and matching component in the RF-IF converter output located in the RF block, amplifies or reduces according to the signal size. It takes its orders from the modem chip when it sets the appropriate receive level as required by the CDMA system. Gain is controlled by applying a DC voltage to the RAGC_CONT pin. The applied DC is produced when the PDM signal, generated as a control signal in the modem, passes through the R-C filter. The control band of this AGC is approx. 90dB. The QPSK Baseband modulator separates and modulates the IF signal sent by the AGC using I(In-phase) and Q(Quad-phase) baseband signal. Essentially, two signals, I-LO and Q-LO (Local oscillator), are mixed with AGC's IF output signals, respectively. The LO(local oscillator) signal is generated by the internal oscillating components, externally connected tank coil, and Varactor, and the externally independent PLL device is used to generate its exact oscillation mid-frequency. T=0 Q-CH I-CH Figure 4. Received I/Q Phase in S1M8662A Defining of the I-Phase and Q-Phase receive path is very important to its design. The polarities of these paths are also important to digital baseband modulation. Therefore, the output of the QPSK baseband modulation determines the I and Q phases; I-phase is defined as the phase leading the Q-phase by exactly 90°, but it simpler to think of I as Cosin and Q as Sin. The figure related to this is shown in Figure 5. This definition is valid only when the QPSK IF input signal is higher than the IF mid-frequency. The baseband signal, output by the QPSK modulator, includes various other unnecessary surrounding band noises, which are removed by the use of the LPF(Low-Pass-Filter). Ultimately, I and Q filtered signals are converted to digital signals by the 4-bit A-D converter and sent to the modem. The A-D converter used is a parallel output type and its outputs are synchronized at the CHIP×8 rising edge. The modem chip captures the data on the CHIP×8 falling edge. The CHIP×8 clock used in the A-D converter received to MSM. 11 S1M8662A (Preliminary) RX IF/BBA WITH GPS GPS Rx Signal Path The difference of the S1M8662A from the S1M8656A is that S1M8662A provides GPS receiving operation. While GPS receiving path shares function blocks with CDMA modes, it needs independent AGC and lowpass filter. GPS IF signal from GPS RF-IF mixer is applied to S1M8662A via GPS SAW filter. GPS IF is differential input pins. The operation of I/Q demodulator is the same in CDMA modes and the phase relation of I/Q signal of the output is the same as depicted in Figure 5. GPS lowpass filter of S1M8662A has its cut off frequency at around 800kHz. A-D converter, as output of GPS path, is the 4bit parallel converter which is the same one used in CDMA path. But the sampling frequency is different from that of CDMA mode. And in operating in GPS mode, sampling clock of A-D converter should be supplied from the modem. TCXO Clock Generator In S1M8656A and S1M8660A, the output of TCXO is divided by 1, 2, and 4 and then clocked out. But in S1M8662A the output of TCXO is just amplified and clocked out. So, there is no SPI control which controls the division ratio of TCXO clock. In this product, the TCXO_in pin can input both TCXO signal (TCXO_sig) and TCXO control (TCXO_cont) at the same time. S1M8662A Buffer C TCXO_sig 22 R x1 9 TCXO_out LPF TCXO_cont Figure 5. TCXO Clock Generating If TCXO_cont pin is held low or high-impedance (floating), TCXO_out keeps high, and on the contrary, if TCXO_cont pin is held high, TCXO_out outputs TCXO clock. If TCXO_cont pin is low or high-impedance (floating), S1M8662A can be pin to pin compatible with IFR3500 of Qualcomm. 12 RX IF/BBA WITH GPS S1M8662A (Preliminary) RX VOLTAGE CONTROLLED OSCILLATOR(VCO) S1M8662A includes the Rx LO block having the VCO and quad-phase generator. The quad-phase generator outputs I-phase and Q-phase clocks with 1/2, 1/3, 1/4 or 1/6 the VCO frequency and sends them to the QPSK modulator. The VCO buffer is used when the VCO output is sent to the external RX PLL. Although the allowable VCO frequency is determined based on an external time constant, it can only range between approx. 100MHz to 500MHz, suggesting that the maximum input IF frequency is 250MHz. Serial Port Interface(SPI) S1M8662A is equipped with the Serial I/F. All internal functions can be controlled through a common bus using an external controller. S1M8662A is designed to be completely compatible with MSM series of Qualcomm. Here, the modem is the master and S1M8662A the slave. Each pin which uses the SPI bus has the following common functions. • The STB(STROBE) for the serial bus start signal is used to initialize serial data transmission. • Serial BUS DATA is used for the bi-direction data input /output at serial data transmission. Because it is an open drain type pin, it requires the pull-up resistance of approx. 8kΩ. • Serial BUS CLK is used to synchronize the data input/output at serial data transmission. Serial Port Interface Operation The modem, the master, controls slaves such as S1M8662A using the SPI bus. The STB falling edge indicates the start of the serial I/F data transmission. The STB becomes high to mark the end of the data transmission. (Data sent after the STB turns high are not valid.) Serial line data is captured and stored as soon as the BBA or the MODEM places the clock on the falling edge. The SPI 3-line must remain high for at least 1-clock cycle in order to sent new data. The MSB always outputs the data line data. After 9-clocks, which is required to send data, the data line driver opens the data line, at which time the data line becomes high because of the external pull-up resistance. Serial Data Transfer format S1M8662A and S1M8657 are all slave devices with the SPI bus. What differentiate them from one another is their different device IDs. Each company has its own characteristic SPI bus configuration , but normally the 3-line bus is most often used and sometimes the 2-line bus such as the IIC bus. Figure 7. shows the serial data transfer format. 13 S1M8662A (Preliminary) RX IF/BBA WITH GPS STB CLK D5 D4 D3 D2 D1 D0 DATA Start bit mode=01 Master drive Slave Address Dummy 1=Master read D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Master drive Register Address Dummy D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Master drive Register Address Master drive data Slave drive data Dummy Dummy Dummy End bit 0=Master read Figure 6. Serial Data Transfer Format (1) The first 2-BITs are for transmission only and this product must send '01'.(Others are not permitted.) (2) The following 6-bit data specifies the slave device, which is connected to the SPI bus and has its own ID. (3) The following 1-bit is a dummy bit, which marks the end of the 8-bit data transmission and the beginning of the next data to be sent. (4) The following 1-bit decides on whether the master will drive the data line or the slave will. If this bit is '1', the master will drive , but if '0' the slave will drive the data line. (5) The following 7-bit data is the register address of the specified slave device; the 7-bits for an address allows 128 register addresses for slaves. (6) The following high 1-BIT data is a dummy data. (7) The following 8-BIT data is the data in the device to be driven. (8) The following 1-BIT data is a dummy data, which marks the end of the 8-bit data transmission and beginning of the next data to be sent. (9) The following 1-bit decides on whether the master will drive the data line or the slave will. If this bit is '1', the master will drive , but if '0' the slave will drive the data line. (10) The following 7-bit data is the register address of the specified slave device. (11) The following high 1-BIT data is a dummy data. (12) The following 8-BIT data is the data in the device to be driven. (Continous data transmission such as this can be ended with a 1-byte transmission or can be read/written repeatedly.) (13) After the last data is sent, the data line opens and becomes high; (14) the CLK continues for half the 1-clock cycle and then becomes high; (15) and the STB becomes high as soon as the clock becomes high and this marks the end of data transmission. 14 RX IF/BBA WITH GPS S1M8662A (Preliminary) Modes of Operation S1M8662A can be controlled by the SPI bus. Table 2 shows the various modes. Table 2. Mode control in the DC control mode Mode 0x03[1:0] BLOCK_CTL 0x06[7] VCO_CTL 0x052:0] FILTER_SEL CHIPx8 Sleep 00 X XXX All circuit are off CDMA idle(Rx) 01 0 100 CDMA Mode 1 111 CDMA Mode or 11 GPS idle(Rx) 01 or 11 CDMA Sot 10 0 100 All circuit are off except the VCO, VCO buffer GPS Slot 10 1 111 Not used 15 S1M8662A (Preliminary) RX IF/BBA WITH GPS CONTROL REGISTERS S1M8662A has various registers which can be programmed by the SPI bus. These registers have their own function which are described below. Table 3. S1M8660A Control Registers Register name Address R/W Default vale Description RESET 0x00 W - Reset. Reset S1M8662A and all the register values are returned to their default value. SPI_ID 0x01 R 0x1F BLOCK_CTL 0x03 R/W 0x8 FILTER_SEL. 0x05 R/W 0x1C. FILTER_SEL. Lowpass filter selection VCO_CTL 0x06 R/W 0x0B VCO_CTL. Controls the VCO operation and VCO output. SPI_ID. Each slave device has its own, independent code; S1M8662A code is 1E. BLOCK_CTL Decides on the S1M8662A operation mode. LO division ratio. Controls VCO output. W : MODEM is recorded in the S1M8662A register R : When S1M8662A sends data to the modem Table 4. Description of Control Registers 16 Address Name Type Bits Description 00(h) RESET W - When the master uses this register, the S1M8662A returns all the programmed register values to their initial value. 01(h) SPI_ID R [5:0] This read-only register is used to confirm the type of slave connected to the master. It is set to 1Eh and all S1M8662A has the same value. This is the ID absolutely required to differentiate the controller from the data, when there are many slaves connected to the SPI bus. RX IF/BBA WITH GPS S1M8662A (Preliminary) Table 4. Description Of Control Registers (Continued) Address Name Type Bits [7] Description Identifies the S1M8662A Default = 1 [6] 03(h) Block_CTL R/W [5:4] Default = 0, Reserved Registers IF LO Divider, Default = 00 00 : 2, 01 : 3 10 : 4, 11 : 6 [3] Default = 1, Reserved Registers [2] RXVCO_OUT2. Default = 1 1 : Singled Ended Output (RXVCO_OUT1 Active, RXVCO_OUT2 Off) 0 : Differential Output (RXVCO_OUT1, 2 Active) 05(h) FILT_SEL R/W [1:0] Mode. Default = 00 00 : Sleep, 01 : Receive 10 : Rx Slot, 11 : Receive [7:2] Default = 0001 11 Reserved Registers 06(h) VCO R/W [1:0] FILT_SEL Default = 00 00 : CDMA LPF 10 : GPS LPF [7] GPS_SEL Default = 0 0 : GPS Mode Disabled 1 : GPS Mode abled [6:3] Default = 0001 Reserved Registers [2] CCO_CTL Default = 0 0 : RX_VCO Low Drive 1 : RX_VCO Low Max [1] Default = 11. Reserved Registers 17 S1M8662A (Preliminary) RX IF/BBA WITH GPS CHARACTERISTIC GRAPH +1.5 +0.5 Relative Amplitude [dB] -1.5 -4.0 -46.0 -48.0 750K 800K 1.1M 1K 1.3M 1.7M Frequency [Hz] Figure 7. GPS Rx Low Pass Filter Mask 10 9 Phase Mismatch [deg] 8 7 6 Region of Acceptable Mismatch Performance 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1.0 Gain Mismatch [dB] Figure 8. GPS Rx Gain/Phase Mismatch Specification 18 1.2 1.4 RX IF/BBA WITH GPS S1M8662A (Preliminary) CHARACTERISTIC GRAPH (Continued) -30 Phase noise(dBc/Hz) -40 -50 -60 -70 -80 -90 -100 -110 -120 10 100 1K 10K 100K 1M Frequency offset(Hz) Figure 9. S1M8662A IF VCO Open Loop Phase Noise 19 S1M8662A (Preliminary) RX IF/BBA WITH GPS CHARACTERISTIC GRAPH (Continued) 100 90 Noise Figure [dB] 80 70 60 50 40 30 Region of Acceptable NF Performace 20 10 0 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 IF Input Power [dBm] Figure 10. GPS Rx Mode Noise Figure Specification 0 -10 Region of Acceptable IIP3 Performance IIP3 [dBm] -20 -30 -40 -50 -60 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 IF Input Power [dBm] Figure 11. GPS Rx Mode IIP3 Specification 20 -25 -20 -15 -10 RX IF/BBA WITH GPS S1M8662A (Preliminary) RXVCO_OUT2 RXVCO_OUT1 SPI_STB 19 20 18 1nF 1nF 10K 21 22 24 25 4-Bit DAC 23 10K 1nF 10uF 10uF 10uF Q_Outpu t SPI_DATA VDDM SPI_CLK TCXO_cont TCXO_in CHIPx8 VDDM VDDD VDDA TEST CIRCUIT 17 26 10nF 16 VDDA 14 29 30 12 31 11 10K 47pF 10K VIOffset 10K Vtune 1nF VQOffset VDDA 10nF 2.3nH 2.3nH 8 TCXO_out SPI_STB : Serial Interface Strobe SPI_CLK : Serial Interface Clock SPI_DATA : Serial Interface Data VDDA CDMA SW GPS VDDA 10nF 2pF 1:8 1K 2pF 2pF 1K 10nF 10nF 10nF 10nF 10nF 4.7K Vcont 7 9 6 10 5 GND SLUG 1:8 2pF VDDD VDDA 10nF 2 1 3 32 10nF I_Output 4-Bit DAC 13 S1M8662A 1pF 28 1SV279 10nF 15 4 VDDM 27 100nH 47pF Vif Figure 12. Test Circuit 21 S1M8662A (Preliminary) RX IF/BBA WITH GPS PACKAGE DIMENSION 32BCC+ Package Outline 5.00 + 0.10 5.00 + 0.10 5.00 + 0.10 #17 #25 #1 Index Laser Mark 0.075 + 0.025 #1 #9 0.80 MAX 0.30 + 0.1 0.50 + 0.1 0.40 + 0.1 0.45 + 0.1 #1 5.0 + 0.1 22 3.50 + 0.1 3.10 + 0.1 0.45 + 0.1