PIC17CXX EPROM Memory Programming Specification This document includes the programming specifications for the following devices: • PIC17C42 • PIC17C42A • PIC17CR42 1.0 Pin Diagram 40L PDIP, Windowed CERDIP • PIC17C43 • PIC17CR43 • PIC17C44 PROGRAMMING THE PIC17CXX For the convenience of a programmer developer, a “program & verify” routine is provided in the on-chip test program memory space, the program resides in ROM and not EPROM. Therefore, it is not erasable. The “program/verify” routine allows the user to load any address, program a location, verify a location or increment to the next location. It allows variable programming pulse width. 1.1 1 2 3 4 40 39 38 37 RD0/AD8 RD1/AD9 RD2/AD10 RD3/AD11 RC3/AD3 RC4/AD4 RC5/AD5 RC6/AD6 5 6 7 8 36 35 34 33 RD4/AD12 RD5/AD13 RD6/AD14 RD7/AD15 RC7/AD7 VSS 9 10 32 31 MCLR/VPP VSS RB0/CAP1 RB1/CAP2 RB2/PWM1 RB3/PWM2 11 12 13 14 30 29 28 27 RE0/ALE RE1/OE RE2/WR TEST RB4/TCLK12 RB5/TCLK3 RB6 RB7 15 16 17 18 26 25 24 23 RA0/INT RA1/T0CKI RA2 RA3 OSC1/CLKIN OSC2/CLKOUT 19 20 22 21 RA4/RX/DT RA5/TX/CK PIC17CXX The PIC17CXX is programmed using the TABLWT instruction. The table pointer points to the internal EPROM location start. Therefore, a user can program an EPROM location while executing code (even from internal EPROM). This programming specification applies to PIC17CXX devices in all packages. VDD RC0/AD0 RC1/AD1 RC2/AD2 Hardware Requirements The PIC17CXX requires two programmable power supplies, one for VDD (2.5V to 6.0V recommended) and one for VPP (13 ± 0.25V). Both supplies should have a minimum resolution of 0.25V. Since the PIC17CXX under programming is actually executing code from “boot ROM,” a clock must be provided to the part. Furthermore, the PIC17CXX under programming may have any oscillator configuration (EC, XT, LF or RC). Therefore, the external clock driver must be able to overdrive pulldown in RC mode. CMOS drivers are required since the OSC1 input has a Schmitt trigger input with levels (typically) of 0.2VDD and 0.8VDD. See the PIC17C4X data sheet (DS30412A) for exact specifications. The PIC17CXX uses an intelligent algorithm. The algorithm calls for program verification at VDDmin as well as VDDmax. Verification at VDDmin guarantees good “erase margin”. Verification at VDDmax guarantees good “program margin”. Three times (3X) additional pulses will increase program margin then beyond VDD (max.) and insure safe operation in user system. PIN DESCRIPTIONS (DURING PROGRAMMING): PIC17C42/42A/43/44 During Programming Pin Name Pin Name Pin Type RA <0:4> TEST RB <7:0> RC <7:0> MCLR/VPP VDD VSS RA <0:4> TEST PAD <15:8> PAD <7:0> VPP VDD VSS I I I/O I/O P P P Pin Description Necessary in programming mode Must be set to “high” to enter programming mode Address & data: high byte Address & data: low byte Programming Power Power Supply Ground Legend: I = Input, O = Output, P = Power 1996 Microchip Technology Inc. DS30139I-page 1 This document was created with FrameMaker 4 0 4 PIC17CXX The actual programming must be done with VDD in the VDDP range (4.75 - 5.25V). Note: VDDP=VDD range required during programming. VDD min.=minimum operating VDD spec for the part. All unused pins during programming are in high impedance state. VDD max.=maximum operating VCC spec for the part. PORTB (RB) has internal weak pull-ups which are active during the programming mode. When TEST pin is high, Power-up timer (PWRT) and Oscillator Start-up Timers (OST) are disabled. Programmers must verify the PIC17CXX at its specified VDDmax and VDDmin levels. Since Microchip may introduce future versions of the PIC17CXX with a broader VDD range, it is best that these levels are user selectable (defaults are ok). Note: 2.0 Program/Verify Mode 2.1 Any programmer not meeting these requirements may only be classified as "prototype" or "development" programmer but not a "production" quality programmer. The program/verify mode is intended for full-feature programmers. This mode offers the following capabilities: a) PROGRAM MODE ENTRY To execute the programming routine, the user must hold TEST pin high, RA2, RA3 must be low and RA4 must be high (after power-up) while keeping MCLR low and then raise MCLR pin from VIL to VDD or VPP. This will force FFE0h in the program counter and execution will begin at that location (the beginning of the boot code) following reset. Execution is forced to Internal mode by overriding the fuse configuration. The code protect bit is not overwritten. The program immediately polls PORT RB<7:0> to determine a branch address. Presenting E1h on PORT RB will cause the program to jump to and execute the “program/verify” routine. FIGURE 2-1: The OSC must not have 72 osc clocks while the device MCLR is between VIL and VIHH. b) c) d) e) Load any arbitrary 16-bit address to start program and/or verify at that location. Increment address to program/verify the next location. Allows arbitrary length programming pulse width. Following a “verify” allows option to program the same location or increment and verify the next location. Following a “program” allows options to program the same location again, verify the same location or to increment and verify the next location. PROGRAMMING/VERIFY STATE DIAGRAM Pulse RA1 Reset Jump to Program Routine Pulse RA1 Pulse RA1 Load Address Increment Address Pulse RA1 (Raise RA1 after RA0↓) Verify RA0↑ Raise RA1 before RA0↓ DS30139I-page 2 Program Pulse RA0 (RA0 pulse width is programming time) 1996 Microchip Technology Inc. EPROM Memory Programming Specification 2.1.1 LOADING NEW ADDRESS The program allows new address to be loaded right out of reset. A 16-bit address is presented on ports RB (high byte) and RC (low byte) and the RA1 is pulsed (0 → 1, then 1 → 0). The address is latched on the rising edge of RA1. See timing diagrams for details. After loading an address, the program automatically goes into a “verify cycle”. To load a new address at any time, the PIC17C4X must be reset and the programming mode re-entered. 2.1.2 VERIFY (OR READ) MODE “Verify mode” can be entered from “Load address” mode, “program mode” or “verify mode”. In verify mode pulsing RA1 will turn on PORTS RB and RC output drivers and output the 16-bit value from the current location. Pulsing RA1 again will increment location count and be ready for the next verify cycle. Pulsing RA0 will begin a program cycle. FIGURE 2-2: 0000 2.1.3 PROGRAM CYCLE “Program cycle” is entered from “verify cycle” or program cycle” itself. After a verify, pulsing RA0 will begin a program cycle. 16-bit data must be presented on PORTS RB (high byte) and RC (low byte) before RA0 is raised. The data is sampled 3 TCY cycles after the rising edge of RA0. Programming continues for the duration of RA0 pulse. At the end of programming the user can choose one of three different routes. If RA1 is kept low and RA0 is pulsed again, the same location will be programmed again. This is useful for applying over programming pulses. If RA1 is raised before RA0 falling edge, then a verify cycle is started without address increment. Raising RA1 after RA0 goes low will increment address and begin verify cycle on the next address. PIC17C4X PROGRAM MEMORY MAP On chip Program EPROM FOSC0 FE00 FOSC1 FE01 WDTPS0 FE02 WDTPS1 FE03 PM0 FE04 Reserved FE05 PM1 FE06 Reserved FE07 Reserved FE08 Reserved FE09 PM2* FE0F 07FF FE00 FE0F Configuration Word FFFF *This location does not exist for PIC17C42 1996 Microchip Technology Inc. DS30139I-page 3 PIC17CXX 3.0 PROGRAMMING SPECIFICATIONS FIGURE 3-1: PROGRAMMING ROUTINE FLOWCHART Reset No RA2 = 0 RA3 = 0 RA4 = 1 RA1 =0 Yes No MCLR = 1 B port = 0xE1 (hold for 10 Tcy) RA1 =1 Yes Present address on ports RB, RC hold Tcy after RA1 changes to 1 No RA1 =0 Yes No RA1 =0 Yes No Read MSB of data from port-B. Read LSB of data from port-C. Enable RA0 to end prog cycle B & C ports not driven by part If programming is desired, force port B = MSB of data force port C = LSB of data (hold 10Tcyc after RA0 is raised) RA1 =1 Program 16 bit data Yes No Yes RA0 = 0 Yes RA1 =0 Stop driving address on port Yes Yes No RA0= 1 No RA1 =1 Yes No No Yes No RA0= 1 No RA1 =0 Increment Address RA1 =1 Yes No RA1 =1 B port = xxx - B port is forced by the part B port = xxx - B port is tri-state, should be forced by user Yes B port = MSB of Data C port = LSB of Data Min RA1 high or low = 10 Tcy DS30139I-page 4 1996 Microchip Technology Inc. EPROM Memory Programming Specification FIGURE 3-2: RECOMMENDED PROGRAMMING ALGORITHM FOR USER EPROM Start Load new address Pulse-count = 0 Set VDD = VDD min Verify blank Pass Blank check? No Issue "Blank check fail" error message Yes Load new data Programming error: Issue error message “Fail verify verify @ @ VVDD DDmin/max” min/max" "Fail Set VDD = VDDmin Set VDD = VDDP Yes Program using 100µs pulse increment pulse-count Pass? No Set DDmax Set VDD = VDD max. Verify location(s) Verify location for correct data Yes Pass? SetVVDD DD = = VVDD DDmin min Set Verify location Apply (3 x Pulse-count) more 100 µs programming pulses for margin (Over programming) No No Pulsecount >25 Location fails programming, issue error message "Unable to program location" 1996 Microchip Technology Inc. DS30139I-page 5 PIC17CXX FIGURE 3-3: RECOMMENDED PROGRAMMING ALGORITHM FOR CONFIGURATION WORDS Start Load new address Pulse-count = 0 Set VDD = VDDmin Verify blank Pass Blank check? No Issue “blank check fail” error message Yes Load new data Programming error: Issue error message “Fail verify @ VDDmin/max” Set VDD = VDDmin Set VDD = VDDP Yes Program using 100 µs pulse increment pulse-count Yes Pass? No Set VDD = VDDmax Verify location(s) Pulse count <100 No Verify location for correct data SetVVDD==VVDDmin min Set DD DD Verify location Yes Pass? No Location fails programming, issue error message “Unable to program location” DS30139I-page 6 1996 Microchip Technology Inc. EPROM Memory Programming Specification 4.0 CONFIGURATION WORD (PORTC). PAD<15:8> (PORTB) will be set to 0xFF. Reading a configuration location between 0xFE08 and 0xFE0F will place the high byte of the configuration word into PAD<7:0> (PORTC). PAD<15:8> (PORTB) will be set to 0xFF. Configuration bits are mapped into program memory. Each bit is assigned one memory location. In erased condition a bit will read as '1'. To program a bit, the user needs to write to the memory address. The data is immaterial; the very act of writing will program the bit. The configuration word locations are shown in Table 4-3. The programmer should not program the reserved locations to avoid unpredictable results and to be compatible with future variations of the PIC17C4X. It is also mandatory that configuration locations are programmed in the strict order starting from the first location (0xFE00) and ending with the last (0xFE0F). Unpredictable results may occur if the sequence is violated. TABLE 4-1: Reading Configuration Word 4.1 The PIC17CXX has seven configuration locations (see Table 4-1). These locations can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. Any write to a configuration location, regardless of the data, will program that configuration bit. Reading any configuration location between 0xFE00 and 0xFE07 will place the low byte of the configuration word (see Table 4-2) into PAD<7:0> TABLE 4-2: Bit Address FOSC0 0xFE00 FOSC1 0xFE01 WDTPS0 0xFE02 WDTPS1 0xFE03 PM0 0xFE04 PM1 0xFE06 † 0xFE0F PM2 †This CONFIGURATION BIT PROGRAMMING LOCATIONS location does not exist on the PIC17C42. READ MAPPING OF CONFIGURATION BITS 15 1 14 1 13 12 11 8 5 1 1 1 7 — 6 1 10 1 9 1 PM1 — 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 PM2* 6 — 5 — 4 3 2 1 0 PM0 WDTPS1 WDTPS0 FOSC1 FOSC0 4 — 3 — 2 — 1 — 0 — —=Unused PM<2:0>, Processor Mode Select bits 111 = Microprocessor mode 110 = Microcontroller mode 101 = Extended Microcontroller mode 000 = Code protected microcontroller mode WDTPS<1:0>, WDT Prescaler Select bits. 11 = WDT enabled, postscaler = 0 10 = WDT enabled, postscaler = 256 01 = WDT enabled, postscaler = 64 00 = WDT disabled, 16-bit overflow timer FOSC<1:0>, Oscillator Select bits 11 = EC oscillator 10 = XT oscillator 01 = RC oscillator 00 = LF oscillator * This bit does not exist on PIC17C42. 1996 Microchip Technology Inc. DS30139I-page 7 PIC17CXX 4.2 Embedding Configuration Word Information in the Hex File To allow portability of code, a PIC17C4X programmer is required to read the configuration word locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, all configuration word information must be included. An option to not include the configuration word information may be provided. When embedding configuration word information in the hex file, it should be to address FE00h. Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer. TABLE 4-3: CONFIGURATION WORD PIC17C42 To code protect: • Protect all memory XXXXXXXXX0X0XXXX Program Memory Segment Configuration Word (0xFE00) All memory PIC17C42A To code protect: • Protect all memory Configuration Word (0xFE00) All memory Configuration Word (0xFE00) All memory Configuration Word (0xFE00) All memory Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled R/W in Protected Mode Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled R/W in Protected Mode Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled 0XXXXXXX0X0XXXX Program Memory Segment Configuration Word (0xFE00) All memory PIC17C44 To code protect: • Protect all memory R/W in Protected Mode 0XXXXXXX0X0XXXX Program Memory Segment PIC17CR43 To code protect: • Protect all memory Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled 0XXXXXXX0X0XXXX Program Memory Segment PIC17C43 To code protect: • Protect all memory Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode 0XXXXXXXX0X0XXXX Program Memory Segment PIC17CR42 To code protect: • Protect all memory R/W in Protected Mode R/W in Protected Mode Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled 0XXXXXXX0X0XXXX Program Memory Segment Configuration Word (0xFE00) All memory R/W in Protected Mode Read Scrambled, Write Enabled Read Scrambled, Write Disabled* R/W in Unprotected Mode Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled Legend: X = Don’t care *Write to on-chip EPROM memory is disabled. The only way these locations can be programmed is if a TABLWT instruction is issued from an “on-chip” program memory space to program an on-chip memory location. DS30139I-page 8 1996 Microchip Technology Inc. EPROM Memory Programming Specification 4.3 CHECKSUM COMPUTATION The checksum is calculated by summing the following: • The contents of all program memory locations • The configuration word, appropriately masked • Masked ID locations (when applicable) The least significant 16 bits of this sum is the checksum. The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. Note that some older devices have an additional value added in the checksum. This is to maintain compatibility with older device programmer checksums. TABLE 4-4: Device PIC17C42 PIC17C42A PIC17CR42 PIC17C43 PIC17CR43 PIC17C44 CHECKSUM COMPUTATION Code Protect MP mode MC mode EMC mode PMC mode MP mode MC mode EMC mode PMC mode MP mode MC mode EMC mode PMC mode MP mode MC mode EMC mode PMC mode MP mode MC mode EMC mode PMC mode MP mode MC mode EMC mode PMC mode Checksum* SUM[0x000:0x7FF] + CFGW & 0x005F + 0xFFA0 SUM[0x000:0x7FF] + CFGW & 0x005F + 0xFFA0 SUM[0x000:0x7FF] + CFGW & 0x005F + 0xFFA0 SUM_XNOR8[0x000:0x7FF] + CFGW & 0x005F + 0xFFA0 SUM[0x000:0x7FF] + CFGW & 0x015F SUM[0x000:0x7FF] + CFGW & 0x015F SUM[0x000:0x7FF] + CFGW & 0x015F SUM_XNOR8[0x000:0x7FF] + CFGW & 0x015F SUM[0x000:0x7FF] + CFGW & 0x015F SUM[0x000:0x7FF] + CFGW & 0x015F SUM[0x000:0x7FF] + CFGW & 0x015F SUM_XNOR8[0x000:0x7FF] + CFGW & 0x015F SUM[0x000:0xFFF] + CFGW & 0x015F SUM[0x000:0xFFF] + CFGW & 0x015F SUM[0x000:0xFFF] + CFGW & 0x015F SUM_XNOR8[0x000:0xFFF] + CFGW & 0x015F SUM[0x000:0xFFF] + CFGW & 0x015F SUM[0x000:0xFFF] + CFGW & 0x015F SUM[0x000:0xFFF] + CFGW & 0x015F SUM_XNOR8[0x000:0xFFF] + CFGW & 0x015F SUM[0x000:0x1FFF] + CFGW & 0x015F SUM[0x000:0x1FFF] + CFGW & 0x015F SUM[0x000:0x1FFF] + CFGW & 0x015F SUM_XNOR8[0x000:0x1FFF] + CFGW & 0x015F Blank Value 0xC0DE at 0 and max address 0xF7FF 0xF7EF 0xF7BF 0xF7AF 0xF95F 0xF94F 0xF91F 0xF80F 0xF95F 0xF94F 0xF91F 0xF80F 0xF15F 0xF14F 0xF11F 0xF00F 0xF15F 0xF14F 0xF11F 0xF00F 0xE15F 0xE14F 0xE11F 0xE00F 0x79BD 0x79AD 0x797D 0xBB73 0x7B1D 0x7B0D 0x7ADD 0xBBD3 0x7B1D 0x7B0D 0x7ADD 0xBBD3 0x731D 0x730D 0x72DD 0xB3D3 0x731D 0x730D 0x72DD 0xB3D3 0x631D 0x630D 0x62DD 0xA3D3 Legend: CFGW = Configuration Word SUM[a:b] = [Sum of locations a to b inclusive] SUM_XNOR8(a:b) = [Sum of 8-bit wide XNOR copied into upper and lower byte, of locations a to b inclusive] *Checksum = [Sum of all the individual expressions] MODULO [0xFFFF] + = Addition & = Bitwise AND 1996 Microchip Technology Inc. DS30139I-page 9 PIC17CXX 5.0 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE Standard Operating Conditions Operating Temperature: Operating Voltage: +10°C ≤ TA ≤ +70°C, unless otherwise stated, (25°C is recommended) 4.5V ≤ VDD ≤ 5.25V, unless otherwise stated. Parameter No. Sym. Characteristic Min. Typ. Max. Units PD1 VDDP 4.75 5.0 5.25 V PD2 IDDP 50 mA PD3 VDDV Supply voltage during programming Supply current during programming Supply voltage during verify V PD4 VPP VDD max. 13.25 PD6 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 Note 1: Note 2: Note 3: VDD min. 12.75 Conditions/Comments Freq = 10MHz, VDD = 5.5V Note 3 Note 2 Voltage on VPP/MCLR pin V Note 1 during programming IPP Programming current on 25 50 mA Note 3 VPP/MCLR pin FOSCP Osc/clockin frequency dur4 10 MHz ing programming TCY Instruction cycle 1 0.4 µs TCY = 4/FOSCP TirV2tsH RA0, RA1, RA2, RA3, RA4 1 µs setup before TEST↑ TtsH2mcH TEST↑ to MCLR↑ 1 µs TbcV2irH RC<7:0>, RB<7:0> valid to 0 µs RA1 or RA0↑ :Address/Data input setup time µs 10 TCY TirH2bcl RA1 or RA0↑ to RB<7:0>, RC<7:0> invalid ; Address data hold time; T0ckiL2rbc RT↓ to RB<7:0>, RC<7:0> 8 TCY Z high impedance T0ckiH2bcV RA1↑ to data out valid 10 TCY Tprog Programming pulse width 10 100 1000 µs TirH2irL RA0, RA1 high pulse width 10 TCY µs TirL2irH RA0, RA1 low pulse width 10 TCY µs T0ckiV2inL RA1↑ before INT↓ (to go 0 µs from prog cycle to verify w/o increment) 10 TCY µs TinL2rtl RA1 valid after RA0 (to select increment or no increment going from program to verify cycle µs Note 1 Tvpps VPP setup time before RA0↑ 100 Tvpph VPP hold time after INT↓ 0 µs Note 1 TvdV2tsH VDD stable to TEST↑ 10 ms TrbV2mcH RB input (E1h) valid to VPP/ 0 µs MCLR↑ TmcH2rbI RB input (E1h) hold after ns 10 TCY VPP/MCLR↑ TvpL2vdL VDD power down after VPP 10 ms power down VPP/MCLR pin must only be equal to or greater than VDD at times other than programming. Program must be verified at the minimum and maximum VDD limits for the part. These parameters are for design guidance only and are not tested nor characterized. DS30139I-page 10 1996 Microchip Technology Inc. 1996 Microchip Technology Inc. RC<7:0> trbV2mcH tmcH2rbL P18 ttsH2mcH Load address X ADDR_LO ADDR_HI P8 tra1L2bcZ INC ADDR Verify location X Increment address to X + 1 by pulsing RA1 DATA_LO OUT DATA_HI OUT P7 tirL2lrH tra1H2bcV tirH2lrL P10 P11 tbcV2irH Verify location X + 1 DATA_LO OUT DATA_HI OUT tprog P9 P6 tirH2bcI Program location X + 1 Do not increment PC by raising RA1 before RA0↓ P5 DATA_LO_IN DATA_HI_IN tvpps P14 P15 Note: RA2 = 0 RA3 = 0 RA4 = 1 Programming Mode entry E1H Jump Address Input P17 RB<7:0> RA0 RA1 P4 tirV2tsH P3 5V 13V tvppH Verify location X + 1 DATA_LO OUT DATA_HI OUT FIGURE 5-1: VPP/MCLR Test EPROM Memory Programming Specification PROGRAMMING AND VERIFY TIMINGS I DS30139I-page 11 DS30139I-page 12 RC<7:0> RB<7:0> RA0 RA1 Note: RA2 = 0 RA3 = 0 RA4 = 1 Programming mode entry E1H Jump Address Input 13V 5V Load address X ADDR_LO ADDR_HI Verify location X DATA_LO OUT DATA_HI OUT P14 tvpps DATA_LO_IN DATA_HI_IN Program location X DATA_LO_IN DATA_HI_IN P9 tprog P9 tprog P9 Program location X Move to verify cycle Prevent increment of PC by raising RA1 before RA0↓ DATA_LO_IN DATA_HI_IN tprog P15 tvppH Verify location X DATA_LO OUT DATA_HI OUT FIGURE 5-2: VPP/MCLR Test PIC17CXX PROGRAMMING AND VERIFY TIMINGS II 1996 Microchip Technology Inc. 1996 Microchip Technology Inc. Note: Device in PGM mode Test = +5 VPP/MCLR = VPP RA2 = 0 RA3 = 0 RA4 = 1 Program location X Do not increment PC Raise RA1 before RA0↓ to do this DATA_LO IN DATA_LO OUT RC<7:0> Verify location X DATA_HI IN DATA_HI OUT P12 RB<7:0> INC PC tra1V2inL Verify location X DATA_LO OUT DATA_HI OUT tinL2ra1l Program location X Raise RA1 after RA0↓ to increment to location X +1 DATA_LO IN DATA_HI IN INC PC P13 Verify location X +1 Pulse RA1 to increment address to X +2 DATA_LO OUT DATA_HI OUT INC PC Verify location X +2 DATA_LO OUT DATA_HI OUT FIGURE 5-3: RA0 RA1 P13 tinL2ra1l EPROM Memory Programming Specification PROGRAMMING AND VERIFY TIMINGS III DS30139I-page 13 PIC17CXX FIGURE 5-4: POWER-UP/DOWN SEQUENCE FOR PROGRAMMING tvpL2vcL P19 VDD tvcV2tsH P16 VPP/MCLR TEST RA4 RA2 RA3 RA0 P3 tirV2tsH RB<7:0> trbV2mcH P17 E1H P18 tmcH2rbI DS30139I-page 14 1996 Microchip Technology Inc. EPROM Memory Programming Specification NOTES: 1996 Microchip Technology Inc. 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Suite 150 Two Prestige Place Miamisburg, OH 45342 Tel: 513 291-1654 Fax: 513 291-9175 Los Angeles Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92715 Tel: 714 263-1888 Fax: 714 263-1338 ASIA/PACIFIC Hong Kong Microchip Technology Rm 3801B, Tower Two Metroplaza, 223 Hing Fong Road, Kwai Fong, N.T., Hong Kong Tel: 852 2 401 1200 Fax: 852 2 401 3431 Korea Microchip Technology 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku, Seoul, Korea Tel: 82 2 554 7200 Fax: 82 2 558 5934 Singapore Microchip Technology 200 Middle Road #10-03 Prime Centre Singapore 188980 Tel: 65 334 8870 Fax: 65 334 8850 Taiwan Microchip Technology 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886 2 717 7175 Fax: 886 2 545 0139 JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81 45 471 6166 Fax: 81 45 471 6122 5/10/96 All rights reserved. 1996, Microchip Technology Incorporated, USA. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS30139I - page 16 1996 Microchip Technology Inc.