MICROCHIP PIC16C50X

PIC16C50X
EPROM Memory Programming Specification
1.2
This document includes the programming
specifications for the following devices:
Programming Mode
• PIC16C505
The Programming mode for the PIC16C50X allows
programming of user program memory, and the configuration word for the PIC16C50X.
1.0
Pin Diagram
PROGRAMMING THE
PIC16C50X
PDIP, SOIC, Windowed CERDIP
1.1
VDD
RB5/OSC1/CLKIN
RB4/OSC2/CLKOUT
RB3/MCLR/VPP
RC5/T0CKI
RC4
RC3
Hardware Requirements
1
2
3
4
5
6
7
PIC16C505
The PIC16C50X can be programmed using a serial
method. Due to this serial programming, the
PIC16C50X can be programmed while in the user’s
system, increasing design flexibility. This programming
specification applies to PIC16C50X devices in all
packages.
14
13
12
11
10
9
8
VSS
RB0
RB1
RB2
RC0
RC1
RC2
The PIC16C50X requires two programmable power
supplies, one for VDD (2.0V to 6.5V recommended) and
one for VPP (12V to 14V). Both supplies should have a
minimum resolution of 0.25V.
TABLE 1-1:
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16C50X
During Programming
Pin Name
Pin Name
Pin Type
Pin Description
RB1
CLOCK
I
RB0
DATA
I/O
Clock Input
RB3/MCLR/VPP
VPP
P
VDD
VDD
P
Power Supply
VSS
VSS
P
Ground
Data Input/Output
Programming Power
Legend: I = Input, O = Output, P = Power
 2001 Microchip Technology Inc.
DS30603B-page 1
PIC16C50X
2.0
PROGRAM MODE ENTRY
The Program/Verify Test mode is entered by holding
pins RB0 and RB1 low, while raising MCLR pin from VIL
to VIHH. Once in this Test mode, the user program
memory and the test program memory can be
accessed and programmed in a serial fashion. The first
selected memory location is the configuration word.
RB0 and RB1 are Schmitt Trigger inputs in this
mode.
Incrementing the PC once (using the increment
address command) selects location 0x000 of the regular program memory. Afterwards, all other memory
locations from 0x001-03FF can be addressed by incrementing the PC.
If the program counter has reached the last user program location and is incremented again, the on-chip special EPROM area will be addressed. (See Figure 2-2 to
determine where the special EPROM area is located for
the various PIC16C50X devices.)
2.1
Programming Method
The programming technique is described in the following section. It is designed to guarantee good programming margins. It does, however, require a variable
power supply for VCC.
2.1.1
6.
Verify all locations at VDD = VDDMAX.
VDDMIN is the minimum operating voltage spec.
for the part. VDDMAX is the maximum operating
voltage spec. for the part.
2.1.2
Clearly, to implement this technique, the most stringent
requirements will be that of the power supplies:
VPP: VPP can be a fixed 13.0V to 13.25V supply. It must
not exceed 14.0V to avoid damage to the pin and
should be current limited to approximately 100mA.
VDD: 2.0V to 6.5V with 0.25V granularity. Since this
method calls for verification at different VDD values, a
programmable VDD power supply is needed.
Current Requirement: 40 mA maximum
Microchip may release devices in the future with different VDD ranges which make it necessary to have a programmable VDD.
It is important to verify an EPROM at the voltages
specified in this method to remain consistent with
Microchip's test screening. For example, a PIC16C50X
specified for 4.5V to 5.5V should be tested for proper
programming from 4.5V to 5.5V.
Note:
PROGRAMMING METHOD DETAILS
Essentially, this technique includes the following steps:
1.
2.
a)
b)
Perform blank check at VDD = VDDMIN. Report
failure. The device may not be properly erased.
Program location with pulses and verify after each
pulse at VDD = VDDP: where VDDP = VDD range
required during programming (4.5V - 5.5V).
Programming condition:
VPP = 12.75V to 13.25V
VDD = VDDP = 4.5V to 5.5V
VPP must be ≥ VDD + 7.25V to keep
“Programming mode” active.
Verify condition:
VDD = VDDP
VPP ≥ VDD + 7.5V but not to exceed 13.25V
If location fails to program after “N” pulses (suggested maximum program pulses of 8), then
report error as a programming failure.
Note:
3.
4.
5.
Device must be verified at minimum and
maximum specified operating voltages as
specified in the data sheet.
Once location passes ‘Step 2’, apply 11X overprogramming, i.e., apply 11 times the number of
pulses that were required to program the location. This will insure a solid programming margin. The overprogramming should be made
“software programmable” for easy updates.
Program all locations.
Verify all locations (using Speed Verify mode) at
VDD = VDDMIN.
DS30603B-page 2
SYSTEM REQUIREMENTS
2.1.3
Any programmer not meeting the programmable VDD requirement and the verify at
VDDMAX and VDDMIN requirement, may
only be classified as a “prototype” or
“development” programmer, but not a
production programmer.
SOFTWARE REQUIREMENTS
Certain parameters should be programmable (and
therefore, easily modified) for easy upgrade.
a)
b)
c)
2.2
Pulse width.
Maximum number of pulses, present limit 8.
Number of over-programming pulses: should be
= (A • N) + B, where N = number of pulses
required in regular programming. In our current
algorithm A = 11, B = 0.
Programming Pulse Width
Program Memory Cells: When programming one
word of EPROM, a programming pulse width (TPW) of
100 µs is recommended.
The maximum number of programming attempts
should be limited to 8 per word.
After the first successful verify, the same location should
be over-programmed with 11X over-programming.
Configuration Word: The configuration word for oscillator selection, WDT (Watchdog Timer) disable and
code protection, and MCLR enable, requires a
programming pulse width (TPWF) of 10 ms. A series of
100 µs pulses is preferred over a single 10 ms pulse.
 2001 Microchip Technology Inc.
PIC16C50X
FIGURE 2-1:
PROGRAMMING METHOD FLOW CHART
Start
Blank Check
@ VDD = VDDMIN
Report Possible Erase Failure
Continue Programming
at user’s option
No
Pass?
Report Programming Failure
Yes
Yes
Program 1 Location
@ VPP = 12.75V to 13.25V
VDD = VDDP
No
Pass?
No
N > 8?
N=N+1
(N = # of program pulses)
Yes
Increment PC to point to
next location, N = 0
Apply 11N additional
program pulses
No
All
locations
done?
Yes
Verify all locations
@ VDD = VDDMIN
No
Pass?
Report verify failure
@ VDDMIN
Yes
Verify all locations
VDD
max.
@VDD
VDD= =
VDDMAX
No
Pass?
Report verify failure
@ VDDMAX
Yes
Now program
Configuration Word
Verify Configuration Word
@ VDDMAX & VDDMIN
Done
 2001 Microchip Technology Inc.
DS30603B-page 3
PIC16C50X
FIGURE 2-2:
PIC16C50X SERIES PROGRAM MEMORY MAP IN PROGRAM/VERIFY MODE
Address 11
(HEX) 000
NNN
Bit Number
0
User Program Memory
(NNN + 1) x 12 bit
TTT
0
0
ID0
TTT + 1
0
0
0
0
ID1
ID2
0
0
ID3
TTT + 2
TTT + 3
For Customer Use
(4 x 4 bit usable)
For Factory Use
TTT + 3F
(FFF)
Configuration Word 5 bits
NNN Highest normal EPROM memory address. NNN = 0x3FF for PIC16C505.
Note that some versions will have an oscillator calibration value programmed at NNN.
TTT Start address of special EPROM area and ID locations.
2.3
Special Memory Locations
2.3.1
CUSTOMER ID CODE LOCATIONS
The highest address of program memory space is
reserved for the internal RC oscillator calibration value.
This location should not be overwritten except when
this location is blank, and it should be verified, when
programmed, that it is a MOVLW XX instruction.
Per definition, the first four words (address TTT to
TTT + 3) are reserved for customer use. It is recommended that the customer use only the four lower order
bits (bits 0 through 3) of each word and filling the eight
higher order bits with ’0’s.
The ID Locations area is only enabled if the device is in
Programming/Verify mode. Thus, in normal operation
mode, only the memory location 0x000 to 0xNNN will
be accessed and the Program Counter will just rollover
from address 0xNNN to 0x000 when incremented.
A user may want to store an identification code (ID) in
the ID locations and still be able to read this code after
the code protection bit was programmed.
The configuration word can only be accessed immediately after MCLR, going from VIL to VHH. The Program
Counter will be set to all ’1’s upon MCLR = VIL. Thus,
it has the value “0xFFF” when accessing the configuration EPROM. Incrementing the Program Counter once
causes the Program Counter to rollover to all '0's.
Incrementing the Program Counter 4K times after
RESET (MCLR = VIL) does not allow access to the
configuration EPROM.
EXAMPLE 2-1:
The Customer ID code “0xD1E2” should be stored in
the ID locations 400-403 like this:
400:
401:
402:
403:
0000
0000
0000
0000
0000
0000
0000
0000
1101
0001
1110
0010
Reading these four memory locations, even with the
code protection bit programmed, would still output on
PORTA the bit sequence “1101”, “0001”, “1110”,
“0010” which is “0xD1E2”.
Note:
DS30603B-page 4
CUSTOMER CODE 0xD1E2
All other locations in PICmicro® configuration memory are reserved and should not
be programmed.
 2001 Microchip Technology Inc.
PIC16C50X
2.4
2.4.1
Program/Verify Mode
The RB1 pin is used as a clock input pin, and the RB0
pin is used for entering command bits and data input/
output during serial operation. To input a command, the
clock pin (RB1) is cycled six times. Each command bit
is latched on the falling edge of the clock with the least
significant bit (LSb) of the command being input first.
The data on pin RB0 is required to have a minimum
setup and hold time (see AC/DC specs), with respect to
the falling edge of the clock. Commands that have data
associated with them (read and load) are specified to
have a minimum delay of 1µs between the command
and the data. After this delay the clock pin is cycled 16
times with the first cycle being a START bit and the last
cycle being a STOP bit. Data is also input and output
LSb first. Therefore, during a read operation, the LSb
will be transmitted onto pin RB0 on the rising edge of
the second cycle, and during a load operation, the LSb
will be latched on the falling edge of the second cycle.
A minimum 1µs delay is also specified between consecutive commands.
The Program/Verify mode is entered by holding pins
RB1 and RB0 low, while raising MCLR pin from VIL to
VIHH (high voltage). Once in this mode, the user program memory and the configuration memory can be
accessed and programmed in serial fashion. The mode
of operation is serial, and the memory that is accessed
is the user program memory. RB0 and RB1 are Schmitt
Trigger inputs in this mode.
The sequence that enters the device into the Programming/Verify mode places all other logic into the RESET
state (the MCLR pin was initially at VIL). This means
that all I/O are in the RESET state (High impedance
inputs).
Note:
PROGRAM/VERIFY OPERATION
The MCLR pin should be raised from VIL to
VIHH within 9 ms of VDD rise. This is to
ensure that the device does not have the
PC incremented while in valid operation
range.
All commands are transmitted LSb first. Data words are
also transmitted LSb first. The data is transmitted on
the rising edge and latched on the falling edge of the
clock. To allow for decoding of commands and reversal
of data pin configuration, a time separation of at least
1µs is required between a command and a data word
(or another command).
The commands that are available are listed in Table 2-1.
TABLE 2-1:
COMMAND MAPPING
Command
Note:
Mapping (MSb ... LSb)
Data
Load Data
0
0
0
0
1
0
0, data(14), 0
Read Data
0
0
0
1
0
0
0, data(14), 0
Increment Address
0
0
0
1
1
0
Begin programming
0
0
1
0
0
0
End Programming
0
0
1
1
1
0
The clock must be disabled during in-circuit programming.
 2001 Microchip Technology Inc.
DS30603B-page 5
PIC16C50X
2.4.1.1
Load Data
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSb’s of the data word are ignored. A timing diagram for the load data command is shown in
Figure 5-1.
2.4.1.2
Read Data
After receiving this command, the chip will transmit
data bits out of the memory currently accessed, starting
with the second rising edge of the clock input. The RB0
pin will go into output mode on the second rising clock
edge, and it will revert back to input mode (hiimpedance) after the 16th rising edge. A timing
diagram of this command is shown in Figure 5-2.
2.4.1.3
Increment Address
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 5-3.
2.4.1.4
Begin Programming
A load data command must be given before every
begin programming command. Programming of the
appropriate memory (test program memory or user program memory) will begin after this command is
received and decoded. Programming should be performed with a series of 100µs programming pulses. A
programming pulse is defined as the time between the
begin programming command and the end programming command.
2.4.1.5
2.5
Programming Algorithm Requires
Variable VDD
The PIC16C50X uses an intelligent algorithm. The
algorithm calls for program verification at VDDMIN, as
well as VDDMAX. Verification at VDDMIN insures good
“erase margin”. Verification at VDDMAX insures good
“program margin”.
The actual programming must be done with VDD in the
VDDP range (4.75 - 5.25V).
VDDP
= VCC range required during programming.
VDDMIN
= minimum operating VDD spec for the part.
VDDMAX = maximum operating VDD spec for the part.
Programmers must verify the PIC16C50X at its specified VDDMAX and VDDMIN levels. Since Microchip may
introduce future versions of the PIC16C50X with a
broader VDD range, it is best that these levels are user
selectable (defaults are ok).
Note:
Any programmer not meeting these
requirements may only be classified as a
“prototype” or “development” programmer,
but not a “production” quality programmer.
End Programming
After receiving this command, the chip stops programming the memory (configuration program memory or
user program memory) that it was programming at the
time.
DS30603B-page 6
 2001 Microchip Technology Inc.
PIC16C50X
3.0
CONFIGURATION WORD
The PIC16C50X family members have several configuration bits. These bits can be programmed (reads ’0’),
or left unprogrammed (reads ’1’), to select various
device configurations. Figure 3-1 provides an overview
of configuration bits.
FIGURE 3-1:
CONFIGURATION WORD BIT MAP
Bit Number:
11
10
9
8
7
6
5
4
3
2
1
CP CP CP CP CP CP MCLRE CP WDTE FOSC2 FOSC1
0
FOSC0
Register:
Address
CONFIG
0FFFh
bit 11-6, 4: CP: Code Protection bits(1) (2)
bit 5:
MCLRE: RB3/MCLR Pin Function Select bit
1 = RB3/MCLR pin function is MCLR
0 = RB3/MCLR pin function is digital I/O, MCLR internally tied to VDD
bit 3:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0:
FOSC2:FOSC0: Oscillator Selection bits
111 = External RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin
110 = External RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
101 = Internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin
100 = Internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
011 = Invalid selection
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Note 1: All of the CP pins have to be given the same value to enable the code protection scheme listed.
2: 03FFh is always uncode protected on the PIC16C505. This location contains the MOVLW xx
calibration instruction for the INTRC.
 2001 Microchip Technology Inc.
DS30603B-page 7
PIC16C50X
4.0
CODE PROTECTION
The program code written into the EPROM can be protected by writing to the CP bit of the configuration word.
In PIC16C50X, it is still possible to program and read
locations 0x000 through 0x03F, after code protection.
Once code protection is enabled, all protected segments read '0's (or “garbage values”) and are prevented from further programming. All unprotected
4.1
segments, including ID locations and configuration
word, read normally. These locations can be programmed.
Once code protection is enabled, all code protected
locations (0x040 to 0x3FE) read 0’s. All unprotected
segments, including the internal oscillator calibration
value (0x3FF location), ID and config word read as
normal.
Embedding Configuration Word and ID Information in the HEX File
To allow portability of code, the programmer is required to read the configuration word and ID locations from the HEX
file when loading the HEX file. If configuration word information was not present in the HEX file, then a simple warning
message may be issued. Similarly, while saving a HEX file, configuration word and ID information must be included.
An option to not include this information may be provided.
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
TABLE 4-1:
CODE PROTECTION: PIC16C505
To code protect:
(CP enable pattern: 000000X0XXXX)
Program Memory Segment
R/W in Protected Mode
R/W in Unprotected Mode
Configuration Word (0xFFF)
Read Enabled, Write Enabled
Read Enabled, Write Enabled
[0x00:0x3F]
Read Enabled, Write Enabled
Read Enabled, Write Enabled
[0x40:0x3FE]
Read Disabled (all 0’s), Write Disabled
Read Enabled, Write Enabled
0x3FF
Read Enabled, Write Enabled
Read Enabled, Write Enabled
ID Locations (0x400 : 0x403)
Read Enabled, Write Enabled
Read Enabled, Write Enabled
DS30603B-page 8
 2001 Microchip Technology Inc.
PIC16C50X
4.2
Checksum
4.2.1
CHECKSUM CALCULATIONS
Checksum is calculated by reading the contents of the
PIC16C50X memory locations and adding up the
opcodes up to the maximum user addressable location
(not including the last location which is reserved for the
oscillator calibration value), e.g., 0x3FE for the
PIC16C505. Any carry bits exceeding 16-bits are
neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum
computation for each member of the PIC16C50X family
is shown in Table 4-2.
The following table describes how to calculate the
checksum for each device. Note that the checksum calculation differs, depending on the code protect setting.
Since the program memory locations read out differently, depending on the code protect setting, the table
describes how to manipulate the actual program memory values to simulate the values that would be read
from a protected device. When calculating a checksum
by reading a device, the entire program memory can
simply be read and summed. The configuration word
and ID locations can always be read.
The oscillator calibration value location is not used in
the above checksums.
The checksum is calculated by summing the following:
• The contents of all program memory locations
• The configuration word, appropriately masked
• Masked ID locations (when applicable)
The Least Significant 16-bits of this sum are the
checksum.
TABLE 4-2:
Device
PIC16C505
CHECKSUM COMPUTATION
Code
Protect
OFF
ON
Checksum*
SUM[0x000:0x3FE] + CFGW & 0xFFF
SUM[0x000:0x03F] + CFGW & 0xFFF + SUM(IDS)
Blank
Value
0x723 at
0 and Max
Address
FC00
FBEF
EA48
E15B
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble.
For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
 2001 Microchip Technology Inc.
DS30603B-page 9
PIC16C50X
5.0
PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 5-1:
AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
Standard Operating Conditions
Operating Temperature: +10°C ≤ TA ≤ +40°C, unless otherwise stated, (20°C recommended)
Operating Voltage:
4.5V ≤ VDD ≤ 5.5V, unless otherwise stated.
Parameter
No.
Sym.
Characteristic
Min.
Typ.
Max.
Units
4.75
5.0
5.25
V
20
mA
Conditions
General
PD1
VDDP Supply voltage during programming
PD2
IDDP
PD3
VDDV Supply voltage during verify
VDDMIN
VDDMAX
V
(Note 1)
PD4
VIHH1 Voltage on MCLR/VPP during
programming
12.75
13.25
V
(Note 2)
PD5
VIHH2 Voltage on MCLR/VPP during verify
VDD + 4.0
13.5
Supply current (from VDD)
during programming
50
Programming supply current (from
VPP)
mA
PD6
IPP
PD9
VIH1
(RB1, RB0) input high level
0.8 VDD
V
Schmitt Trigger input
PD8
VIL1
(RB1, RB0) input low level
0.2 VDD
V
Schmitt Trigger input
Serial Program Verify
P1
TR
MCLR/VPP rise time (VSS to VHH)
8.0
µs
P2
Tf
MCLR fall time
8.0
µs
P3
Tset1 Data in setup time before clock ↓
100
ns
P4
Thld1 Data in hold time after clock ↓
100
ns
P5
Tdly1 Data input not driven to next clock input
(delay required between
command/data or command/command)
1.0
µs
P6
Tdly2 Delay between clock ↓ to clock ↑ of
next command or data
1.0
µs
P7
Tdly3 Clock ↑ to date out valid
(during read data)
200
ns
P8
Thld0 Hold time after MCLR ↑
2
µs
Note 1: Program must be verified at the minimum and maximum VDD limits for the part.
2: VIHH must be greater than VDD + 4.5V to stay in Programming/Verify mode.
DS30603B-page 10
 2001 Microchip Technology Inc.
PIC16C50X
FIGURE 5-1:
LOAD DATA COMMAND (PROGRAM/VERIFY)
VIHH
MCLR/VPP
100ns
P8
1
P6
2
3
4
5
100ns
0
0
0
RB1
(Clock)
RB0
(Data)
0
1
2
1µs min. 1
6
4
5
15
0
0
0
P5
P3
P4
P3
1µs min.
P4
}
}
}
}
100ns
min.
100ns
min.
Program/Verify Mode
RESET
FIGURE 5-2:
3
READ DATA COMMAND (PROGRAM/VERIFY)
VIHH
MCLR/VPP
100ns
P8
1
P6
2
3
4
5
100ns
1
0
0
RB1
(Clock)
RB0
(Data)
0
0
2
1µs min. 1
6
3
4
5
15
P7
0
P5
P3
P4
1µs min.
}
}
100ns
min.
RB0
Input
RB0 = Output
Program/Verify Mode
RESET
FIGURE 5-3:
INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
VIHH
MCLR/VPP
P6
1
2
0
1
3
4
5
6
0
0
0
1µs min.
Next Command
1
2
RB1
(Clock)
RB0
(Data)
1
0
0
P5
P3 P4
1µs min.
}
}
100ns
min.
RESET
 2001 Microchip Technology Inc.
Program/Verify Mode
DS30603B-page 11
PIC16C50X
NOTES:
DS30603B-page 12
 2001 Microchip Technology Inc.
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system for the design and manufacture of
development systems is ISO 9001 certified.
DS30557F - page 15
 2001 Microchip Technology Inc.
WORLDWIDE SALES AND SERVICE
AMERICAS
New York
Corporate Office
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Rocky Mountain
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-7456
Atlanta
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
ASIA/PACIFIC
Austin
Australia
Analog Product Sales
8303 MoPac Expressway North
Suite A-201
Austin, TX 78759
Tel: 512-345-2030 Fax: 512-345-6085
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848 Fax: 978-692-3821
Boston
Analog Product Sales
Unit A-8-1 Millbrook Tarry Condominium
97 Lowell Road
Concord, MA 01742
Tel: 978-371-6400 Fax: 978-371-0050
Microchip Technology Australia Pty Ltd
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
China - Beijing
Microchip Technology Beijing Office
Unit 915
New China Hong Kong Manhattan Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
China - Shanghai
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Hong Kong
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423 Fax: 972-818-2924
Microchip Asia Pacific
RM 2101, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
Dayton
Two Prestige Place, Suite 130
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
Mountain View
Analog Product Sales
1300 Terra Bella Avenue
Mountain View, CA 94043-1836
Tel: 650-968-9241 Fax: 650-967-1590
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-334-8870 Fax: 65-334-8850
Taiwan
Microchip Technology Shanghai Office
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Chicago
ASIA/PACIFIC (continued)
India
Microchip Technology Inc.
India Liaison Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Microchip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann Ring 125
D-81739 Munich, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Germany
Analog Product Sales
Lochhamer Strasse 13
D-82152 Martinsried, Germany
Tel: 49-89-895650-0 Fax: 49-89-895650-22
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/30/01
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 2/01
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS30557F-page 16
 2001 Microchip Technology Inc.