LTC2205/LTC2204 16-Bit, 65Msps/40Msps ADCs DESCRIPTIO U FEATURES n n n n n n n n n n n n n Sample Rate: 65Msps/40Msps 79dB SNR and 100dB SFDR (2.25VP-P Range) SFDR >92dB at 140MHz (1.5VP-P Input Range) PGA Front End (2.25VP-P or 1.5VP-P Input Range) 700MHz Full Power Bandwidth S/H Optional Internal Dither Optional Data Output Randomizer Single 3.3V Supply Power Dissipation: 610mW/480mW Optional Clock Duty Cycle Stabilizer Out-of-Range Indicator Pin Compatible Family 105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit) 80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit) 65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit) 40Msps: LTC2204 (16-Bit) 48-Pin (7mm × 7mm) QFN Package U APPLICATIO S n n n n n n The LTC®2205/LTC2204 are sampling 16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals up to input frequencies of 700MHz. The input range of the ADC can be optimized with the PGA front end. The LTC2205/LTC2204 are perfect for demanding communications applications, with AC performance that includes 79dB SNR and 100dB spurious free dynamic range (SFDR). Ultralow jitter of 90fsRMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±4LSB INL, ±1LSB DNL (no missing codes). A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems ATE U TYPICAL APPLICATIO 3.3V LTC2205: 64K Point FFT, fIN = 5.1MHz, –1dBFS, PGA = 0, DITH = 0 SENSE 2.2µF AIN+ 1.25V COMMON MODE BIAS VOLTAGE + ANALOG INPUT AIN– 16-BIT PIPELINED ADC CORE S/H AMP – OVDD INTERNAL ADC REFERENCE GENERATOR OUTPUT DRIVERS CORRECTION LOGIC AND SHIFT REGISTER 0.5V TO 3.6V 0.1µF 0 OF CLKOUT D15 • • • D0 –20 AMPLITUDE (dBFS) VCM OGND CLOCK/DUTY CYCLE CONTROL –60 –80 –100 3.3V VDD GND –40 0.1µF 0.1µF 0.1µF 22076 TA01 –120 –140 0 ENC ENC PGA SHDN DITH MODE OE ADC CONTROL INPUTS RAND 5 20 15 25 10 FREQUENCY (MHz) 30 22054 TA01b 22054fb 1 LTC2205/LTC2204 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION OVDD = VDD (Notes 1 and 2) 48 GND 47 PGA 46 RAND 45 MODE 44 OE 43 OF 42 D15 41 D14 40 D13 39 D12 38 OGND 37 OVDD TOP VIEW SENSE 1 VCM 2 VDD 3 VDD 4 GND 5 AIN+ 6 AIN– 7 GND 8 ENC+ 9 ENC– 10 GND 11 VDD 12 36 OVDD 35 D11 34 D10 33 D9 32 D8 31 OGND 30 CLKOUT+ 29 CLKOUT– 28 D7 27 D6 26 D5 25 OVDD 49 VDD 13 VDD 14 GND 15 SHDN 16 DITH 17 D0 18 D1 19 D2 20 D3 21 D4 22 OGND 23 OVDD 24 Supply Voltage (VDD) ................................... –0.3V to 4V Digital Output Ground Voltage (OGND)........ –0.3V to 1V Analog Input Voltage (Note 3) ......–0.3V to (VDD + 0.3V) Digital Input Voltage .....................–0.3V to (VDD + 0.3V) Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) Power Dissipation.............................................2000mW Operating Temperature Range LTC2205C/LTC2204C ............................... 0°C to 70°C LTC2205I/LTC2204I.............................. –40°C to 85°C Storage Temperature Range .................. –65°C to 150°C Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V UK PACKAGE 48-LEAD (7mm × 7mm) PLASTIC QFN EXPOSED PAD IS GND (PIN 49) MUST BE SOLDERED TO PCB BOARD TJMAX = 150°C, θJA = 29°C/W ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2205CUK#PBF LTC2205CUK#TRPBF LTC2205UK 48-Lead (7mm x 7mm) Plastic DFN 0°C to 70°C LTC2204CUK#PBF LTC2204CUK#TRPBF LTC2204UK 48-Lead (7mm x 7mm) Plastic DFN 0°C to 70°C LTC2205IUK#PBF LTC2205IUK#TRPBF LTC2205UK 48-Lead (7mm x 7mm) Plastic DFN –40°C to 85°C LTC2204IUK#PBF LTC2204IUK#TRPBF LTC2204UK 48-Lead (7mm x 7mm) Plastic DFN –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2205CUK LTC2205CUK#TR LTC2205UK 48-Lead (7mm x 7mm) Plastic DFN 0°C to 70°C LTC2204CUK LTC2204CUK#TR LTC2204UK 48-Lead (7mm x 7mm) Plastic DFN 0°C to 70°C LTC2205IUK LTC2205IUK#TR LTC2205UK 48-Lead (7mm x 7mm) Plastic DFN –40°C to 85°C LTC2204IUK LTC2204IUK#TR LTC2204UK 48-Lead (7mm x 7mm) Plastic DFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER Resolution (No Missing Codes) Integral Linearity Error Integral Linearity Error Differential Linearity Error Offset Error Offset Drift Gain Error Full-Scale Drift Transition Noise CONDITIONS l Differential Analog Input (Note 5) Differential Analog Input (Note 5), TA = 25°C Differential Analog Input (Note 6) l External Reference Internal Reference External Reference l l l MIN 16 TYP MAX ±0.7 ±0.7 ±0.3 ±1 ±10 ±0.2 ±30 ±10 2.5 ±4.5 ±4 ±1 ±8.5 ±1.9 UNITS Bits LSB LSB LSB mV µV/°C %FS ppm/°C ppm/°C LSBRMS 22054fb 2 LTC2205/LTC2204 ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL VIN VIN, CM IIN ISENSE IMODE CIN PARAMETER Analog Input Range (AIN+ – AIN–) Analog Input Common Mode Analog Input Leakage Current SENSE Input Leakage Current MODE Pin Pull-Down Current to GND Analog Input Capacitance tAP Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio Full Power Bandwidth tJITTER CMRR BW-3dB CONDITIONS 3.135V ≤ VDD ≤ 3.465V Differential Input (Note 7) 0V ≤ AIN+, AIN– ≤ VDD 0V ≤ SENSE ≤ VDD MIN l l l l 1 –1 –3 Sample Mode ENC+ < ENC– Hold Mode ENC+ > ENC– 1V < (AIN+ = AIN–) <1.5V TYP 1.5 to 2.25 1.25 MAX 10 6.5 1.8 0.7 UNITS VP-P V µA µA µA pF pF ns 90 fsRMS 60 dB 700 MHz 1.5 1 3 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS SNR 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) Signal-to-Noise Ratio 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 70MHz Input (1.5V Range, PGA = 1) SFDR Spurious Free Dynamic Range 2nd or 3rd Harmonic MIN LTC2204 TYP MAX MIN 79.1 76.5 l 77.6 78 l 74.6 75 79.0 79.0 76.5 78.5 76.3 77.5 77.9 74.6 75 LTC2205 TYP MAX UNITS 79.0 76.4 dBFS dBFS 78.9 78.9 76.4 dBFS dBFS dBFS 78.4 76.2 dBFS dBFS dBFS 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 77.4 75.5 77.3 75.4 dBFS dBFS 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) 76.5 74.9 76.5 74.8 dBFS dBFS 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 100 100 100 100 dB dB 100 100 100 dB dB dB 92 94 94 dB dB dB 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (2.25V Range, PGA = 0 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 70MHz Input (1.5V Range, PGA = 1) l 87 88 l 84.5 86 100 100 100 92 94 94 87 88 84.5 86 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 89 92 89 92 dB dB 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) 82 84 82 84 dB dB 22054fb 3 LTC2205/LTC2204 DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4) SYMBOL PARAMETER CONDITIONS SFDR 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) Spurious Free Dynamic Range 4th Harmonic or Higher 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) S/(N+D) Signal-to-Noise Plus Distortion Ratio SFDR Spurious Free Dynamic Range at –25dBFS Dither “ON” MAX MIN 105 105 l 90 l 88.5 100 100 100 100 90 88.5 LTC2205 TYP MAX UNITS 105 105 dB dB 100 100 dB dB 100 100 dB dB 97 97 97 97 dB dB 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) 95 95 95 95 dB dB 79.1 76.5 79.0 76.4 dBFS dBFS 78.9 78.9 76.4 dBFS dBFS dBFS 78.4 76.2 76.2 dBFS dBFS dBFS 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 70MHz Input (1.5V Range, PGA = 1) Spurious Free Dynamic Range at –25dBFS Dither “OFF” LTC2204 TYP 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) SFDR MIN l 77.5 77.7 l 73.8 74.2 79.0 79.0 76.5 78.5 76.2 76.2 77.4 77.6 73.8 74.2 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 77.3 75.4 77.0 75.3 dBFS dBFS 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) 76.5 75.4 76.0 75.2 dBFS dBFS 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 105 105 105 105 dBFS dBFS 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) 105 105 105 105 dBFS dBFS 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 105 105 105 105 dBFS dBFS 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 100 100 100 100 dBFS dBFS 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) 100 100 100 100 dBFS dBFS 5MHz Input (2.25V Range, PGA = 0) 5MHz Input (1.5V Range, PGA = 1) 115 115 115 115 dBFS dBFS 115 115 dBFS dBFS 15MHz Input (2.25V Range, PGA = 0) 15MHz Input (1.5V Range, PGA = 1) l 98 115 115 98 70MHz Input (2.25V Range, PGA = 0) 70MHz Input (1.5V Range, PGA = 1) 115 115 115 115 dBFS dBFS 140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1) 115 115 115 115 dBFS dBFS 170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1) 105 105 105 105 dBFS dBFS 22054fb 4 LTC2205/LTC2204 COMMON MODE BIAS CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER VCM Output Voltage VCM Output Tempco VCM Line Regulation VCM Output Resistance CONDITIONS IOUT = 0 IOUT = 0 3.135V ≤ VDD ≤ 3.465V 1mA ≤ | IOUT | ≤ 1mA MIN 1.15 TYP 1.25 ±40 1 1 MAX 1.35 UNITS V ppm/°C mV/ V Ω DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER ENCODE INPUTS (ENC+, ENC–) VID Differential Input Voltage (Note 7) VICM Common Mode Input Voltage RIN Input Resistance CIN Input Capacitance LOGIC INPUTS (DITH, PGA, SHDN, RAND) VIH High Level Input Voltage VIL Low Level Input Voltage IIN Digital Input Current CIN Digital Input Capacitance LOGIC OUTPUTS OVDD = 3.3V VOH High Level Output Voltage CONDITIONS MIN l Internally Set Externally Set (Note 7) TYP MAX 0.2 V 1.6 1.2 (See Figure 2) (Note 7) 3.0 6 3 l VDD = 3.3V VDD = 3.3V VIN = 0V to VDD (Note 7) 0.8 ±10 1.5 V V µA pF 3.299 3.29 0.01 0.10 –50 50 0.4 V V V V mA mA l IO = –10µA IO = –200µA l IO = 160µA IO = 1.6mA l 3.1 V V kΩ pF 2 l VDD = 3.3V UNITS VOL Low Level Output Voltage VDD = 3.3V ISOURCE ISINK OVDD = 2.5V VOH VOL OVDD = 1.8V VOH VOL Output Source Current Output Sink Current VOUT = 0V VOUT = 3.3V High Level Output Voltage Low Level Output Voltage VDD = 3.3V VDD = 3.3V IO = –200µA IO = 1.60mA 2.49 0.1 V V High Level Output Voltage Low Level Output Voltage VDD = 3.3V VDD = 3.3V IO = –200µA IO = 1.60mA 1.79 0.1 V V POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. SYMBOL PARAMETER CONDITIONS MIN LTC2204 TYP MAX MIN LTC2205 TYP MAX UNITS 3.135 3.3 3.465 3.315 3.3 3.465 V 3.6 0.5V 3.3 3.6 V VDD Analog Supply Voltage PSHDN Shutdown Power OVDD Output Supply Voltage l IVDD Analog Supply Current l 145 200 185 235 mA PDIS Power Dissipation l 480 660 610 776 mW SHDN = VDD 0.2 0.5V 0.2 mW 22054fb 5 LTC2205/LTC2204 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN LTC2204 TYP MAX MIN 40 1 l 1 Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) l l 10.4 2.7 12.5 12.5 500 500 6.40 2.70 Duty Cycle Stabilizer Off (Note 7) Duty Cycle Stabilizer On (Note 7) l 10.4 2.7 12.5 12.5 500 500 6.40 2.70 LTC2205 TYP MAX UNITS fS Sampling Frequency tL ENC Low Time tH ENC High Time tAP Sample-and-Hold Aperture Delay tD ENC to DATA Delay (Note 7) l 1.3 2.7 4.0 1.3 2.7 4.0 ns tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4.0 1.3 2.7 4.0 ns tSKEW DATA to CLKOUT Skew (tD – tC) (Note 7) l –0.6 0 0.6 –0.6 0 0.6 ns tOE DATA Access Time Bus Relinquish Time CL = 5pf (Note 7) (Note 7) l l 5 5 15 15 5 5 15 15 ns ns 0.7 Pipeline Latency MHz 7.69 7.69 500 500 ns ns 7.69 7.69 500 500 ns ns 0.7 7 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND, with GND and OGND shorted (unless otherwise noted). Note 3: When these pin voltages are taken below GND or above VDD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above VDD without latchup. Note 4: VDD = 3.3V, fSAMPLE = 65MHz (LTC2205), 40MHz (LTC2204) differential ENC+/ENC– = 2VP-P sine wave with 1.6V common mode, 65 7 ns Cycles input range = 2.25VP-P with differential drive (PGA = 0), unless otherwise specified. Note 5: Integral nonlinearity is defined as the deviation of a code from a “best fit straight line” to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the offset voltage measured from –1/2LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2’s complement output mode. Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. TIMING DIAGRAM tAP ANALOG INPUT N+1 N+4 N N+3 N+2 tH tL – ENC ENC+ tD N–7 D0-D15, OF CLKOUT+ CLKOUT – N–6 N–5 N–4 N–3 tC 22054 TD01 22054fb 6 LTC2205/LTC2204 TYPICAL PERFORMANCE CHARACTERISTICS LTC2205: DNL (Differential NonLinearity) vs Code 160,000 1.5 0.75 140,000 1.0 0.50 120,000 0.5 0.25 100,000 0 COUNT 1.00 0 –0.25 60,000 –1.0 –0.50 40,000 –1.5 –0.75 20,000 0 0 –1.00 8192 16384 24576 32768 40960 49152 57344 65536 0 CODE 22054 G01 22054 G02 LTC2205: 64K Point FFT, fIN = 5.1MHz, –1dBFS, PGA = 0, DITH = 0 LTC2205: 64K Point FFT, fIN = 5.1MHz, –25dBFS, PGA = 0, DITH = 0 –20 –20 –20 –40 –40 –40 –80 –100 AMPLITUDE (dBFS) 0 AMPLITUDE (dBFS) 0 –60 –60 –80 –100 –120 –120 5 20 15 25 10 FREQUENCY (MHz) 0 30 –60 –80 –100 –120 –140 –140 5 20 15 25 10 FREQUENCY (MHz) –140 30 0 –20 –20 –20 –40 –40 –40 –120 AMPLITUDE (dBFS) 0 AMPLITUDE (dBFS) 0 –100 –60 –80 –100 –120 –140 5 20 15 25 10 FREQUENCY (MHz) 30 22054 G07 –60 –80 –100 –120 –140 0 30 LTC2205: 64K Point FFT, fIN = 5.1MHz, –40dBFS, PGA = 0, DITH = 1 0 –80 20 15 25 10 FREQUENCY (MHz) 22054 G06 LTC2205: 64K Point FFT, fIN = 5.1MHz, –40dBFS, PGA = 0, DITH = 0 –60 5 22054 G05 22054 G04 LTC2205: 64K Point FFT, fIN = 5.1MHz, –25dBFS, PGA = 0, DITH = 1 8 10 22054 G03 LTC2205: 64K Point FFT, 65Msps, fIN = 5.1MHz, –1dBFS, PGA = 1, DITH = 0 0 0 –10 –8 –6 –4 –2 0 2 4 6 CODE FROM MID-SCALE 8192 16384 24576 32768 40960 49152 57344 65536 CODE AMPLITUDE (dBFS) 80,000 –0.5 –2.0 AMPLITUDE (dBFS) LTC2205: Grounded Input Histogram 2.0 DNL (LSB) INL (LSB) LTC2205: INL (Integral NonLinearity) vs Code 0 5 20 15 25 10 FREQUENCY (MHz) 30 22054 G08 –140 0 5 20 15 25 10 FREQUENCY (MHz) 30 22054 G09 22054fb 7 LTC2205/LTC2204 TYPICAL PERFORMANCE CHARACTERISTICS LTC2205: 64K Point FFT, 65Msps, fIN = 15.1MHz, –1dBFS, PGA = 1, DITH = 0 0 –20 –20 –20 –40 –40 –40 –60 –80 –100 AMPLITUDE (dBFS) 0 –60 –80 –100 –120 –120 0 5 20 15 25 10 FREQUENCY (MHz) 0 30 5 20 15 25 10 FREQUENCY (MHz) –80 –100 –140 30 0 –20 –20 –40 –40 –40 –100 –120 AMPLITUDE (dBFS) –20 AMPLITUDE (dBFS) 0 –60 –80 –100 –120 –140 5 20 15 25 10 FREQUENCY (MHz) 30 –60 –80 –100 –120 –140 0 –140 0 5 20 15 25 10 FREQUENCY (MHz) 22054 G13 30 0 –20 –20 –40 –40 –40 –100 –120 AMPLITUDE (dBFS) –20 AMPLITUDE (dBFS) 0 –60 –80 –100 –120 –140 0 5 20 15 25 10 FREQUENCY (MHz) 30 22054 G16 30 LTC2205: 64K Point FFT, 65Msps, fIN = 70.1MHz, –25dBFS, PGA = 0, DITH = 0 0 –80 20 15 25 10 FREQUENCY (MHz) 22054 G15 LTC2205: 64K Point FFT, 65Msps, fIN = 70.1MHz, –1dBFS, PGA = 1, DITH = 0 0 –60 5 22054 G14 LTC2205: 64K Point FFT, 65Msps, fIN = 70.1MHz, –1dBFS, PGA = 0, DITH = 0 30 LTC2205: 64K Point FFT, 65Msps, fIN = 15.1MHz, –40dBFS, PGA = 0, DITH = 1 0 –80 20 15 25 10 FREQUENCY (MHz) 22054 G12 LTC2205: 64K Point FFT, 65Msps, fIN = 15.1MHz, –40dBFS, PGA = 0, DITH = 0 0 –60 5 22054 G11 22054 G10 LTC2205: 64K Point FFT, 65Msps, fIN = 15.1MHz, –25dBFS, PGA = 0, DITH = 1 AMPLITUDE (dBFS) –60 –120 –140 –140 AMPLITUDE (dBFS) LTC2205: 64K Point FFT, 65Msps, fIN = 15.1MHz, –25dBFS, PGA = 0, DITH = 0 0 AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2205: 64K Point FFT, 65Msps, fIN = 15.1MHz, –1dBFS, PGA = 0, DITH = 0 –60 –80 –100 –120 –140 –140 0 5 20 15 25 10 FREQUENCY (MHz) 30 22054 G17 0 5 20 15 25 10 FREQUENCY (MHz) 30 22054 G18 22054fb 8 LTC2205/LTC2204 TYPICAL PERFORMANCE CHARACTERISTICS LTC2205: 64K Point FFT, 65Msps, fIN = 70.1MHz, –40dBFS, PGA = 0, DITH = 0 0 –20 –20 –20 –40 –40 –40 –60 –80 –100 AMPLITUDE (dBFS) 0 –60 –80 –100 –120 –120 0 5 20 15 25 10 FREQUENCY (MHz) 0 30 5 20 15 25 10 FREQUENCY (MHz) –80 –100 –140 30 0 –20 –20 –40 –40 –40 –120 AMPLITUDE (dBFS) –20 AMPLITUDE (dBFS) 0 –100 –60 –80 –100 0 5 20 15 25 10 FREQUENCY (MHz) –80 –100 –140 –140 30 –60 –120 –120 –140 0 5 20 15 25 10 FREQUENCY (MHz) 22054 G22 0 30 –20 –20 –40 –40 –40 AMPLITUDE (dBFS) –20 AMPLITUDE (dBFS) 0 –100 –60 –80 –100 –120 –120 0 5 20 15 25 10 FREQUENCY (MHz) 30 22054 G25 –60 –80 –100 –120 –140 –140 30 22054 G24 0 –80 20 15 25 10 FREQUENCY (MHz) LTC2205: 64K Point FFT, 65Msps, fIN = 140.1MHz, –40dBFS, PGA = 0, DITH = 1 0 –60 5 22054 G23 LTC2205: 64K Point FFT, 65Msps, fIN = 140.1MHz, –40dBFS, PGA = 0, DITH = 0 LTC2205: 64K Point FFT, 65Msps, fIN = 140.1MHz, –25dBFS, PGA = 0, DITH = 1 30 LTC2205: 64K Point FFT, 65Msps, fIN = 140.1MHz, –25dBFS, PGA = 0, DITH = 0 0 –80 20 15 25 10 FREQUENCY (MHz) 22054 G21 LTC2205: 64K Point FFT, fIN = 140.1MHz, –1dBFS, PGA = 1, DITH = 0 0 –60 5 22054 G20 22054 G19 LTC2205: 64K Point FFT, 65Msps, fIN = 140.1MHz, –1dBFS, PGA = 0, DITH = 0 AMPLITUDE (dBFS) –60 –120 –140 –140 AMPLITUDE (dBFS) LTC2205: 64K Point FFT, 65Msps, fIN = 70.1MHz, –40dBFS, PGA = 0, DITH = 1 0 AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2205: 64K Point FFT, 65Msps, fIN = 70.1MHz, –25dBFS, PGA = 0, DITH = 1 0 5 20 15 25 10 FREQUENCY (MHz) 30 22054 G26 –140 0 5 20 15 25 10 FREQUENCY (MHz) 30 22054 G27 22054fb 9 LTC2205/LTC2204 TYPICAL PERFORMANCE CHARACTERISTICS LTC2205: 64K Point FFT, fIN1 = 64.1MHz, –7dBFS, fIN2 = 20.1MHz, –7dBFS, PGA = 0 0 0 –20 –20 –40 –40 –80 –100 –80 –100 –120 –140 –140 0 5 20 15 25 10 FREQUENCY (MHz) 30 110 –60 –120 22054 G28 100 90 80 70 60 50 40 30 0 5 20 15 25 10 FREQUENCY (MHz) 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 30 22054 G29 LTC2205: SFDR vs Input Level, fIN = 15.1MHz, DITH = 1, RAND = 1, PGA = 0 130 120 120 110 110 110 100 100 100 80 70 60 50 SFDR (dBFS AND dBc) 130 120 SFDR (dBFS AND dBc) 130 90 90 80 70 60 50 90 80 70 60 50 40 40 40 30 30 30 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22054 G32 22054 G31 LTC2205: SFDR vs Input Level, fIN = 140.1MHz, DITH = 0, RAND = 1, PGA = 0 130 120 120 110 110 110 100 100 100 80 70 60 50 SFDR (dBFS AND dBc) 130 120 SFDR (dBFS AND dBc) 130 90 90 80 70 60 50 90 80 70 60 50 40 40 40 30 30 30 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22054 G34 0 22054 G33 LTC2205: SFDR vs Input Level, fIN = 70.1MHz, DITH = 1, RAND = 1, PGA = 0 LTC2205: SFDR vs Input Level, fIN = 70.1MHz, DITH = 0, RAND = 1, PGA = 0 0 22054 G30 LTC2205: SFDR vs Input Level, fIN = 15.1MHz, DITH = 0, RAND = 1, PGA = 0 LTC2205: SFDR vs Input Level, fIN = 5.1MHz, DITH = 1, RAND = 1, PGA = 0 SFDR (dBFS AND dBc) 130 SFDR (dBFS AND dBc) –60 SFDR (dBFS AND dBc) LTC2205: SFDR vs Input Level, fIN = 5.1MHz, DITH = 0, RAND = 1, PGA = 0 120 AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2205: 64K Point FFT, fIN1 = 14.9MHz, –7dBFS, fIN2 = 20.1MHz, –7dBFS, PGA = 0 0 22054 G35 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22054 G36 22054fb 10 LTC2205/LTC2204 TYPICAL PERFORMANCE CHARACTERISTICS LTC2205: SFDR vs Input Level, fIN = 140.1MHz, DITH = 1, RAND = 1, PGA = 0 LTC2205: SFDR vs Input Frequency, DITH = 0, RAND = 0 130 LTC2205: SNR vs Input Frequency, DITH = 0, RAND = 0 110 80 120 79 78 100 100 80 70 60 50 90 SNR (dBFS) 77 90 SFDR (dBc) SFDR (dBFS AND dBc) 110 PGA = 1 76 74 73 PGA = 0 80 PGA = 0 75 PGA = 1 72 40 71 30 20 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 70 0 0 50 150 200 100 INPUT FREQUENCY (MHz) 70 250 22054 G37 22054 G38 22054 G39 LTC2205: SFDR and SNR vs Supply Voltage, fIN = 5.1MHz, 65Msps, PGA = 0 LTC2205: SFDR and SNR vs Sample Rate, fIN = 5.1MHz, –1dBFS, PGA = 0 LTC2205: IVDD vs Sample Rate, fIN = 5.1MHz, –1dBFS 110 110 210 VDD = 3.47V 90 80 SFDR 100 190 IVDD (mA) 100 SFDR (dBc) AND SNR (dBFS) SFDR (dBc) AND SNR (dBFS) 200 SFDR 400 200 100 300 INPUT FREQUENCY (MHz) 0 90 VDD = 3.3V 180 170 VDD = 3.13V 160 80 150 SNR SNR 140 70 70 2.4 0 10 20 30 40 50 60 70 80 90 100 110 SAMPLE RATE (Msps) 2.6 2.8 3.0 3.2 3.4 SUPPLY VOLTAGE 130 3.6 0 10 20 30 40 50 60 70 80 90 100 110 SAMPLE RATE (Msps) 22054 G41 22054 G40 LTC2205: Gain Error Drift with Internal Reference vs Temperature 22054 G42 LTC2205: Gain Drift with External Reference vs Temperature 1 0.8 0 0.6 LTC2205: VCM Drift vs Temperature 0 0.4 –2 –3 –4 0.2 –1 0 VCM (mV) GAIN DRIFT (mV) DRIFT (mV) –1 –0.2 –0.4 –0.6 –5 –3 –0.8 –6 –7 20 40 60 –60 –40 –20 0 TEMPERATURE (°C) –2 –1.0 80 100 22054 G43 –1.2 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) 80 100 22054 G44 –4 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 22054 G45 22054fb 11 LTC2205/LTC2204 TYPICAL PERFORMANCE CHARACTERISTICS LTC2205: SFDR and SNR vs Input Common Mode Voltage, fIN = 5.1MHz LTC2205: SFDR and SNR vs Temperature, fIN = 5.1MHz 120 100 90 SNR 80 70 – 40 0 20 40 60 TEMPERATURE (°C) – 20 90 80 SNR 70 0.50 80 –40 –60 –80 –100 –120 0.75 1.00 1.25 1.50 1.75 INPUT COMMON MODE VOLTAGE (V) –140 2.00 0 LTC2204: 64K Point FFT, 40Msps, fIN = 5.1MHz, –25dBFS, PGA = 0, DITH = 1 0 –20 –20 –20 –40 –40 –40 –100 AMPLITUDE (dBFS) 0 AMPLITUDE (dBFS) 0 –80 –60 –80 –100 –120 –120 0 5 0 20 15 10 FREQUENCY (MHz) –60 –80 –100 –120 –140 –140 5 –140 20 15 10 FREQUENCY (MHz) 0 LTC2204: 64K Point FFT, 40Msps, fIN = 15.1MHz, –1dBFS, PGA = 0, DITH = 0 0 –20 –20 –20 –40 –40 –40 –100 AMPLITUDE (dBFS) 0 AMPLITUDE (dBFS) 0 –80 –60 –80 –100 0 5 15 10 FREQUENCY (MHz) 20 22054 G51 –80 –100 –140 –140 –140 –60 –120 –120 –120 20 15 10 FREQUENCY (MHz) 22054 G50 LTC2204: 64K Point FFT, 40Msps, fIN = 5.1MHz, –40dBFS, PGA = 0, DITH = 1 –60 5 22054 G49 22054 G48 LTC2204: 64K Point FFT, 40Msps, fIN = 5.1MHz, –40dBFS, PGA = 0, DITH = 0 20 15 10 FREQUENCY (MHz) 22054 G47 LTC2204: 64K Point FFT, 40Msps, fIN = 5.1MHz, –25dBFS, PGA = 0, DITH = 0 –60 5 29701 G46b 22054 G46 LTC2204: 64K Point FFT, 40Msps, fIN = 5.1MHz, –1dBFS, PGA = 1, DITH = 0 AMPLITUDE (dBFS) –20 SFDR 100 AMPLITUDE (dBFS) SFDR SNR (dBFS) AND SFDR (dBc) SFDR (dBc) AND (dBFS) 0 110 110 AMPLITUDE (dBFS) LTC2204: 64K Point FFT, 40Msps, fIN = 5.1MHz, –1dBFS, PGA = 0, DITH = 0 0 5 15 10 FREQUENCY (MHz) 20 22054 G52 0 5 15 10 FREQUENCY (MHz) 20 22054 G53 22054fb 12 LTC2205/LTC2204 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 –20 –20 –20 –40 –40 –40 –60 –80 –100 AMPLITUDE (dBFS) 0 –120 –60 –80 –100 5 15 10 FREQUENCY (MHz) 20 0 5 15 10 FREQUENCY (MHz) 22054 G54 –100 0 20 –20 –20 –40 –40 –40 –100 –120 AMPLITUDE (dBFS) –20 AMPLITUDE (dBFS) 0 –60 –80 –100 0 5 15 10 FREQUENCY (MHz) 0 5 15 10 FREQUENCY (MHz) –100 0 20 22054 G59 –20 –20 –40 –40 –40 –120 AMPLITUDE (dBFS) –20 AMPLITUDE (dBFS) 0 –100 –60 –80 –100 5 15 10 FREQUENCY (MHz) 20 22054 G60 –80 –100 –140 –140 0 –60 –120 –120 –140 20 LTC2204: 64K Point FFT, 40Msps, fIN = 70.1MHz, –25dBFS, PGA = 0, DITH = 1 0 –80 15 10 FREQUENCY (MHz) 22054 G58 0 –60 5 LTC2204: 64K Point FFT, 40Msps, fIN = 70.1MHz, –25dBFS, PGA = 0, DITH = 0 22054 G57 LTC2204: 64K Point FFT, 40Msps, fIN = 70.1MHz, –1dBFS, PGA = 1, DITH = 0 –80 –140 –140 20 –60 –120 –120 –140 20 LTC2204: 64K Point FFT, 40Msps, fIN = 70.1MHz, –1dBFS, PGA = 0, DITH = 0 0 –80 15 10 FREQUENCY (MHz) 22054 G56 LTC2204: 64K Point FFT, 40Msps, fIN = 15.1MHz, –40dBFS, PGA = 0, DITH = 1 0 –60 5 22054 G55 LTC2204: 64K Point FFT, 40Msps, fIN = 15.1MHz, –40dBFS, PGA = 0, DITH = 0 AMPLITUDE (dBFS) –80 –140 –140 0 –60 –120 –120 –140 AMPLITUDE (dBFS) LTC2204: 64K Point FFT, 40Msps, fIN = 15.1MHz, –25dBFS, PGA = 0, DITH = 1 LTC2204: 64K Point FFT, 40Msps, fIN = 15.1MHz, –25dBFS, PGA = 0, DITH = 0 AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2204: 64K Point FFT, 40Msps, fIN = 15.1MHz, –1dBFS, PGA = 1, DITH = 0 0 5 15 10 FREQUENCY (MHz) 20 22054 G61 0 5 15 10 FREQUENCY (MHz) 20 22054 G62 22054fb 13 LTC2205/LTC2204 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 –20 –20 –20 –40 –40 –40 –80 –100 AMPLITUDE (dBFS) 0 –60 –60 –80 –100 0 5 15 10 FREQUENCY (MHz) 0 20 5 15 10 FREQUENCY (MHz) –100 0 20 –20 –20 –40 –40 –40 –120 AMPLITUDE (dBFS) –20 AMPLITUDE (dBFS) 0 –100 –60 –80 –100 0 5 15 10 FREQUENCY (MHz) –80 –100 –140 –140 20 –60 –120 –120 –140 0 5 15 10 FREQUENCY (MHz) 22054 G66 0 20 –20 –20 –20 –40 –40 –40 –120 AMPLITUDE (dBFS) 0 AMPLITUDE (dBFS) 0 –100 –60 –80 –100 5 15 10 FREQUENCY (MHz) 20 22054 G69 –80 –100 –140 –140 0 –60 –120 –120 –140 20 22054 G68 0 –80 15 10 FREQUENCY (MHz) LTC2204: 64K Point FFT,fIN1 = 14.9MHz, –7dBFS,fIN2 = 20.1MHz, –7dBFS, PGA = 0, DITH = 0 LTC2204: 64K Point FFT, 40Msps, fIN = 140.1MHz, –40dBFS, PGA = 0, DITH = 1 –60 5 22054 G67 LTC2204: 64K Point FFT, 40Msps, fIN = 140.1MHz, –25dBFS, PGA = 0, DITH = 0 20 LTC2204: 64K Point FFT, 40Msps, fIN = 140.1MHz, –25dBFS, PGA = 0, DITH = 1 0 –80 15 10 FREQUENCY (MHz) 22054 G65 LTC2204: 64K Point FFT, 40Msps, fIN = 140.1MHz, –25dBFS, PGA = 0, DITH = 0 0 –60 5 22054 G64 22054 G63 LTC2204: 64K Point FFT, 40Msps, fIN = 140.1MHz, –1dBFS, PGA = 1, DITH = 0 AMPLITUDE (dBFS) –80 –140 –140 –140 –60 –120 –120 –120 AMPLITUDE (dBFS) LTC2204: 64K Point FFT, 40Msps, fIN = 140.1MHz, –1dBFS, PGA = 0, DITH = 0 LTC2204: 64K Point FFT, 40Msps, fIN = 70.1MHz, –40dBFS, PGA = 0, DITH = 1 AMPLITUDE (dBFS) AMPLITUDE (dBFS) LTC2204: 64K Point FFT, 40Msps, fIN = 70.1MHz, –40dBFS, PGA = 0, DITH = 0 0 5 15 10 FREQUENCY (MHz) 20 22054 G70 0 5 15 10 FREQUENCY (MHz) 20 22054 G71 22054fb 14 LTC2205/LTC2204 TYPICAL PERFORMANCE CHARACTERISTICS LTC2204: 64K Point FFT, fIN1 = 65.1MHz, –7dBFS, fIN2 = 70.1MHz, –7dBFS, PGA = 0, DITH = 0 SFDR (dBFS AND dBc) –60 –80 –100 –120 5 20 15 10 FREQUENCY (MHz) 120 110 110 100 90 80 70 60 80 70 60 50 40 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22054 G73 LTC2204: SFDR vs Input Level, fIN = 70.1MHz, DITH = 0, RAND = 1 130 120 120 110 110 110 90 80 70 60 SFDR (dBFS AND dBc) 130 120 SFDR (dBFS AND dBc) 130 100 100 90 80 70 60 100 90 80 70 60 50 50 50 40 40 40 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22054 G75 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 LTC2204: SFDR vs Input Level, fIN = 140.1MHz, DITH = 0, RAND = 1 LTC2204: SFDR vs Input Level, fIN = 140.1MHz, DITH = 1, RAND = 1 130 130 120 120 120 110 110 110 SFDR (dBFS AND dBc) 130 100 90 80 70 60 100 90 80 70 60 100 90 80 70 60 50 50 50 40 40 40 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22054 G78 0 22054 G77 22054 G76 LTC2204: SFDR vs Input Level, fIN = 70.1MHz, DITH = 1, RAND = 1 0 22054 G74 LTC2204: SFDR vs Input Level, fIN = 15.1MHz, DITH = 1, RAND = 1 LTC2204: SFDR vs Input Level, fIN = 5.1MHz, DITH = 0, RAND = 1 SFDR (dBFS AND dBc) 90 40 22054 G72 SFDR (dBFS AND dBc) 100 50 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) –140 0 130 120 SFDR (dBFS AND dBc) AMPLITUDE (dBFS) –20 130 SFDR (dBFS AND dBc) 0 –40 LTC2204: SFDR vs Input Level, fIN = 5.1MHz, DITH = 1, RAND = 1 LTC2204: SFDR vs Input Level, fIN = 5.1MHz, DITH = 0, RAND = 1 0 22054 G79 30 –80 –70 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dBFS) 0 22054 G80 22054fb 15 LTC2205/LTC2204 TYPICAL PERFORMANCE CHARACTERISTICS LTC2204: SFDR vs Input Frequency, DITH = 0, RAND = 0 LTC2204: SFDR and SNR vs Sample Rate, fIN = 5.1MHz, –1dBFS, PGA = 0, DITH = 0, RAND = 0 LTC2204: SNR vs Input Frequency, DITH = 0, RAND = 0 110 80 110 79 100 SFDR SFDR (dBc) AND SNR (dBFS) 78 SNR (dBFS) SFDR (dBc) 77 90 PGA = 1 80 PGA = 0 76 PGA = 0 75 74 PGA = 1 73 70 72 100 90 80 SNR 71 60 0 50 150 200 100 INPUT FREQUENCY (MHz) 70 70 250 22054 G81 SNR (dBFS) AND SFDR (dBc) VDD = 3.3V IVDD (mA) 160 150 VDD = 3.13V 140 80 2.6 2.8 3.0 3.2 3.4 SUPPLY VOLTAGE (V) SFDR 100 90 80 SNR 130 3.6 22054 G84 90 VDD = 3.47V 100 2.4 80 110 170 SFDR 70 30 40 50 60 70 SAMPLE RATE (Msps) LTC2204: SNR and SFDR vs Input Common Mode Voltage, DITH = 0, RAND = 0 180 110 SNR 20 22054 G83 LTC2204: IVDD vs Sample Rate, fIN = 5.1MHz, dBFS, DITH = 0, RAND = 0 90 10 22054 G82 LTC2204: SFDR and SNR vs Supply Voltage, DITH = 0, RAND = 0 SFDR (dBC) AND SNR (dBFS) 0 400 200 100 300 INPUT FREQUENCY (MHz) 0 120 0 10 20 30 40 50 60 70 SAMPLE RATE (Msps) 80 90 22054 G85 70 0.50 0.75 1.00 1.25 1.50 1.75 INPUT COMMON MODE VOLTAGE (V) 2.00 22054 G86 22054fb 16 LTC2205/LTC2204 PIN FUNCTIONS SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE to VDD to select the internal 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.25V (PGA = 0). VCM (Pin 2): 1.25V Output. Optimum voltage for input common mode. Must be bypassed to ground with a minimum of 2.2µF. Ceramic chip capacitors are recommended. VDD (Pins 3, 4, 12, 13, 14): 3.3V Analog Supply Pin. Bypass to GND with 0.1µF ceramic chip capacitors. GND (Pins 5, 8, 11, 15, 48, 49): ADC Power Ground. AIN+ (Pin 6): Positive Differential Analog Input. AIN – (Pin 7): Negative Differential Analog Input. ENC+ (Pin 9): Positive Differential Encode Input. The sampled analog input is held on the rising edge of ENC+. Internally biased to 1.6V through a 6.2kΩ resistor. Output data can be latched on the rising edge of ENC+. ENC– (Pin 10): Negative Differential Encode Input. The sampled analog input is held on the falling edge of ENC–. Internally biased to 1.6V through a 6.2kΩ resistor. Bypass to ground with a 0.1µF capacitor for a single-ended Encode signal. SHDN (Pin 16): Power Shutdown Pin. SHDN = low results in normal operation. SHDN = high results in powered down analog circuitry and the digital outputs placed in a high impedance state. DITH (Pin 17): Internal Dither Enable Pin. DITH = low disables internal dither. DITH = high enables internal dither. Refer to Internal Dither section of this data sheet for details on dither operation. D0-D15 (Pins 18-22, 26-28, 32-35 and 39-42): Digital Outputs. D15 is the MSB. OGND (Pins 23, 31 and 38): Output Driver Ground. OVDD (Pins 24, 25, 36, 37): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitors. CLKOUT– (Pin 29): Data Valid Output. CLKOUT– will toggle at the sample rate. Latch the data on the falling edge of CLKOUT–. CLKOUT+ (Pin 30): Inverted Data Valid Output. CLKOUT+ will toggle at the sample rate. Latch the data on the rising edge of CLKOUT+. OF (Pin 43): Over/Under Flow Digital Output. OF is high when an over or under flow has occurred. OE (Pin 44): Output Enable Pin. Low enables the digital output drivers. High puts digital outputs in Hi-Z state. MODE (Pin 45): Output Format and Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE to 0V selects offset binary output format and disables the clock duty cycle stabilizer. Connecting MODE to 1/3VDD selects offset binary output format and enables the clock duty cycle stabilizer. Connecting MODE to 2/3VDD selects 2’s complement output format and enables the clock duty cycle stabilizer. Connecting MODE to VDD selects 2’s complement output format and disables the clock duty cycle stabilizer. RAND (Pin 46): Digital Output Randomization Selection Pin. RAND low results in normal operation. RAND high selects D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The output can be decoded by again applying an XOR operation between the LSB and all other bits. This mode of operation reduces the effects of digital output interference. PGA (Pin 47): Programmable Gain Amplifier Control Pin. Low selects a front-end gain of 1, input range of 2.25VP-P. High selects a front-end gain of 1.5, input range of 1.5VP-P. GND (Exposed Pad, Pin 49): ADC Power Ground. The exposed pad on the bottom of the package must be soldered to ground. 22054fb 17 LTC2205/LTC2204 BLOCK DIAGRAM AIN+ AIN– VDD INPUT S/H FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE GND DITHER SIGNAL GENERATOR CORRECTION LOGIC AND SHIFT REGISTER ADC CLOCKS RANGE SELECT OVDD SENSE PGA VCM BUFFER ADC REFERENCE DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER CLKOUT + CLKOUT – OF CONTROL LOGIC OUTPUT DRIVERS • • • VOLTAGE REFERENCE OGND ENC+ ENC– SHDN PGA RAND M0DE OE D15 D14 D1 D0 22054 F01 DITH Figure 1. Functional Block Diagram 22054fb 18 LTC2205/LTC2204 OPERATION DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. Signal-to-Noise Ratio The signal-to-noise (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components, except the first five harmonics. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = –20Log√(V22 + V32 + V42 + ... VN2)/V12 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through nth harmonics. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 3rd order IMD terms include (2fa + fb), (fa + 2fb), (2fa – fb) and (fa – 2fb). The 3rd order IMD is defined as the ratio of the RMS value of either input tone to the RMS value of the largest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signal amplitude to the RMS value of the peak spurious spectral component expressed in dBc. SFDR may also be calculated relative to full scale and expressed in dBFS. Full Power Bandwidth The Full Power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full scale input signal. Aperture Delay Time The time from when a rising ENC+ equals the ENC– voltage to the instant that the input signal is held by the sampleand-hold circuit. Aperture Delay Jitter The variation in the aperture delay time from conversion to conversion. This random variation will result in noise when sampling an AC input. The signal to noise ratio due to the jitter alone will be: SNRJITTER = –20log (2π • fIN • tJITTER) 22054fb 19 LTC2205/LTC2204 APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2205/LTC2204 are CMOS pipelined multistep converters with a front-end PGA. As shown in Figure 1, the converter has five pipelined ADC stages; a sampled analog input will result in a digitized value seven cycles later (see the Timing Diagram section). The analog input is differential for improved common mode noise immunity and to maximize the input range. Additionally, the differential input drive will reduce even order harmonics of the sample and hold circuit. The encode input is also differential for improved common mode noise immunity. The LTC2205/LTC2204 have two phases of operation, determined by the state of the differential ENC+/ENC– input pins. For brevity, the text will refer to ENC+ greater than ENC– as ENC high and ENC+ less than ENC– as ENC low. Each pipelined stage shown in Figure 1 contains an ADC, a reconstruction DAC and a residue amplifier. In operation, the ADC quantizes the input to the stage, and the quantized value is subtracted from the input by the DAC to produce a residue. The residue is amplified and output by the residue amplifier. Successive stages operate out of phase so that when odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. When ENC is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the “input S/H” shown in the block diagram. At the instant that ENC transitions from low to high, the voltage on the sample capacitors is held. While ENC is high, the held input voltage is buffered by the S/H amplifier which drives the first pipelined ADC stage. The first stage acquires the output of the S/H amplifier during the high phase of ENC. When ENC goes back low, the first stage produces its residue which is acquired by the second stage. At the same time, the input S/H goes back to acquiring the analog input. When ENC goes high, the second stage produces its residue which is acquired by the third stage. An identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage for final evaluation. Each ADC stage following the first has additional range to accommodate flash and amplifier offset errors. Results from all of the ADC stages are digitally delayed such that the results can be properly combined in the correction logic before being sent to the output buffer. LTC2005/LTC2004 VDD CSAMPLE 4.9pF AIN+ CPARASITIC 1.8pF VDD CSAMPLE 4.9pF AIN– CPARASITIC 1.8pF VDD 1.6V 6k ENC+ ENC– 6k 1.6V 22054 F02 Figure 2. Equivalent Input Circuit 22054fb 20 LTC2205/LTC2204 APPLICATIONS INFORMATION SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2205/ LTC2204 CMOS differential sample and hold. The differential analog inputs are sampled directly onto sampling capacitors (CSAMPLE) through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all other capacitance associated with each input. During the sample phase when ENC is low, the NMOS transistors connect the analog inputs to the sampling capacitors which charge to, and track the differential input voltage. When ENC transitions from low to high, the sampled input voltage is held on the sampling capacitors. During the hold phase when ENC is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the ADC core for processing. As ENC transitions for high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. Since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. If the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. If the input change is large, such as the change seen with input frequencies near Nyquist, then a larger charging glitch will be seen. Common Mode Bias The ADC sample-and-hold circuit requires differential drive to achieve specified performance. Each input should swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V for the 1.5V range (PGA = 1), around a common mode voltage of 1.25V. The VCM output pin (Pin 2) is designed to provide the common mode bias level. VCM can be tied directly to the center tap of a transformer to set the DC input level or as a reference level to an op amp differential driver circuit. The VCM pin must be bypassed to ground close to the ADC with 2.2µF or greater. Input Drive Impedance As with all high performance, high speed ADCs the dynamic performance of the LTC2205/LTC2204 can be influenced by the input drive circuitry, particularly the second and third harmonics. Source impedance and input reactance can influence SFDR. At the falling edge of ENC the sample-and-hold circuit will connect the 4.9pF sampling capacitor to the input pin and start the sampling period. The sampling period ends when ENC rises, holding the sampled input on the sampling capacitor. Ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however, this is not always possible and the incomplete settling may degrade the SFDR. The sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. For the best performance it is recommended to have a source impedance of 100Ω or less for each input. The source impedance should be matched for the differential inputs. Poor matching will result in higher even order harmonics, especially the second. INPUT DRIVE CIRCUITS Input Filtering A first order RC lowpass filter at the input of the ADC can serve two functions: limit the noise from input circuitry and provide isolation from ADC S/H switching. The LTC2205/LTC2204 have a very broadband S/H circuit, DC to 700MHz; it can be used in a wide range of applications; therefore, it is not possible to provide a single recommended RC filter. Figures 3, 4a and 4b show three examples of input RC filtering at three ranges of input frequencies. In general it is desirable to make the capacitors as large as can be tolerated—this will help suppress random noise as well as noise coupled from the digital circuitry. The LTC2205/ LTC2204 do not require any input filter to achieve data sheet specifications; however, no filtering will put more stringent noise requirements on the input drive circuitry. 22054fb 21 LTC2205/LTC2204 APPLICATIONS INFORMATION Transformer Coupled Circuits Figure 3 shows the LTC2205/LTC2204 being driven by an RF transformer with a center-tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input signal at its optimum DC level. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used; however, as the turns ratio increases so does the impedance seen by the ADC. Source impedance greater than 50Ω can reduce the input bandwidth and increase high frequency distortion. A disadvantage of using a transformer is the loss of low frequency response. Most small RF transformers have poor performance at frequencies below 1MHz. Center-tapped transformers provide a convenient means of DC biasing the secondary; however, they often show poor balance at high input frequencies, resulting in large 2nd order harmonics. Figure 4a shows transformer coupling using a transmission line balun transformer. This type of transformer has much better high frequency response and balance than flux coupled center tap transformers. Coupling capacitors are added at the ground and input primary terminals to allow the secondary terminals to be biased at 1.25V. Figure 4b shows the same circuit with components suitable for higher input frequencies. VCM VCM 2.2µF 2.2µF 5Ω 5Ω AIN+ 10Ω 0.1µF T1 35Ω 8.2pF 0.1µF 10Ω T1 = MA/COM ETC1-1T RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2µF 35Ω 10Ω 5Ω 25Ω 0.1µF 4.7pF 25Ω 10Ω ANALOG INPUT LTC2205/ LTC2204 8.2pF 0.1µF 5Ω AIN– 8.2pF T1 1:1 4.7pF T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2µF 22054 F03 Figure 3. Single-Ended to Differential Conversion Using a Transformer. Recommended for Input Frequencies from 5MHz to 150MHz 5Ω 4.7pF AIN+ LTC2205/ LTC2204 AIN– 22054 F04a Figure 4a. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 70MHz to 250MHz VCM 2.2µF 0.1µF 5Ω ANALOG INPUT 25Ω 0.1µF T1 1:1 0.1µF 25Ω T1 = MA/COM ETC1-1-13 RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE EXCEPT 2.2µF AIN+ 2.2pF 5Ω 2.2pF LTC2205/ LTC2204 AIN– 22054 F04b Figure 4b. Using a Transmission Line Balun Transformer. Recommended for Input Frequencies from 250MHz to 500MHz 22054fb 22 LTC2205/LTC2204 APPLICATIONS INFORMATION Direct Coupled Circuits Figure 5 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. The advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of any op amp or closed-loop amplifier will degrade the ADC SFDR at high input frequencies. Additionally, wideband op amps or differential amplifiers tend to have high noise. As a result, the SNR will be degraded unless the noise bandwidth is limited prior to the ADC input. very stringent settling requirements and is not accessible for external use. The SENSE pin can be driven ±5% around the nominal 2.5V or 1.25V external reference inputs. This adjustment range can be used to trim the ADC gain error or other system gain errors. When selecting the internal reference, the SENSE pin should be tied to VDD as close to the converter as possible. If the sense pin is driven externally it should be bypassed to ground as close to the device as possible with 1µF (or larger) ceramic capacitor. VCM HIGH SPEED DIFFERENTIAL AMPLIFIER ANALOG INPUT + LTC2205/ LTC2204 2.2µF AIN+ 25Ω 12pF + LTC2205/ LTC2204 CM – – AIN– 25Ω AMPLIFIER = LTC6600-20, LTC1993, ETC. 12pF 22054 F05 TIE TO VDD TO USE INTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 1.25V REFERENCE Figure 5. DC Coupled Input with Differential Amplifier RANGE SELECT AND GAIN CONTROL INTERNAL ADC REFERENCE SENSE PGA 2.5V BANDGAP REFERENCE VCM BUFFER 1.25V 2.2µF Reference Operation Figure 6 shows the LTC2205/LTC2204 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifier and control circuit. The LTC2205/LTC2204 have three modes of reference operation: Internal Reference, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to VDD. To use an external reference, simply apply either a 1.25V or 2.5V reference voltage to the SENSE input pin. Both 1.25V and 2.5V applied to SENSE will result in a full scale range of 2.25VP-P (PGA = 0). A 1.25V output, VCM is provided for a common mode bias for input drive circuitry. An external bypass capacitor is required for the VCM output. This provides a high frequency low impedance path to ground for internal and external circuitry. This is also the compensation capacitor for the reference; it will not be stable without this capacitor. The minimum value required for stability is 2.2µF. 22054 F06 Figure 6. Reference Circuit VCM 1.25V 2.2µF 3.3V 1µF 2 LT1461-2.5 4 6 SENSE LTC2205/ LTC2204 2.2µF 22054 F07 Figure 7. A 2.25V Range ADC with an External 2.5V Reference The internal programmable gain amplifier provides the internal reference voltage for the ADC. This amplifier has 22054fb 23 LTC2205/LTC2204 APPLICATIONS INFORMATION PGA Pin The PGA pin selects between two gain settings for the ADC front-end. PGA = 0 selects an input range of 2.25VP-P; PGA = 1 selects an input range of 1.5VP-P. The 2.25V input range has the best SNR; however, the distortion will be higher for input frequencies above 100MHz. For applications with high input frequencies, the low input range will have improved distortion; however, the SNR will be worse by up to approximately 2dB to 6dB. See the typical performance curves section. Driving the Encode Inputs The noise performance of the LTC2205/LTC2204 can depend on the encode signal quality as much as on the analog input. The encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. Any noise present on the encode signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical (high input frequencies), take the following into consideration: 1. Differential drive should be used. 2. Use as large an amplitude possible. If using transformer coupling, use a higher turns ratio to increase the amplitude. 3. If the ADC is clocked with a fixed frequency sinusoidal signal, filter the encode signal to reduce wideband noise. 4. Balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to 3V. Each input may be driven from ground to VDD for single-ended drive. LTC2205/ LTC2204 VDD TO INTERNAL ADC CLOCK DRIVERS VDD 1.6V ENC+ 6k 0.1µF ENCODE INPUT ETC1-1T 50Ω 100Ω • • VDD 1.6V 50Ω 0.1µF 33pF 6k ENC– 22054 F08 Figure 8. Transformer Driven Encode 22054fb 24 LTC2205/LTC2204 APPLICATIONS INFORMATION 3.3V MC100LVELT22 ENC+ VTHRESHOLD = 1.6V 3.3V 130Ω Q0 ENC+ D0 1.6V ENC– LTC2205/ LTC2204 0.1µF 130Ω ENC– Q0 83Ω LTC2205/ LTC2204 83Ω 22054 F09 22054 F10 Figure 9. Single-Ended ENC Drive, Not Recommended for Low Jitter Maximum and Minimum Encode Rates The maximum encode rate for the LTC2205 is 65Msps. The maximum encode rate for the LTC2204 is 40Msps. For the ADC to operate properly the encode signal should have a 50% (±2.5%) duty cycle. Achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as PECL or LVDS. When using a single-ended ENCODE signal asymmetric rise and fall times can result in duty cycles that are far from 50%. An optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. This circuit uses the rising edge of ENC pin to sample the analog input. The falling edge of ENC is ignored and an internal falling Figure 10. ENC Drive Using a CMOS to PECL Translator edge is generated by a phase-locked loop. The input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin must be connected to 1/3VDD or 2/3VDD using external resistors. The lower limit of the LTC2205/LTC2204 sample rate is determined by droop of the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2205/LTC2204 is 1Msps. 22054fb 25 LTC2205/LTC2204 APPLICATIONS INFORMATION DIGITAL OUTPUTS Data Format Digital Output Buffers The LTC2205/LTC2204 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. This pin has a four level logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can be user to set the 1/3VDD and 2/3VDD logic levels. Table 1 shows the logic states for the MODE pin. Figure 11 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output eliminates the need for external damping resistors. As with all high speed/high resolution converters, the digital output loading can affect the performance. The digital outputs of the LTC2205/LTC2204 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as a ALVCH16373 CMOS latch. For full speed operation the capacitive load should be kept under 10pF. A resistor in series with the output may be used but is not required since the ADC has a series resistor of 33Ω on chip. Table 1. MODE Pin Function MODE 0(GND) 1/3VDD 2/3VDD VDD Output Format Clock Duty Cycle Stabilizer Offset Binary Offset Binary 2’s Complement 2’s Complement Off On On Off Overflow Bit An overflow output bit (OF) indicates when the converter is over-ranged or under-ranged. A logic high on the OF pin indicates an overflow or underflow. Lower OVDD voltages will also help reduce interference from the digital outputs. LTC2205/LTC2204 OVDD VDD 0.5V TO 3.6V VDD 0.1mF OVDD DATA FROM LATCH PREDRIVER LOGIC 33W TYPICAL DATA OUTPUT OGND 22054 F11 Figure 11. Equivalent Circuit for a Digital Output Buffer 22054fb 26 LTC2205/LTC2204 APPLICATIONS INFORMATION Output Clock The ADC has a delayed version of the encode input available as a digital output. Both a noninverted version, CLKOUT+ and an inverted version CLKOUT – are provided. The CLKOUT+/CLKOUT – can be used to synchronize the converter data to the digital system. This is necessary when using a sinusoidal encode. Data can be latched on the rising edge of CLKOUT+ or the falling edge of CLKOUT –. CLKOUT+ falls and CLKOUT – rises as the data outputs are updated. Digital Output Randomizer Interference from the ADC digital outputs is sometimes unavoidable. Interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. Even a tiny coupling factor can result in discernible unwanted tones in the ADC output spectrum. By randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise floor for a large reduction in unwanted tone amplitude. The digital output is “Randomized” by applying an exclusive-OR logic operation between the LSB and all other data output bits. To decode, the reverse operation is applied; that is, an exclusive-OR operation is applied between the LSB and all other bits. The LSB, OF and CLKOUT output are not affected. The output Randomizer function is active when the RAND pin is high. LTC2205/LTC2204 CLKOUT CLKOUT OF OF D15 D15/D0 D14 D2 D14/D0 • • • D2/D0 D1 RAND = HIGH, SCRAMBLE ENABLED D1/D0 RAND D0 D0 22054 F12 Figure 12. Functional Equivalent of Digital Output Randomizer 22054fb 27 LTC2205/LTC2204 APPLICATIONS INFORMATION Output Driver Power Separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. The power supply for the digital output buffers, OVDD, should be tied to the same power supply as for the logic being driven. OVDD can be powered with any logic voltage up to the VDD of the ADC. OGND can be powered with any voltage from ground up to 1V and must be less than OVDD. The logic outputs will swing between OGND and OVDD. Internal Dither The LTC2205/LTC2204 are 16-bit ADCs with very linear transfer functions; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches. An optional internal dither mode can be enabled to randomize the input location on the ADC transfer curve, resulting in improved SFDR for low signal levels. As shown in Figure 14, the output of the sample-and-hold amplifier is summed with the output of a dither DAC. The dither DAC is driven by a long sequence pseudo-random number generator; the random number fed to the dither DAC is also subtracted from the ADC result. If the dither DAC is precisely calibrated to the ADC, very little of the dither signal will be seen at the output. The dither signal that does leak through will appear as white noise. The dither DAC is calibrated to result in less than 0.5dB elevation in the noise floor of the ADC, as compared to the noise floor with dither off. PC BOARD FPGA CLKOUT OF D15/D0 D15 LTC2205/ LTC2204 D14/D0 D14 D2/D0 • • • D2 D1/D0 D1 D0 D0 22054 F13 Figure 13. Descrambling a Scrambled Digital Output 22054fb 28 LTC2205/LTC2204 APPLICATIONS INFORMATION Grounding and Bypassing The LTC2205/LTC2204 require a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2205/LTC2204 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. High quality ceramic bypass capacitors should be used at the VDD, VCM, and OVDD pins. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC2205/LTC2204 differential inputs should run parallel and close to each other. The input traces should be as short as possible to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTC2205/LTC2204 is transferred from the die through the bottom-side exposed pad. For good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the PC board. It is critical that the exposed pad and all ground pins are connected to a ground plane of sufficient area with as many vias as possible. LTC2205/LTC2204 AIN+ ANALOG INPUT AIN– 16-BIT PIPELINED ADC CORE S/H AMP CLOCK/DUTY CYCLE CONTROL PRECISION DAC DIGITAL SUMMATION CLKOUT OF D15 • • • D0 OUTPUT DRIVERS MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR 22054 F14 ENC + ENC – DITH DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF Figure 14. Functional Equivalent Block Diagram of Internal Dither Circuit 22054fb 29 LTC2205/LTC2204 APPLICATIONS INFORMATION RANDOMIZER (REQUIRES CHANGE IN SELECTED DEVICE IN PSCOPE) 0V 3.3V NOT PROVIDED BY DC718 JUMPERS ARE SHOWN IN DEFAULT POSITIONS CLOCK POLARITY PGA SENSE CLOCK OUT MSB DIGITAL OUTPUTS TO DC718 (2.5V CMOS) ANALOG INPUT (50Ω) LSB ENABLE 22076 DC918C DITHER ENC CLOCK INPUT (50Ω) SHUTDOWN Ordering Guide: DEMO BOARD NUMBER PART NUMBER RESOLUTION SPEED INPUT FREQUENCY USB I/F BOARD DC918C-A LTC2207CUK 16-Bit 105Msps 1MHz to 70MHz DC718 DC918C-B LTC2207CUK 16-Bit 105Msps 70MHz to 140MHz DC718 DC918C-C LTC2206CUK 16-Bit 80Msps 1MHz to 70MHz DC718 DC918C-D LTC2206CUK 16-Bit 80Msps 70MHz to 140MHz DC718 DC918C-E LTC2205CUK 16-Bit 65Msps 1MHz to 70MHz DC718 DC918C-F LTC2205CUK 16-Bit 65Msps 70MHz to 140MHz DC718 DC918C-G LTC2204CUK 16-Bit 40Msps 1MHz to 70MHz DC718 DC918C-H LTC2207CUK-14 14-Bit 105Msps 1MHz to 70MHz DC718 DC918C-I LTC2207CUK-14 14-Bit 105Msps 70MHz to 140MHz DC718 DC918C-J LTC2206CUK-14 14-Bit 80Msps 1MHz to 70MHz DC718 DC918C-K LTC2206CUK-14 14-Bit 80Msps 70MHz to 140MHz DC718 DC918C-L LTC2205CUK-14 14-Bit 65Msps 1MHz to 70MHz DC718 See Web site for ordering details or contact local sales. 22054fb 30 LTC2205/LTC2204 APPLICATIONS INFORMATION Silkscreen Top Top Side 22054fb 31 LTC2205/LTC2204 APPLICATIONS INFORMATION Inner Layer 2 Inner Layer 4 Inner Layer 3 Inner Layer 5 22054fb 32 LTC2205/LTC2204 APPLICATIONS INFORMATION Bottom Side Silkscreen Bottom 22054fb 33 C30 0.01µF C10 0.01µF R31 * ASSEMBLY TYPE DC918C-A DC918C-B DC918C-C DC918C-D DC918C-E DC918C-F DC918C-G DC918C-H DC918C-I DC918C-J DC918C-K DC918C-L 5 4 T2 1 2 U1 LTC2207CUK LTC2207CUK LTC2206CUK LTC2206CUK LTC2205CUK LTC2205CUK LTC2204CUK LTC2207CUK-14 LTC2207CUK-14 LTC2206CUK-14 LTC2206CUK-14 LTC2205CUK-14 T3 MABAES0060 WBC1-1L MABAES0060 WBC1-1L MABAES0060 WBC1-1L MABAES0060 MABAES0060 WBC1-1L MABAES0060 WBC1-1L MABAES0060 C12 0.01µF C5 4.7pF 1.8pF 4.7pF 1.8pF 4.7pF 1.8pF 4.7pF 4.7pF 1.8pF 4.7pF 1.8pF 4.7pF C15 0.1µF R28 49.9Ω C5 * R26 5.1Ω C7, C28 8.2pF 3.9pF 8.2pF 3.9pF 8.2pF 3.9pF 8.2pF 8.2pF 3.9pF 8.2pF 3.9pF 8.2pF C16 0.1µF R29 5.1Ω R30 86.6 182 86.6 182 86.6 182 86.6 86.6 182 86.6 182 86.6 1 R1 10k AIN– GND AIN+ SENSE VCM VDD VDD 3 1 JP5 3 SHDN GND VDD R21, 10k R20 10k R6 OPEN R2 10k R3 1k R7 1k R4 OPEN OVP GND JP1 U1* 2 2 1 3 GND VDD JP6 DITH INPUT FREQUENCY BITS Msps 1MHz < AIN < 70MHz 16 105 105 70MHz < AIN < 140MHz 16 1MHz < AIN < 70MHz 16 80 80 70MHz < AIN < 140MHz 16 16 65 1MHz < AIN < 70MHz 70MHz < AIN < 140MHz 16 65 16 40 1MHz < AIN < 70MHz 1MHz < AIN < 70MHz 14 105 70MHz < AIN < 140MHz 14 105 14 80 1MHz < AIN < 70MHz 80 70MHz < AIN < 140MHz 14 14 65 1MHz < AIN < 70MHz VDD GND 9 ENC+ 10 ENC– 11 GND 12 VDD 1 2 3 4 5 6 7 8 C2 2.2µF L1 56nH 18nH 56nH 18nH 56nH 18nH 56nH 56nH 18nH 56nH 18nH 56nH 3 JP3 1 JP4 1 PGA RAND 2 2 VDD VDD GND GND OPEN VDD R31, R32 86.6 43.2 86.6 43.2 86.6 43.2 86.6 86.6 43.2 86.6 43.2 86.6 C17 0.1µF R33 100Ω R10 10Ω R14 10Ω C11 8.2pF C3 0.01µF C8 2.2µF R8 100Ω R13 10Ω R12 33.2Ω R11 3 33.2Ω R9 10Ω R27 49.9Ω 1 1 5 C9 0.01µF 2 2 C6 0.01µF 3 R32 * 5 T1 MABA007159000000 4 3 4*T3 MABA-007159000000 C7 * * L1 * VERSION TABLE J3 ENCODE INPUT C28 * C4 0.01µF J2 ANALOG INPUT * R30 2 JP2 SHDN GND 48 PGA 47 RAND 46 MODE 45 OE 44 13 VDD 14 VDD 15 GND 16 SHDN 17 DITH 18 D0 19 D1 20 D2 21 D3 22 D4 23 3 1 3 2 DD 36 35 34 33 32 31 30 CLKOUT– + 29 28 D7 27 D6 26 D5 25 OVDD OVDD D11 D10 D9 D8 OGND CLKOUT+ OF 43 D15 42 D14 41 D13 40 D12 39 OGND 38 37 OV OGND OVDD 34 24 VDD C27 100µF 6.3V OPT. C1 0.1µF 3 5 E4 E3 A7 A6 A5 A4 A3 A2 A1 A0 T/R GND VCC 20 OVP A7 A6 A5 A4 A3 A2 A1 A0 T/R GND VCC 20 OVP 4 5 C22 1µF 9 8 7 6 5 4 3 2 1 10 9 8 7 6 5 4 3 2 1 10 C14 0.1µF LT1763 OVP 1 A0 2 A1 3 A2 4 A3 8 7 6 5 33 33 RN4C RN4D R23 100k R22 105k VCC WP SCL SDA C20 10µF 6.3V R17 10k 33 33 33 33 RN3C RN3D RN4A RN4B 33 33 33 33 RN1C RN1D RN2A RN2B 33 33 33 33 33 33 RN1A RN1B RN2C RN2D RN3A RN3B 33 R5 U6 24LC025 C21, 0.01µF 1 IN OUT 2 7 GND ADJ 3 6 GND GND 4 5 SHDN BYP 8 U7 1 2 74VCX245BQX B7 B6 B5 B4 B3 B2 B1 B0 OE U2 74VCX245BQX B7 B6 B5 B4 B3 B2 B1 B0 OE U2 C19 3 U5 0.1µF NC7SV86P5X 11 12 13 14 15 16 17 18 19 11 12 13 14 15 16 17 18 19 VDD VDD R25 3.3V 1Ω 4 U4 NC7SV86P5X E1 C23 4.7µF GND C18 0.1µF VDD 2 1 OVP 2 4 6 8 20 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 2 4 6 8 20 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C25 0.1µF OVP R19 10k C13 0.1µF 22054 F15 C26 0.1µF 3201S-40G1 OGND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 J1 R18 10k 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 LTC2205/LTC2204 APPLICATIONS INFORMATION 22054fb LTC2205/LTC2204 PACKAGE DESCRIPTION UK Package 48-Lead Plastic QFN (7mm × 7mm) (Reference LTC DWG # 05-08-1704) 0.70 ±0.05 5.15 ± 0.05 5.50 REF 6.10 ±0.05 7.50 ±0.05 (4 SIDES) 5.15 ± 0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 ± 0.10 (4 SIDES) 0.75 ± 0.05 R = 0.10 TYP R = 0.115 TYP 47 48 0.40 ± 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 PIN 1 CHAMFER C = 0.35 5.15 ± 0.10 5.50 REF (4-SIDES) 5.15 ± 0.10 (UK48) QFN 0406 REV C 0.200 REF 0.00 – 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 22054fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC2205/LTC2204 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1748 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package 14-Bit, 80Msps 5V ADC LTC1750 14-Bit, 80Msps, 5V Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain LT1994 Low Noise, Low Distortion Fully Differential Input/ Output Amplifier/Driver Low Distortion: –94dBc at 1MHz LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 140mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN LTC2203 16-Bit, 25Msps, 3.3V ADC, Lowest Noise 220mW, 81.6dB SNR, 100dB SFDR, 48-Pin QFN LTC2204 16-Bit, 40Msps, 3.3V ADC 480mW, 79.1dB SNR, 100dB SFDR, 48-Pin QFN LTC2205 16-Bit, 65Msps, 3.3V ADC 610mW, 79dB SNR, 100dB SFDR, 48-Pin QFN LTC2206 16-Bit, 80Msps, 3.3V ADC 725mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN LTC2207 16-Bit, 105Msps, 3.3V ADC 900mW, 77.9dB SNR, 100dB SFDR, 48-Pin QFN LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin QFN LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin QFN LTC2224 12-Bit, 135Msps, 3.3V ADC, High IF Sampling 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin QFN LTC2255 14-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin QFN LTC2284 14-Bit, Dual, 105Msps, 3V ADC, Low Crosstalk 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin QFN LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer LT5514 Ultralow Distortion IF Amplifier/ADC Driver with Digitally Controlled Gain 450MHz to 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step LT5515 1.5GHz to 2.5GHz Direct Conversion Quadrature Demodulator High IIP3: 20dBm at 1.9GHz, Integrated LO Quadrature Generator LT5516 800MHz to 1.5GHz Direct Conversion Quadrature Demodulator High IIP3: 21.5dBm at 900MHz, Integrated LO Quadrature Generator LT5517 40MHz to 900MHz Direct Conversion Quadrature Demodulator High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator LT5522 600MHz to 2.7GHz High Linearity Downconverting Mixer 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz. NF = 12.5dB, 50W Single-Ended RF and LO Ports 22054fb 36 Linear Technology Corporation LT 0907 REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006