LTC4101
Smart Battery
Charger Controller
U
FEATURES
DESCRIPTIO
■
The LTC®4101 Smart Battery Charger is a single chip
charging solution that dramatically simplifies construction of an SBS compliant system. The LTC4101 implements a Level 2 charger function whereby the charger can
be programmed by the battery or by the host. A SafetySignal
on the battery being charged is monitored for temperature, connectivity and battery type information. The SMBus
interface remains alive when the AC power adapter is
removed and responds to all SMBus activity directed to
it, including SafetySignal status (via the ChargerStatus
command). The charger also provides an interrupt to the
host whenever a status change is detected (e.g., battery
removal, AC adapter connection).
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Single Chip Smart Battery Charger Controller
100% Compliant (Rev. 1.1) SMBus Support Allows
for Operation with or without Host
Up to 4A Charging Current Capability
High Efficiency Synchronous Buck Charger
VBAT Optimized 3V to 5.5V
SMBus Accelerator Improves SMBus Timing
Hardware Interrupt and SMBAlert Response
Eliminate Interrupt Polling
0.5V Dropout Voltage; Maximum Duty Cycle > 98%
AC Adapter Current Limit Maximizes Charge Rate
±0.8% Voltage Accuracy; ±4% Current Accuracy
10-Bit DAC for Charge Current Programming
11-Bit DAC for Charger Voltage Programming
User-Selectable Overvoltage and Overcurrent Limits
High Noise Immunity SafetySignal Sensor
Available in a 24-Pin SSOP Package
U
APPLICATIO S
■
■
Portable Instruments and Computers
Data Storage Systems and Battery Backup Servers
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All
other trademarks are the property of their respective owners. Protected by U.S. Patents
including 6650174, 5723970.
Charging current and voltage are restricted to chemistryspecific limits for improved system safety and reliability.
Limits are programmable by two external resistors. Additionally, the maximum average current from the AC adapter
is programmable to avoid overloading the adapter when
simultaneously supplying load current and charging
current. When supplying system load current, charging
current is automatically reduced to prevent adapter
overload.
U
TYPICAL APPLICATIO
DCIN
9V to 12V, 2A
0.1µF
6.04k
3V
TO 5.5V
1.21k
17
11
6
CHGEN
10
ACP
7
9
8
15
16
13
1.13k
14
10k
20
LTC4101
VDD
DCIN
DCDIV
INFET
CHGEN
CLP
ACP
CLN
SMBALERT
TGATE
SCL
BGATE
SDA
PGND
THB
CSP
THA
BAT
ILIM
VSET
VLIM
ITH
IDC
GND
0.1µF
5
4
PART
LTC4101
LTC4100
5k
24
SYSTEM LOAD
23
5µF
1
3
SMART BATTERY
0.1Ω 1%
24µH
2
5µF
21
22
18
19
12
0.03µF
100Ω
6.04k
0.0015µF
54.9k
0.068µF
SMBALERT#
0.05Ω
VBAT
< 5.5V
> 5.5V
0.12µF
0.1µF
SafetySignal
SMBCLK
SMBCLK
SMBDAT
SMBDAT
4101 F01a
Figure 1. 1A Smart Battery Charger
4101f
1
LTC4101
U
W W
W
ABSOLUTE
AXI U RATI GS
U
W
U
PACKAGE/ORDER I FOR ATIO
(Note 1)
TOP VIEW
Voltage from VDD to GND ................................ 7V/–0.3V
Voltage from CHGEN, DCDIV, SDA, SCL
and SMBALERT to GND .............................. 7V/–0.3V
Voltage from DCIN, CLP, CLN to GND ........... 32V/–0.3V
Voltage from CLP to CLN ...................................... ±0.3V
PGND wrt. GND .................................................... ±0.3V
CSP, BAT to GND .............................................. 28V/–5V
Operating Ambient Temperature Range (Note 4)
........................................................... – 40°C to 85°C
Junction Temperature Range ............... – 40°C to 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
TGATE
1
24 CLP
PGND
2
23 CLN
BGATE
3
22 BAT
INFET
4
21 CSP
DCIN
5
20 IDC
CHGEN
6
19 ITH
SMBALERT
7
18 VSET
SDA
8
17 VDD
SCL
9
16 THA
ACP 10
15 THB
DCDIV 11
14 VLIM
GND 12
13 ILIM
G PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 90°C/W
ORDER PART NUMBER
LTC4101EG
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 4V unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
●
DCIN Operating Range
IDCIN
DCIN Operating Current
Charging, Sum of Currents on
DCIN, CLP and CLN
VTOL
Charge Voltage Accuracy
(Note 2)
ITOL
VDD
MIN
TYP
6
3
MAX
UNITS
28
V
5
mA
●
–1.1
–1.3
1.1
1.3
%
%
VCSP – VBAT Target = 102.3mV
IDAC = 0xFFFF
●
–2
–3
6
7
%
%
VDD Operating Voltage
0V ≤ VDCIN ≤ 28V
●
3
5.5
V
Battery Leakage Current
DCIN = 0V, VCLP = VCLN = VCSP = VBAT
●
15
35
µA
4.7
5.5
V
3
V
3
mA
Charge Current Accuracy (Note 3)
Shutdown
UVLO
Undervoltage Lockout Threshold
DCIN Rising, VBAT = 0V
●
VDD Power-Fail
Part Held in Reset Until this VDD Present
●
DCIN Current in Shutdown
VCHGEN = 0V
4.2
2
Current Sense Amplifier, CA1
Input Bias Current into BAT Pin
CMSL
CA1/I1 Input Common Mode Low
CMSH
CA1/I1 Input Common Mode High
µA
11.66
●
VDCIN ≤ 28V
●
0
V
VCLN-0.2
V
4101f
2
LTC4101
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 4V unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current Comparators IREV
ITREV
Reverse Current Threshold (VCSP-VBAT)
– 30
mV
Current Sense Amplifier, CA2
Transconductance
1
mmho
Source Current
Measured at ITH, VITH = 1.4V
–40
µA
Sink Current
Measured at ITH, VITH = 1.4V
40
µA
1.5
mmho
Current Limit Amplifier
Transconductance
VCLP
Current Limit Threshold
ICLN
CLN Input Bias Current
●
93
100
107
mV
50
nA
1
mmho
36
µA
Voltage Error Amplifier, EA
Transconductance
Sink Current
OVSD
Measured at ITH, VITH = 1.4V
Overvoltage Shutdown Threshold as a Percent
of Programmed Charger Voltage
●
102
107
110
%
●
0
0.17
0.25
V
25
50
Input P-Channel FET Driver (INFET)
DCIN Detection Threshold (VDCIN-VCLP)
DCIN Voltage Ramping Up
from VCLP-0.05V
Forward Regulation Voltage (VDCIN-VCLP)
●
Reverse Voltage Turn-Off Voltage (VDCIN-VCLP)
●
–60
–25
●
5
5.8
INFET “ON” Clamping Voltage (VDCIN-VINFET)
IINFET = 1µA
INFET “OFF” Clamping Voltage (VDCIN-VINFET)
IINFET = –25µA
mV
mV
6.5
V
0.25
V
Oscillator
fOSC
Regulator Switching Frequency
255
300
fMIN
Regulator Switching Frequency in Drop Out
Duty Cycle ≥ 98%
20
25
345
kHz
kHz
DCMAX
Regulator Maximum Duty Cycle
VCSP = VBAT
98
99
%
Gate Drivers (TGATE, BGATE)
VTGATE High (VCLP-VTGATE)
ITGATE = –1mA
50
mV
VBGATE High
CLOAD = 3000pF
4.5
5.6
10
V
VTGATE Low (VCLP-VTGATE)
CLOAD = 3000pF
4.5
VBGATE Low
IBGATE = 1mA
5.6
10
V
50
mV
TGTR
TGTF
TGATE Transition Time
TGATE Rise Time
TGATE Fall Time
CLOAD = 3000pF, 10% to 90%
CLOAD = 3000pF, 10% to 90%
50
50
110
100
ns
ns
BGTR
BGTF
BGATE Transition Time
BGATE Rise Time
BGATE Fall Time
CLOAD = 3000pF, 10% to 90%
CLOAD = 3000pF, 10% to 90%
40
40
90
80
ns
ns
VTGATE at Shutdown (VCLN-VTGATE)
ITGATE = –1µA
100
mV
VBGATE at Shutdown
ITGATE = 1µA
100
mV
4101f
3
LTC4101
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 4V unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.14
1.20
1.26
V
AC Present Comparator
VACP
DCDIV Threshold
VDCDIV Rising from 1V to 1.4V
●
DCDIV Hysteresis
25
DCDIV Input Bias Current
VDCDIV = 1.2V
–1
ACP VOH
IACP = –2mA
2
mV
1
µA
V
ACP VOL
IACP = 1mA
0.5
V
DCDIV to ACP Delay
VDCDIV = 1.3V
10
µs
SafetySignal Decoder
SafetySignal Trip (RES_COLD/RES_OR)
RTHA = 1130Ω ±1%, CTH = 1nF (Note 6)
RTHB = 54.9Ω ±1%
●
95
100
105
kΩ
SafetySignal Trip (RES_IDEAL/RES_COLD)
RTHA = 1130Ω ±1%, CTH = 1nF (Note 6)
RTHB = 54.9Ω ±1%
●
28.5
30
31.5
kΩ
SafetySignal Trip (RES_HOT/RES_IDEAL)
RTHA = 1130Ω ±1%, CTH = 1nF (Note 6)
RTHB = 54.9Ω ±1%
●
2.85
3
3.15
kΩ
SafetySignal Trip (RES_UR/RES_HOT)
RTHA = 1130Ω ±1%, CTH = 1nF (Note 6)
RTHB = 54.9Ω ±1%
●
425
500
575
Ω
Time Between SafetySignal Measurements
DCDIV = 1.3V
DCDIV = 1V
250
ms
ms
32
DACs
Charging Current Resolution
Guaranteed Monotonic Above IMAX/16
Charging Current Granularity
RILIM = 0
RILIM = 10k ±1%
RILIM = 33k ±1%
RILIM = Open (or Short to VDD)
Wake-Up Charging Current (IWAKE-UP)
All Values of RILIM
All Values of RVLIM
Charging Current Limit
CSP – BAT
RILIM = 0 (0-1A)
Charging Current = 0x03FF (0x0400 Note 7)
97.3
107.3
mV
RILIM = 10k ±1% (0-2A)
Charging Current = 0x07FE (0x0800 Note 7)
97.3
107.3
mV
RILIM = 33k ±1% (0-3A)
Charging Current = 0x0BFC (0x0C00 Note 7)
72.3
82.3
mV
97.3
107.3
mV
RILIM = 0pen (or Short to VDD) (0-4A)
Charging Current = 0x0FFC (0x1000 Note 7)
Charging Voltage Resolution
Guaranteed Monotonic (2.9V ≤ VBAT ≤ 5.6V)
10
●
1
2
4
4
mA
mA
mA
mA
80 (Note 5)
mA
11
Charging Voltage Granularity
Charging Voltage Limit
Bits
Bits
16
mV
RVLIM = 0
Charging Voltage = 0x1090 (Note 7)
4.206
4.240
4.274
V
RVLIM = 10k ±1%
Charging Voltage = 0x10D0 (Note 7)
4.270
4.304
4.338
V
RVLIM = 33k ±1%
Charging Voltage = 0x1150 (Note 7)
4.397
4.432
4.467
V
RVLIM = 100k ±1%
Charging Voltage = 0x11A0 (Note 7)
4.476
4.512
4.548
V
RVLIM = 0pen (or Short to VDD)
Charging Voltage = 0x1580 (Note 7)
5.460
5.504
5.548
V
4101f
4
LTC4101
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDCIN = 20V, VDD = 3.3V, VBAT = 4V unless otherwise noted. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIL
SCL/SDA Input Low Voltage
VDD = 3V and VDD = 5.5V
●
VIH
SCL/SDA Input High Voltage
VDD = 3V and VDD = 5.5V
●
VOL
SDA Output Low Voltage
IPULL-UP = 350µA
●
IIL
SCL/SDA Input Current
VSDA, VSCL = VIL
IIH
SCL/SDA Input Current
VSDA, VSCL = VIH
VOL
SMBALERT Output Low Voltage
IPULL-UP = 500µA
SMBALERT Output Pull-Up Current
VSMBALERT = VOL
TYP
MAX
UNITS
Logic Levels
–1
–17.5
SDA/SCL/SMBALERT Power Down Leakage VSDA, VSCL, VSMBALERT = 5.5V, VDD = OV
●
CHGEN Output Low Voltage
IOL = 100µA
●
CHGEN Output Pull-Up Current
VCHGEN = VOL
CHGEN Input Low Voltage
CHGEN Input High Voltage
Power-On Reset Duration
–10
–2
–17.5
–10
●
●
VDD = 3V
VDD = 5.5V
0.4
V
1
µA
1
µA
0.4
V
–3.5
µA
2
µA
0.5
V
–3.5
µA
0.9
2.5
VDD Ramp from 0V to >3V in <5µs
V
V
●
VOL
VIH
2.1
–1
ILEAK
VIL
0.8
V
3.9
V
V
100
µs
SMBus Timing (Refer to System Management Bus Specification, Revision 1.1, Section 2.1 for Timing Diagrams)
tHIGH
SCL Serial Clock High Period
IPULL-UP = 350µA, CLOAD = 250pF, RPU = 9.31k,
VDD = 3V and VDD = 5.5V
●
4
tLOW
SCL Serial Clock Low Period
IPULL-UP = 350µA, CLOAD = 250pF, RPU = 9.31k,
VDD = 3V and VDD = 5.5V
●
4.7
tR
SDA/SCL Rise Time
CLOAD = 250pF, RPU = 9.31k, VDD = 3V
and VDD = 5.5V
tF
SDA/SCL Fall Time
tSU:STA
tHD:STA
µs
15000
µs
●
1000
ns
CLOAD = 250pF, RPU = 9.31k, VDD = 3V
and VDD = 5.5V
●
300
ns
Start Condition Setup Time
VDD = 3V and VDD = 5.5V
●
4.7
µs
Start Condition Hold Time
VDD = 3V and VDD = 5.5V
●
4
µs
tHD:DAT
SDA to SCL Falling-Edge Hold Time,
Slave Clocking in Data
VDD = 3V and VDD = 5.5V
●
300
ns
tTIMEOUT
Time Between Receiving Valid
ChargingCurrent() and
ChargingVoltage() Commands
VDD = 3V and VDD = 5.5V
●
140
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: See Test Circuit.
Note 3: Does not include tolerance of current sense resistor.
Note 4: The LTC4101E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
175
210
sec
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Current accuracy dependent upon circuit compensation and sense
resistor.
Note 6: CTH is defined as the sum of capacitance on THA, THB and
SafetySignal.
Note 7: The corresponding overrange bit will be set when a HEX value
greater than or equal to this value is used.
4101f
5
LTC4101
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
INFET Response Time to
Reverse Current
Output Voltage vs Output Current
PWM Frequency vs Duty Cycle
0
Vgs OF PFET (2V/DIV)
–0.5
Id (REVERSE) OF
PFET (5A/DIV)
300
–1.0
PWM FREQUENCY (kHz)
Vs = 0V
OUTPUT VOLTAGE ERROR (%)
Vgs = 0
Vs OF PFET (5V/DIV)
350
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
VDCIN = 20V
VPROG = 4.176V
IPROG = 4V
–4.5
40
1A STEP
3A STEP
DISCONNECT
RECONNECT
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DUTY CYCLE (VOUT/VIN)
4101 G03
Efficiency at VPROG = 4.208V
100
VDCIN = 0V
35
25
20
15
10
92
88
VIN = 20V
84
80
76
5
72
0
0
LOAD CURRENT = 1A, 2A, 3A
DCIN = 12V
VFLOAT = 4.2V
VIN = 8V
96
30
POWER EFFICIENCY (%)
BATTERY LEAKAGE CURRENT (µA)
LOAD
STATE
0
Battery Leakage Current vs
Battery Voltage
3A STEP
DCIN = 9V
DCIN = 12V
DCIN = 24V
4101 G02
Disconnect/Reconnect Battery
(Load Dump)
1A STEP
PROGRAMMED CURRENT = 10%
100
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
OUTPUT CURRENT (A)
TEST PERFORMED ON DEMOBOARD
VCHARGE = 4.2V
VIN = 15VDC
CHARGER = ON
INFET = 1/2 Si4925DY
ICHARGE = <10mA
4101 G01
VFLOAT
1V/(DIV)
150
0
0
1.25µs/DIV
200
50
–5.0
Id = 0A
250
5
10
15
20
BATTERY VOLTAGE (V)
25
30
0.0
0.5
1.0
1.5 2.0
IOUT (A)
2.5
SMBus Accelerator Operation
3.5
4101 G07
4101 G05
4101 G04
3.0
Low Current Operation
0.6
VDD = 5V
5V CBUS = 200pF
VDD = 5V
VBAT = 4V
VDCIN = 20V
VPROG = 4.208V
0.5
ICHARGE (A)
0.4
LTC4101
RPULLUP = 15k
NO LOW
CURRENT
MODE
0.3
PROGRAMMED
CURRENT
0.2
0V
LOW
CURRENT
MODE
0.1
0
1µs/DIV
4101 G09
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
IPROG (A)
4101 G10
4101f
6
LTC4101
U W
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted.
Charging Current Error
Transfer Function of Charger
50
200
VDD = 5V
IBAT = 0.120A
OUTPUT VOLTAGE ERROR (V)
OUTPUT CURRENT ERROR (mA)
VDD = 5V
100
VDCIN = 20V
VDCIN = 9V
0
–100
–200
0
2
1
3
CHARGING CURRENT (A)
4
4101 G11
VDCIN = 9V
0
VDCIN = 20V
–50
VDCIN = 28V
–100
–150
0
1
2
3
4
5
CHARGING VOLTAGE (V)
6
4101 G12
U
U
U
PI FU CTIO S
TGATE (Pin 1): Drives the Top External P-MOSFET of the
Battery Charger Buck Converter.
PGND (Pin 2): High Current Ground Return for BGATE
Driver.
BGATE (Pin 3): Drives the Bottom External N-MOSFET of
the Battery Charger Buck Converter.
INFET (Pin 4): Drives the Gate of the External Input
P-MOSFET.
DCIN (Pin 5): External DC Power Source Input. Bypass to
ground with a 0.1µF capacitor.
CHGEN (Pin 6): Digital Bidirectional Pin to Enable Charger
Function. This pin is connected as a wired AND bus.
The following events will cause the POWER_FAIL bit in
the ChargerStatus register to become set:
1. An external device pulling the CHGEN signal to within
0.9V to GND;
2. The AC adapter voltage is not above the battery
voltage.
SMBALERT (Pin 7): Active Low Interrupt Output to Host
(referred to as the SMBALERT signal in the SMBus Revision 1.1 specification). Signals host that there has been a
change of status in the charger registers and that the host
should read the LTC4101 status registers to determine if
any action on its part is required. This signal can be
connected to the optional SMBALERT line of the SMBus.
Open drain with weak current source pull-up to VDD (with
Schottky to allow it to be pulled to 5V externally).
SDA (Pin 8): SMBus Data Signal from Main (host-controlled) SMBus. External pull-up resistor is required.
SCL (Pin 9): SMBus Clock Signal from Main (host-controlled) SMBus. External pull-up resistor is required.
ACP (Pin 10): This Output Indicates the Value of the DCDIV
Comparator. It can be used to indicate whether AC is
present or not.
DCDIV (Pin 11): Supply Divider Input. This is a high
impedance comparator input with a 1.2V threshold (rising
edge) and hysteresis.
GND (Pin 12): Ground for Digital and Analog Circuitry.
ILIM (Pin 13): An external resistor is connected between
this pin and GND. The value of the external resistor
programs the range and resolution of the programmed
charger current.
VLIM (Pin 14): An external resistor is connected between
this pin and GND. The value of the external resistor
programs the range and resolution of the charging
voltage.
4101f
7
LTC4101
U
U
U
PI FU CTIO S
THB (Pin 15): SafetySignal Force/Sense Pin to Smart
Battery. See description of operation for more detail. The
maximum allowed combined capacitance on THA, THB
and SafetySignal is 1nF (see Figure 4). A series resistor
54.9k needs to be connected between this pin and the
battery’s SafetySignal for this circuit to work correctly.
ITH (Pin 19): Control Signal of the Inner Loop of the
Current Mode PWM. Higher ITH corresponds to higher
charging current in normal operation. A 0.0015µF capacitor to GND filters out PWM ripple. Typical full-scale output
current is 40µA. Nominal voltage range for this pin is 0V
to 3V.
THA (Pin 16): SafetySignal Force/Sense Pin to Smart
Battery. See description of operation for more detail. The
maximum allowed combined capacitance on THA, THB
and SafetySignal is 1nF (see Figure 4). A series resistor
1130Ω needs to be connected between this pin and the
battery’s SafetySignal for this circuit to work correctly.
IDC (Pin 20): Bypass to GND with a 0.068µF Capacitor.
VDD (Pin 17): Power Supply Input for the LTC4101 Digital
Circuitry. Bypass this pin with 0.1µF. Typically between
3.3V and 5VDC.
VSET (Pin 18): Tap Point of the Programmable Resistor
Divider, which Provides Battery Voltage Feedback to the
Charger.
CSP (Pin 21): Current Amplifier CA1 Input. This pin and
the BAT pin measure the voltage across the sense resistor,
RSENSE, to provide the instantaneous current signals required for both peak and average current mode operation.
BAT (Pin 22): Battery Sense Input and the Negative
Reference for the Current Sense Resistor. A bypass capacitor of at least 10µF is required.
CLN (Pin 23): Negative Input to the Input Current Limiting
Circuit Block. If no current limit function is desired, connect this pin to CLP. The threshold is set at 100mV below
the voltage at the CLP pin. When used to limit supply
current, a filter is needed to filter out the switching noise.
CLP (Pin 24): Positive Input to the Input Current Limiting
Circuit Block. This pin also serves as a power supply for
the IC.
4101f
8
LTC4101
W
BLOCK DIAGRA
VBAT
VBAT
18
C5, 0.1µF
GND
11-BIT
VDAC
1.28V
OSCILLATOR
WATCHDOG
DETECT tON
SYSTEM
LOAD
3k
+
11.67µA
22
21
+
÷5
EA
+
–
PGND
R1
CLN
RCL
C9
CLP
DCIN
INFET
Q1
1
ICMP
PWM
LOGIC
–
IREV
3
+
2
–
CA2
+
100mV
+
CL1
–
23
24
gm = 1.5m
Ω
Q3
BGATE
S
Q R
gm = 1m
Ω
D1
TGATE
17mV
20
1.19V
19
IDC
C8
0.068µF
ITH
C6, 0.12µF
5.8V
10 ACP
DCDIV
11
4
CHGEN 6
VDD
C1, 0.1µF
C7
0.0015µF
R5, 6.04k
10-BIT
IDAC
5
CLP
VIN
CSP
BUFFERED
ITH
gm = 1m
–
1.19V
Q2
CSP
0V
CLP
CSP
20µF
3k
9k
20µF
L1
BAT
RSENSE
12
DCIN
–
–
CA1
+
Ω
C4
R4
0.03µF
100Ω
VSET
R11
1.2V
VIN
R10
10µA
17 VDD TO SMBUS
POWER SUPPLY
SMBALERT 7
TO HOST AND BATTERY
SDA 8
1.13k
LIMIT
DECODER
SCL 9
THA
54.9k
SMBus
INTERFACE
AND CONTROL
THB
16
15
THERMISTER
INTERFACE
13
14
ILIM
VLIM
RVLIM
RILIM
10k
Figure 2.
4101f
9
LTC4101
TEST CIRCUIT
LTC4101
21
CSP
22
18
BAT VSET
+
–
EA
VTOL =
VDAC
LT1055
DCIN = 21V
CLN = CLP = 20 V
VDD = 3.3V
ITH
BAT
VBAT – VVDAC
• 100
VVDAC
FOR VVDAC = 4.176 V(0 x 10
050)
19
+
–
+
1.19V
0.7V
–
4101 TC01
U
OPERATIO
Overview (Refer to Block Diagram)
The LTC4101 is composed of a battery charger section, a
charger controller, a 10-bit DAC to control charger current, an 11-bit DAC to control charger voltage, a SafetySignal
decoder, limit decoder and an SMBus controller block. If
no battery is present, the SafetySignal decoder indicates a
RES_OR condition and charging is disabled by the charger
controller (CHGEN = Low). Charging will also be disabled
if DCDIV is low, or the SafetySignal is decoded as
RES_HOT. If a battery is inserted and AC power is connected, the battery will be charged with an 80mA “wakeup” current. The wake-up current is discontinued after
tTIMEOUT if the SafetySignal is decoded as RES_UR or
RES_C0LD, and the battery or host doesn’t transmit
charging commands.
The SMBus interface and control block receives
ChargingCurrent() and ChargingVoltage() commands via
the SMBus. If ChargingCurrent() and ChargingVoltage()
command pairs are received within a tTIMEOUT interval, the
values are stored in the current and voltage DACs and the
charger controller asserts the CHGEN line if the decoded
SafetySignal value will allow charging to commence.
ChargingCurrent() and ChargingVoltage() values are compared against limits programmed by the limit decoder
block; if the commands exceed the programmed limits
these limits are substituted and overrange flags are set.
The charger controller will assert SMBALERT whenever
a status change is detected, namely: AC_PRESENT,
BATTERY_PRESENT, ALARM_INHIBITED, or V DD
power-fail. The host may query the charger, via the SMBus,
to obtain ChargerStatus() information. SMBALERT will be
deasserted upon a successful read of ChargerStatus() or
a successful Alert Response Address (ARA) request.
Battery Charger Controller
The LTC4101 charger controller uses a constant off-time,
current mode step-down architecture. During normal
operation, the top MOSFET is turned on each cycle when
the oscillator sets the SR latch and turned off when the
main current comparator ICMP resets the SR latch. While
the top MOSFET is off, the bottom MOSFET is turned
on until either the inductor current trips the current
comparator IREV, or the beginning of the next cycle.
The oscillator uses the equation,
tOFF =
(VDCIN – VBAT )
(VDCIN • fOSC )
4101f
10
LTC4101
U
OPERATIO
to set the bottom MOSFET on time. The result is quasiconstant frequency operation: the converter frequency
remains nearly constant over a wide range of output
voltages. This activity is diagrammed in Figure 3.
OFF
TGATE
ON
ON
tOFF
BGATE
OFF
TRIP POINT SET
BY ITH VOLTAGE
INDUCTOR
CURRENT
Charger Start-Up
When the charger is enabled, it will not begin switching
until the ITH voltage exceeds a threshold that assures initial
current will be positive. This threshold is 5% to 15% of the
maximum programmed current. After the charger begins
switching, the various loops will control the current at a
level that is higher or lower than the initial current. The
duration of this transient condition depends upon the loop
compensation, but is typically less than 1ms.
SMBus Interface
4101 F01
Figure 3.
The peak inductor current, at which ICMP resets the SR
latch, is controlled by the voltage on ITH. ITH is in turn
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative current.
Error amp CA2 compares this current against the desired
current programmed by the IDAC at the IDC pin and adjusts
ITH for the desired voltage across RSENSE.
The voltage at BAT is divided down by an internal resistor
divider set by the VDAC and is used by error amp EA to
decrease ITH if the divider voltage is above the 1.19V
reference.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter, to a preset level (100mV/
RCL). At input current limit, CL1 will decrease the ITH
voltage to reduce charging current.
An overvoltage comparator, OV, guards against transient
overshoots (>7%). In this case, the top MOSFET is turned
off until the overvoltage condition is cleared. This feature
is useful for batteries that “load dump” themselves by
opening their protection switch to perform functions such
as calibration or pulse mode charging.
PWM Watchdog Timer
There is a watchdog timer that observes the activity on the
TGATE pin. If TGATE stops switching for more than 40µs,
the watchdog activates and turns off the top MOSFET for
about 400ns. The watchdog engages to prevent very low
frequency operation in dropout – a potential source of audible
noise when using ceramic input and output capacitors.
All communications over the SMBus are interpreted by the
SMBus interface block. The SMBus interface is a SMBus
slave device. All internal LTC4101 registers may be updated and accessed through the SMBus interface, and
charger controller as required. The SMBus protocol is a
derivative of the I2CTM bus (Reference “I 2C-Bus and How
to Use It, V1.0” by Philips, and “System Management Bus
Specification,” Version 1.1, from the SBS Implementers
Forum, for a complete description of the bus protocol
requirements.)
All data is clocked into the shift register on the rising edge
of SCL. All data is clocked out of the shift register on the
falling edge of SCL. Detection of an SMBus Stop condition,
or power-on reset via the VDD power-fail, will reset the
SMBus interface to an initial state at any time.
The LTC4101 command set is interpreted by the SMBus
interface and passed onto the charger controller block as
control signals or updates to internal registers.
Description of Supported Battery Charger Functions
The functions are described as follows (see Table 1 also):
FunctionName() 'hnn (command code)
Description: A brief description of the function.
Purpose: The purpose of the function, and an example
where appropriate.
• SMBus Protocol: Refer to Section 5 of the Smart
Battery Charger specification for more details.
I2C is a trademark of Philips Electronics N.V.
*http://www. SBS-FORUM.org
4101f
11
LTC4101
U
OPERATIO
Input, Output or Input/Output: A description of the data
supplied to or returned by the function.
ChargerStatus() ('h13)
ChargerSpecInfo() ('h11)
Description: The SMBus Host uses this command to read
the LTC4101’s status bits.
Description: The SMBus Host uses this command to read
the LTC4101’s extended status bits.
Purpose: Allows the SMBus Host to determine the status
and level of the LTC4101.
Purpose: Allows the System Host to determine the specification revision the charger supports as well as other
extended status information.
• SMBus Protocol: Read Word.
Output: The CHARGER_SPEC indicates that the LTC4101
supports Version 1.1 of the Smart Battery Charger Specification. The SELECTOR_SUPPORT indicates that the
LTC4101 does not support the optional Smart Battery
Selector Commands.
ChargerMode() ('h12)
Description: The SMBus Host uses this command to set
the various charger modes. The default values are set to
allow a Smart Battery and the LTC4101 to work in concert
without requiring an SMBus Host.
Purpose: Allows the SMBus Host to configure the charger
and change the default modes. This is a write only function, but the value of the “mode” bit, INHIBIT_CHARGE
may be determined using the ChargerStatus() function.
• SMBus Protocol: Write Word.
Input: The INHIBIT_CHARGE bit allows charging to be
inhibited without changing the ChargingCurrent() and
ChargingVoltage() values. The charging may be resumed
by clearing this bit. This bit is automatically cleared when
power is reapplied or when a battery is reinserted.
The ENABLE_POLLING bit is not supported by the LTC4101.
Values written to this bit are ignored.
The POR_RESET bit sets the LTC4101 to its power-on
default condition.
The RESET_TO_ZERO bit sets the ChargingCurrent()and
ChargingVoltage() values to zero. This function ALWAYS
clears the ChargingVoltage() and ChargingCurrent() values to zero even if the INHIBIT_CHARGE bit is set.
• SMBus Protocol: Read Word.
Output: The CHARGE_INHIBITED bit reflects the status of
the LTC4101 set by the INHIBIT_CHARGE bit in the
ChargerMode() function.
The POLLING_ENABLED, VOLTAGE_NOTREG, and
CURRENT_NOTREG are not supported by the LTC4101.
The LTC4101 always reports itself as a Level 2 Smart
Battery Charger.
CURRENT_OR bit is set only when ChargingCurrent() is
set to a value outside the current regulation range of the
LTC4101. This bit may be used in conjunction with the
INHIBIT_CHARGE bit of the ChargerMode() and
ChargingCurrent() to determine the current capability of
the LTC4101. When ChargingCurrent() is set to the programmatic maximum current + 1, the CURRENT_OR bit
will be set.
VOLTAGE_OR bit is set only when ChargingVoltage() is
set to a value outside the voltage regulation range of the
LTC4101. This bit may be used in conjunction with the
INHIBIT_CHARGE bit of the ChargerMode() and
ChargingVoltage() to determine the voltage capability of
the LTC4101. When ChargingVoltage() is set to the
programmatic maximum voltage, the VOLTAGE_OR bit
will be set.
The RES_OR bit is set only when the SafetySignal resistance value is greater than 95kΩ. This indicates that the
SafetySignal is to be considered as an open circuit.
The RES_COLD bit is set only when the SafetySignal
resistance value is greater than 28.5kΩ. The SafetySignal
indicates a cold battery. The RES_COLD bit will be set
whenever the RES_OR bit is set.
The RES_HOT bit is set only when the SafetySignal
resistance is less than 3150Ω, which indicates a hot
battery. The RES_HOT bit will be set whenever the
RES_UR bit is set.
4101f
12
LTC4101
U
OPERATIO
Table 1: Summary of Supported Charger Functions
7'b0001_001
8'h12
0
0
0
0
0
0
0
0
0
0
0
0
0
Control
Reserved
Permitted
Values
Return
Values
Control
7'b0001_001
8'h3C
Register
Reserved
Permitted
Values
Return
Values
Write
Read
Alert Response
Address
7'b0001_100
N/A
LEVEL:3/LEVEL:2
CURRENT_OR
VOLTAGE_OR
RES_OR
RES_COLD
RES_HOT
Permitted
Values 1/0 1/0 1/0 1/0
Write
LTCO()
RES_UR
Unsigned integer representing voltage in mV
Ignored
0
1
1/0
Ign 1/0
0
0
1/0
Ignored
LTC4101's Version Identification
Ignored
1/0
0
0
0
0
0
0
1
Status
0
0
0
0
0
0
LTC4101's Address
Not Supported
Read
Byte
Return
Values
0
0
FULLY DISCHARGED
8'h16
Permitted
Values
FULLY_CHARGED
7'b0001_001
CHARGING_VOLTAGE[15:0]
OVER_CHARGED_ALARM
AlarmWarning()
Value
DISCHARGING
Write
Unsigned integer representing current in mA
INITIALIZED
8'h15
1
Permitted
Values
REMAINING_TIME_ALARM
7'b0001_001
0
CHARGING_CURRENT[15:0]
REMAINING_CAPACITY_ALARM
ChargingVoltage()
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
Reserved
Write
1/0 1/0
Value
TERMINATE_DISCHARGE_ALARM
8'h14
OVER_TEMP_ALARM
7'b0001_001
NO_LOWI
ChargingCurrent()
TERMINATE_CHARGE_ALARM
Read
ALARM_INHIBITED
Status
POWER_FAIL
8'h13
BATTERY_PRESENT
7'b0001_001
AC_PRESENT
ChargerStatus()
Ignored
RESERVED_ALARM
Write
1
CHARGE_INHIBITED
ChargerMode()
0
Undefined
Return
Values
Read
CHARGER_SPEC
INHIBIT_CHARGE
Reserved
ENABLE_POLLING
Info
D1 DO
POLLING_ENABLED
8'h11
D5 D4 D3 D2
POR_RESET
7'b0001_001
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6
RESET_TO_ZERO
Data
Type
VOLTAGE_NOTREG
Command
Code
CURRENT_NOTREG
ChargerSpecInfo()
SMBus
Address
ERROR
Access
SELECTOR_SUPPORT
Function
0
0
0
1
0
0
1
X
4101f
13
LTC4101
U
OPERATIO
The RES_UR bit is set only when the SafetySignal resistance value is less than 575Ω.
ALARM_INHIBITED bit is set if a valid AlarmWarning()
message has been received and charging is inhibited as a
result. This bit is cleared if both ChargingVoltage() and
ChargingCurrent() are rewritten to the LTC4101, power is
removed (DCDIV < VACP), or if a battery is removed. The
setting of the ALARM_INHIBITED will activate the LTC4101
SMBALERT pull-down.
POWER_FAIL bit is set if the LTC4101 does not have
sufficient DCIN voltage to charge the battery or if an
external device is pulling the CHGEN input signal low.
Charging is disabled whenever this bit is set. The setting
of this bit does not clear the values in the ChargingVoltage()
and ChargingCurrent() function values, nor does it necessarily affect the charging modes of the LTC4101.
BATTERY_PRESENT is set if a battery is present otherwise
it is cleared. The LTC4101 uses the SafetySignal
in order to determine battery presence. If the LTC4101
detects a RES_OR condition, the BATTERY_PRESENT bit
is cleared immediately. The LTC4101 will not set the
BATTERY_PRESENT bit until it successfully samples the
SafetySignal twice and does not detect a RES_OR condition on either sampling. If AC is not present (e.g. DCDIV <
VACP), this bit may not be set for up to one-half second
after the battery is connected to the SafetySignal. The
ChargingCurrent() and ChargingVoltage() function values
are immediately cleared whenever this bit is cleared.
Charging will never be allowed if this bit is cleared. A
change in BATTERY_PRESENT will activate the LTC4101
SMBALERT pull-down.
AC_PRESENT is set if the voltage on DCDIV is greater than
VACP. This does not necessarily indicate that the voltage on
DCIN is sufficient to charge the battery. A change in
AC_PRESENT will activate the LTC4101 SMBALERT pulldown.
ChargingCurrent() ('h14)
Description: The Battery, System Host or other master device sends the desired charging current (mA) to the LTC4101.
Purpose: The LTC4101 uses RILIM, the granularity of the
IDAC, and the value of the ChargingCurrent() function to
determine its charging current supplied to the battery. The
charging current will never exceed the maximum current
permitted by RILIM. The ChargingCurrent() value will be
truncated to the granularity of the IDAC. The charging
current will also be reduced if the battery voltage exceeds
the programmed charging voltage.
• SMBus Protocol: Write Word.
Input: The CHARGING_CURRENT is an unsigned 16 bit
integer specifying the requested charging current in mA.
The following table defines the maximum permissible
value of CHARGING_CURRENT that will not set the
CURRENT_OR in the ChargerStatus() function for a given
value of the RILIM:
RILIM
ChargingCurrent()
Current
Short to GND
0x0000 through 0x03FF
0mA through 1023mA
10kΩ ±1%
0x0000 through 0x07FF
0mA through 2047mA
33kΩ ±1%
0x0000 through 0x0BFF
0mA through 3071mA
Open (or short to VDD) 0x0000 through 0x0FFF
0mA through 4095mA
ChargingVoltage() ('h15)
Description: The Battery, SMBus Host or other master
device sends the desired charging voltage (mV) to the
LTC4101.
Purpose: The LTC4101 uses RVLIM, the granularity of the
VDAC, and the value of the ChargingVoltage() function to
determine its charging voltage supplied to the battery. The
charging voltage will never be forced beyond the voltage
permitted by RVLIM. The ChargingVoltage() value will be
truncated to the granularity of the VDAC. The charging
voltage will also be reduced if the battery current exceeds
the programmed charging current.
• SMBus Protocol: Write Word.
Input: The CHARGING_VOLTAGE is an unsigned 16-bit
integer specifying the requested charging voltage in mV.
The LTC4101 considers any value from 0x0001 through
0x044F the same as writing 0x0000. The following
4101f
14
LTC4101
U
OPERATIO
table defines the maximum permissible value of
CHARGING_VOLTAGE that will not set the VOLTAGE_OR
in the ChargerStatus() function for a given value of RVLIM:
RVLIM
Maximum ChargingVoltage()
Short to GND
0x1090 (4240mV)
10kΩ ± 1%
0x10D0 (4304mV)
33kΩ ± 1%
0x1150 (4432mV)
100kΩ ± 1%
0x11A0 (4512mV)
Open (or short to VDD)
0x1580 (5504mV)
AlarmWarning() ('h16)
Description: The Smart Battery, acting as a bus master
device, sends the AlarmWarning() message to the LTC4101
to notify it that one or more alarm conditions exist. Alarm
indications are encoded as bit fields in the Battery’s Status
register, which is then sent to the LTC4101 by this
function.
Purpose: The LTC4101 will use the information sent by
this function to properly charge the battery. The LTC4101
will only respond to certain alarm bits. Writing to this
function does not necessarily cause an alarm condition
that inhibits battery charging.
• SMBus Protocol: Write Word.
Input: Only the OVER_CHARGED_ALARM, TERMINATE
_CHARGE_ALARM, reserved (0x2000), and OVER
_TEMP_ALARM bits are supported by the LTC4101.
Writing a one to any of these specified bits will inhibit
the charging by the LTC4101 and will set the
ALARM_INHIBITED bit in the ChargerStatus() function. The
TERMINATE_DISCHARGE_ALARM, REMAINING_
CAPACITY_ALARM, REMAINING_TIME_ALARM, and the
ERROR bits are ignored by the LTC4101.
LTC0() ('h3C)
Description: The SMBus Host uses this command to
determine the version number of the LTC4101 and set
extended operation modes not defined by the Smart
Battery Charger Specification.
Purpose: This function allows the SMBus Host to
determine if the battery charger is an LTC4101. Identifying the manufacturer and version of the Smart Battery
Charger permits software to perform tasks specific to
a given charger. The LTC4101 also provides a means of
disabling the LOWI current mode of the IDAC.
• SMBus Protocol: Write Word.
Input: The NO_LOWI is the only bit recognized by this
function. The default value of NO_LOWI is zero. The
LTC4101 LOWI current mode provides a more accurate
average charge current when the charge current is less
than 1/16 of the full scale IDAC value. When the NO_LOWI
is set, a less accurate IDAC algorithm is used to generate
the charging current, but because the charger is not
pulsed on and off, it may be preferred.
• SMBus Protocol: Read Word.
Output: The NO_LOWI indicates the IDAC mode of operation. If clear, then the LOWI current mode will be used
when the charging current is less than 1/16 of the fullscale IDAC value.
The LTC Version Identification will always be 0x4040 for
the LTC4101.
Alert Response Address (ARA)
Description: The SMBus system host uses the Alert
Response Address to quickly identify the generator of an
SMBALERT# event.
Purpose: The LTC4101 will respond to an ARA if the
SMBALERT signal is actively pulling down the SMBALERT#
bus. The LTC4101 will follow the prioritization reporting as
defined in the System Management Bus Specification,
Version 1.1, from the SBS Implementers Forum.
• SMBus Protocol: A 7-bit Addressable Device Responds to an ARA.
Output: The Device Address will be sent to the SMBus
system host. The LTC4101 Device address is 0x12
(or 0x09 if just looking at the 7-bit address field).
The following events will cause the LTC4101 to pull-down
the SMBALERT# bus through the SMBALERT pin:
• Change of AC_PRESENT in the ChargerStatus()
function.
• Change of BATTERY_PRESENT in the ChargerStatus()
function.
• Setting ALARM_INHIBITED in the ChargerStatus()
function.
• Internal power-on reset condition.
4101f
15
LTC4101
U
OPERATIO
SMBus Accelerator Pull-Ups
Wake-up Charging Mode
Both SCL and SDA have SMBus accelerator circuits which
reduce the rise time on systems with significant capacitance on the two SMBus signals. The dynamic pull-up
circuitry detects a rising edge on SDA or SCL and applies
1mA to 10mA pull-up to VDD when VIN > 0.8V until VIN
< VDD – 0.8V (external pull-up resistors are still required
to supply DC current). This action allows the bus to meet
SMBus rise time requirements with as much as 250pF on
each SMBus signal. The improved rise time will benefit all
of the devices which use the SMBus, especially those
devices that use the I2C logic levels. Note that the dynamic
pull-up circuits only pull to VDD, so some SMBus devices
that are not compliant to the SMBus specifications may
still have rise time compliance problems if the SMBus pullup resistors are terminated with voltages higher than VDD.
The following conditions must be met in order to allow
wake-up charging of the battery:
The Control Block
3. The successful writing of the ChargingCurrent() AND
ChargingVoltage() function. The LTC4101 will proceed
to the controlled charging mode after these two functions are written.
The LTC4101 charger operations are handled by the
control block. This block is capable of charging the selected battery autonomously or under SMBus Host control. The control block can request communications with
the system management host (SMBus Host) by asserting
SMBALERT = 0; this will cause the SMBus Host, if present,
to poll the LTC4101.
The control block receives SMBus slave commands from
the SMBus interface block.
The control block allows the LTC4101 to meet the following Smart Battery-controlled (Level 2) charger
requirements:
1. Implements the Smart Battery’s critical warning messages over the SMBus.
2. Operates as an SMBus slave device that responds to
ChargingVoltage() and ChargingCurrent() commands
and adjusts the charger output parameters accordingly.
3. The host may control charging by disabling the Smart
Battery’s ability to transmit ChargingCurrent() and
ChargingVoltage() request functions and broadcasting
the charging commands to the LTC4101 over the SMBus.
1. The SafetySignal must be RES_COLD, RES_IDEAL, or
RES_UR.
2. AC must be present. This is qualified by DCDIV > VACP.
Wake-up charging initiates when a newly inserted battery
does not send ChargingCurrent() and ChargingVoltage()
functions to the LTC4101.
The following conditions will terminate the Wake-up Charging Mode.
1. A TTIMEOUT period is reached when the SafetySignal is
RES_COLD or RES_UR.
2. The SafetySignal is registering RES_OR.
4. The SafetySignal is registering RES_HOT.
5. The AC power is no longer present. (DCDIV < VACP)
6. The ALARM_INHIBITED becomes set in the
ChargerStatus() function.
7. The INHIBIT_CHARGE is set in the ChargerMode()
function.
8. The CHGEN pin is pulled low by an external device. The
LTC4101 will resume wake-up charging, if the CHGEN
pin is released by the external device. Toggling the
CHGEN pin will not reset the TTIMEOUT timer.
9. There is insufficient DCIN voltage to charge the battery.
The LTC4101 will resume wake-up charging when there
is sufficient DCIN voltage to charge the battery. This
condition will not reset the TTIMEOUT timer.
4. The LTC4101 will still respond to Smart Battery critical
warning messages without host intervention.
4101f
16
LTC4101
U
OPERATIO
Controlled Charging Algorithm Overview
7. RESET_TO_ZERO is set in the ChargerMode() function.
The following conditions must be met in order to allow
controlled charging to start on the LTC4101:
8. CHGEN pin is pulled low by an external device. The
LTC4101 will resume charging using the previous
ChargingVoltage() AND ChargingCurrent() function values, if the CHGEN pin is released by the external device.
1. The ChargingVoltage() AND ChargingCurrent() function must be written to non-zero values.
2. The SafetySignal must be RES_COLD, RES_IDEAL, or
RES_UR.
3. AC must be present. This is qualified by DCDIV > VACP.
The following conditions will stop the Controlled Charging
Algorithm and will cause the Battery Charger Controller to
stop charging:
1. The ChargingCurrent() AND ChargingVoltage() functions have not been written for TTIMEOUT.
2. The SafetySignal is registering RES_OR.
3. The SafetySignal is registering RES_HOT.
4. The AC power is no longer present. (DCDIV < VACP)
5. ALARM_INHIBITED is set in the ChargerStatus()
function.
6. INHIBIT_CHARGE is set in the ChargerMode() function.
Clearing INHIBIT_CHARGE will cause the LTC4101 to
resume charging using the previous ChargingVoltage()
AND ChargingCurrent() function values.
9. Insufficient DCIN voltage to charge the battery. The
LTC4101 will resume charging using the previous
ChargingVoltage() AND ChargingCurrent() function values, when there is sufficient DCIN voltage to charge the
battery.
10. Writing a zero value to ChargingVoltage() function.
11. Writing a zero value to ChargingCurrent() function.
The SafetySignal Decoder Block
This block measures the resistance of the SafetySignal
and features high noise immunity at critical trip points. The
low power standby mode supports only battery presence
SMB charger reporting requirements when AC is not
present. The SafetySignal decoder is shown in Figure 4.
The value of RTHA is 1.13k and RTHB is 54.9k.
SafetySignal sensing is accomplished by a state machine
that reconfigures the switches of Figure 4 using THA_SELB
and THB_SELB, a selectable reference generator, and two
comparators. This circuit has two modes of operation
based upon whether AC is present.
VDD
THA_SELB
RTHA
1.13k
16
+
MUX
THA
HI_REF
REF
LO_REF
VDD
THB_SELB
RTHB
54.9k
TH_HI
–
+
TH_LO
–
SafetySignal
CONTROL
15
RES_OR
THB
CSS
RSafetySignal
RES_COLD
LATCH
RES_H0T
RES_UR
4101 F04
Figure 4. SafetySignal Decoder Block
4101f
17
LTC4101
U
OPERATIO
When AC is present, the LTC4101 samples the value of the
SafetySignal and updates the ChargerStatus register approximately every 32ms. The state machine successively
samples the SafetySignal value starting with the RES_OR
≥ RES_COLD threshold, then RES_C0LD ≥ RES_IDEAL
threshold, RES_IDEAL ≥ RES_HOT threshold, and finally
the RES_HOT ≥ RES_UR threshold. Once the SafetySignal
range is determined, the lower value thresholds are not
sampled. The SafetySignal decoder block uses the previously determined SafetySignal value to provide the appropriate adjustment in threshold to add hysteresis. The RTHB
resistor value is used to measure the RES_OR ≥ RES_COLD
and RES_COLD ≥ RES_IDEAL thresholds by connecting
the THB pin to VDD and measuring the voltage resultant on
the THA pin. The RTHA resistor value is used to measure
the RES_IDEAL ≥ RES_HOT and RES_HOT ≥ RES_UR
thresholds by connecting the THA pin to VDD and measuring the voltage resultant on the THB pin.
The SafetySignal decoder block uses a voltage divider
network between VDD and GND to determine SafetySignal
range thresholds. Since the THA and THB inputs are
sequentially connected to VDD, this provides VDD noise
immunity during SafetySignal measurement.
When AC power is not available the SafetySignal block
supports the following low power operating features:
1. The SafetySignal is sampled every 250ms or less,
instead of 32ms.
2. A full SafetySignal status is sampled every 30s or less,
instead of every 32ms.
The SafetySignal impedance is interpreted according to
Table 4.
Table 4. SafetySignal State Ranges
SafetySignal
RESISTANCE
CHARGE
STATUS BITS
0Ω to 500Ω
RES_UR,
RES_HOT
BATTERY_PRESENT
Underrange
500Ω to 3kΩ
RES_HOT
BATTERY_PRESENT
Hot
3kΩ to 30kΩ
BATTERY_PRESENT
Ideal
30kΩ to 100kΩ
RES_COLD
BATTERY_PRESENT
Cold
Above 100kΩ
RES_OR
RES_COLD
Overrange
DESCRIPTION
Note: The underrange detection scheme is a very important feature of the
LTC4101. The RTHA/RSafetySignal divider trip point of 0.333 • VDD (1V) is
well above the 0.047 • VDD (140mV) threshold of a system using a 10k
pull-up. A system using a 10k pull-up would not be able to resolve the
important underrange to hot transition point with a modest 100mV of
ground offset between battery and SafetySignal detection circuitry. Such
offsets are anticipated when charging at normal current levels.
The required values for RTHA and RTHB are shown in
Table 5.
Table 5. SafetySignal External Resistor Values
EXTERNAL RESISTOR
VALUE (Ω)
RTHA
1130 ±1%
RTHB
54.9k ±1%
CSS represents the capacitance between the SafetySignal
and GND. CSS may be added to provide additional noise
immunity from transients in the application. CSS cannot
exceed 1nF if the LTC4101 is to properly sense the value
of RSafetySignal.
4101f
18
LTC4101
U
OPERATIO
The ILIM Decoder Block
The VLIM Decoder Block
The value of an external resistor connected from this pin
to GND determines one of four current limits that are used
for maximum charging current value. These limits provide
a measure of safety with a hardware restriction on charging current which cannot be overridden by software.
The value of an external resistor connected from this pin
to GND determines one of five voltage limits that are
applied to the charger output value. These limits provide
a measure of safety with a hardware restriction on charging voltage which cannot be overridden by software.
Table 6. ILIM Trip Points and Ranges
Table 7. VLIM Trip Points and Ranges (See Figure 5)
EXTERNAL
RESISTOR
(RILIM)
EXTERNAL
RESISTOR
(RVLIM)
ILIM VOLTAGE
CONTROLLED
CHARGING
CURRENT RANGE GRANULARITY
Short to GND
VILIM < 0.09VDD
0 < I < 1023mA
1mA
10k ±1%
0.17VVDD < VILIM
< 0.34VVDD
0 < I < 2046mA
2mA
33k ±1%
0.42VVDD < VILIM
< 0.59V
0 < I < 3068mA
4mA
0.66VVDD < VILIM
0 < I < 4092mA
Open (>250k,
or Short to VDD)
VLIM VOLTAGE
CONTROLLED
CHARGING VOLTAGE
(VOUT) RANGE
GRANULARITY
Short to
GND
VVLIM < 0.09VVCCP
2900mV < VOUT
< 4240mV
16mV
10k ±1%
0.17VVDD < VVLIM
< 0.34VVDD
2900mV < VOUT
< 4304mV
16mV
33k ±1%
0.42VVCCP < VVLIM
< 0.59VVDD
2900mV < VOUT
< 4432mV
16mV
100k ±1%
0.66VVDD < VVLIM
< 0.84VVDD
2900mV < VOUT
< 4512mV
16mV
Open or
Tied to VDD
0.91VVDD < VVLIM
2900mV < VOUT
< 5504mV
16mV
4mA
VDD
AC_PRESENT
12.5k
+
33k
25k
–
+
VLIM
14
–
25k
+
RVLIM
25k
4
VLIM [3:0]
ENCODER
–
+
12.5k
–
4101 F05
Figure 5. Simplified VLIM Circuit Concept (ILIM is Similar)
4101f
19
LTC4101
U
OPERATIO
The Voltage DAC Block
Note that the charger output voltage is offset by VREF.
Therefore, the value of VREF is subtracted from the SMBus
ChargingVoltage() value in order for the output voltage to
be programmed properly (without offset). If the
ChargingVoltage() value is below the nominal reference
voltage of the charger, nominally 1.104V, the charger
output voltage is programmed to zero. In addition, if the
ChargingVoltage() value is above the limit set by the VLIM
pin, then the charger output voltage is set to the value
determined by the VLIM resistor and the VOLTAGE_OR bit
is set. These limits are demonstrated in Figure 6.
6
RVLIM = 33k
CHARGER VBAT (V)
5
4
3
2
1
0
0
1
2
3
4
5
PROGRAMMED VALUE (V)
6
4101 F06
NOTE: THE LTC4101 CAN BE PROGRAMMED WITH ChargingVoltage() FUNCTION VALUES
BETWEEN 1.104V AND 2.9V, HOWEVER, THE BATTERY CHARGER CONTROLLER OUTPUT
VOLTAGE MAY BE ZERO WITH PROGRAMMED VALUES BELOW 2.9V.
IPROG
(FROM CA1 AMP)
IDC
ITH
–
20
RSET
VREF
19
+
∆-∑
MODULATOR
CHARGING_CURRENT
VALUE
4101 F07
Figure 7. Current DAC Operation
When a value less than 1/16th of the maximum current
allowed by ILIM is applied to the current DAC input, the
current DAC enters a different mode of operation called
LOWI. The current DAC output is pulse width modulated
with a high frequency clock having a duty cycle value of
1/8. Therefore, the maximum output current provided by
the charger is IMAX/8. The delta-sigma output gates this
low duty cycle signal on and off. The delta-sigma shift
registers are then clocked at a slower rate, about 45ms/bit,
so that the charger has time to settle to the IMAX/8 value.
The resulting average charging current is equal to that
requested by the ChargingCurrent() value.
Note: The LOWI mode can be disabled by setting the
NO_LOWI bit in the LTC0() function.
When wake-up is asserted to the current DAC block, the
delta-sigma is then fixed at a value equal to 80mA, independent of the ILIM setting.
Figure 6. Transfer Function of Charger
Input FET
The Current DAC Block
The current DAC is a delta-sigma modulator which controls the effective value of an external resistor, RSET, used
to set the current limit of the charger. Figure 7 is a
simplified diagram of the DAC operation. The delta-sigma
modulator and switch convert the ChargingCurrent() value,
received via the SMBus, to a variable resistance equal to:
1.25RSET/[ChargingCurrent()/ILIM[x]] = RIDC
Therefore, programmed current is equal to:
ICHARGE = (102.3mV/RSENSE) (ChargingCurrent()/ILIM[x]),
for ChargingCurrent() < ILIM[x].
The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLP pin,
and provides an indication of this condition at both the
CHGEN pin and the PWR_FAIL bit in the ChargerStatus()
register. It also controls the gate of the input FET to keep
a low forward voltage drop when charging and prevents
reverse current flow through the input FET.
If the input voltage is less than VCLP, it must go at least
130mV higher than VCLP to activate the charger. The
CHGEN pin is forced low unless this condition is met. The
gate of the input FET is driven to a voltage sufficient to keep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLP drops to less than 25mV,
4101f
20
LTC4101
U
OPERATIO
This feature is created by sensing total adapter output
current and adjusting charging current downward if a
preset adapter current limit is exceeded. True analog
control is used, with closed loop feedback ensuring that
adapter load current remains within limits. Amplifier CL1
in Figure 9 senses the voltage across RCL, connected
between the CLP and CLN pins. When this voltage exceeds
100mV, the amplifier will override programmed charging
current to limit adapter current to 100mV/RCL. A lowpass
filter formed by 4.99k and 0.1µF is required to eliminate
switching noise. If the current limit is not used, CLP should
be connected to CLP, but leave CLN connected to power.
the input FET is turned off slowly. If the voltage between
DCIN and CLP is ever less than –25mV, then the input FET
is turned off quickly to prevent significant reverse current
from flowing in the input FET. In this condition the CHGEN
pin is driven low and the charger is disabled.
The AC Present Block (AC_PRESENT)
The DCDIV pin is used to determine AC presence. If the
DCDIV voltage is above the DCDIV comparator threshold
(VACP), then the ACP output pin will be switched to VDD and
the AC_PRESENT bit in the ChargerStatus() function will
be set. If the DCDIV voltage is below the DCDIV comparator threshold minus the DCDIV comparator hysteresis,
then the ACP output pin is switched to GND and the
AC_PRESENT bit in the ChargerStatus() function is cleared.
The ACP output pin is designed to drive 2mA continuously.
Setting Input Current Limit
To set the input current limit, you need to know the
minimum wall adapter current rating. Subtract 7% for the
input current limit tolerance and use that current to determine the resistor value.
Adapter Limiting
RCL = 100mV/ILIM
ILIM = Adapter Min Current –
(Adapter Min Current • 7%)
An important feature of the LTC4101 is the ability to
automatically adjust charging current to a level which
avoids overloading the wall adapter. This allows the product to operate at the same time that batteries are being
charged without complex load management algorithms.
Additionally, batteries will automatically be charged at the
maximum possible rate of which the adapter is capable.
As is often the case, the wall adapter will usually have at
least a +10% current limit margin and many times one can
simply set the adapter current limit value to the actual
adapter rating (see Figure 9).
AVERAGE CHARGER CURRENT
ILIMIT/8
0
4101 F08
~40ms
Figure 8. Charging Current Waveform in Low Current Mode
LTC4101
CLP
–
24
CL1
+
+
VIN
CLN
C9
0.1µF
INFET
R1
4.99k
TO LOAD
23
100mV
4
*RCL =
RCL*
100mV
ADAPTER CURRENT LIMIT
4101 F09
Figure 9. Adapter Current Limiting
4101f
21
LTC4101
U
W
U U
APPLICATIO S I FOR ATIO
Charge Termination Issues
Warning
Batteries with constant current charging and voltagebased charger termination might experience problems
with reductions of charger current caused by adapter
limiting. It is recommended that input limiting feature be
defeated in such cases. Consult the battery manufacturer
for information on how your battery terminates charging.
DO NOT CHANGE THE VALUE OF RILIM DURING OPERATION. The value must remain fixed and track the RSENSE
value at all times. Changing the current setting can result
in currents that greatly exceed the requested value and
potentially damage the battery or overload the wall adapter
if no input current limiting is provided.
Setting Output Current Limit (Refer to Figure 1)
Inductor Selection
The LTC4101 current DAC and the PWM analog circuitry
must coordinate the setting of the charger current. Failure
to do so will result in incorrect charge currents.
Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value on
ripple current and low current operation must also be
considered. The inductor ripple current ∆IL decreases
with higher frequency and increases with higher VIN.
Table 9. Recommended Resistor Values
IMAX (A)
RSENSE (Ω) 1% RSENSE (W)
1.023
RILIM (Ω) 1%
0.100
0.25
0
2.046
0.05
0.25
10k
3.068
0.025
0.5
33k
4.092
0.025
0.5
Open
∆IL =
⎛ V ⎞
1
VOUT ⎜ 1 − OUT ⎟
( f)(L) ⎝ VIN ⎠
Table 8. Common RCL Resistor Values
Adapter
Rating (A)
–7% Adapter
Rating (A)
RCL Value*
(Ω)1%
RCL
Limit (A)
RCLPower
Dissipation (W)
RCL Power
Rating(W)
1.5
1.40
0.068
1.47
0.15
0.25
1.8
1.67
0.062
1.61
0.16
0.25
2.0
1.86
0.051
1.96
0.20
0.25
2.3
2.14
0.047
2.13
0.21
0.25
2.5
2.33
0.043
2.33
0.23
0.50
2.7
2.51
0.039
2.56
0.26
0.50
3.0
2.79
0.036
2.79
0.28
0.50
3.3
3.07
0.033
3.07
0.31
0.50
3.6
3.35
0.030
3.35
0.33
0.50
4.0
3.72
0.027
3.72
0.37
0.50
* Rounded to nearest 5% standard step value. Many non standard values are popular.
4101f
22
LTC4101
U
W
U
U
APPLICATIO S I FOR ATIO
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.4(IMAX). Remember the
maximum ∆IL occurs at the maximum input voltage. The
inductor value also has an effect on low current operation.
The transition to low current operation begins when the
inductor current reaches zero while the bottom MOSFET is
on. Lower inductor values (higher ∆IL) will cause this to
occur at higher load currents, which can cause a dip in
efficiency in the upper range of low current operation.
Table 10. Recommended Inductor Values
Inductance
VIN Range (V)
1
IMAX (A)
2
3* annd 4
≤ 7.5
16µH ± 20%
8µH ± 20%
4µH ± 20%
≤ 9.0
20µH ± 20%
10µH ± 20%
5µH ± 20%
≤ 12.0
24µH ± 20%
12µH ± 20%
6µH ± 20%
≤ 15.0
26µH ± 20%
13µH ± 20%
6.5µH ± 20%
≤ 28.0
30µH ± 20%
15µH ± 20%
7.5µH ± 20%
RSENSE
0.1Ω
0.05Ω
0.025Ω
* 3 Amp uses the same RSENSE that 4 amps uses. Thus the inductance can
be the same.
Choose and inductor who’s inductance value is equal to
or greater than the value shown. Values assume:
1.–32% RSS result from –20% inductance tolerance
and a –25% inductance loss at IMAX.
2.Inductor ripple current ratio of 0.51 of IOUT across
RSENSE.
3. VOUT is at 4.2V
Charger Switching Power MOSFET
and Diode Selection
Two external power MOSFETs must be selected for use
with the charger: a P-channel MOSFET for the top (main)
switch and an N-channel MOSFET for the bottom (synchronous) switch.
The peak-to-peak gate drive levels are set internally. This
voltage is typically 6V. Consequently, logic-level threshold
MOSFETs must be used. Pay close attention to the BVDSS
specification for the MOSFETs as well; many of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance RDS(ON), total gate capacitance QG, reverse
transfer capacitance CRSS, input voltage and maximum
output current. The charger is operating in continuous
mode so the duty cycles for the top and bottom MOSFETs
are given by:
Main Switch Duty Cycle = VOUT/VIN
Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN.
The MOSFET power dissipations at maximum output
current are given by:
PMAIN = VOUT/VIN(IMAX)2(1 + δ∆T)RDS(ON)
+ k(VIN)2(IMAX)(CRSS)(fOSC)
PSYNC = (VIN – VOUT)/VIN(IMAX)2(1 + δ∆T)RDS(ON)
Where δ∆T is the temperature dependency of RDS(ON) and
k is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the PMAIN equation
includes an additional term for transition losses, which are
highest at high input voltages. For VIN < 20V the high
current efficiency generally improves with larger MOSFETs, while for VIN > 20V the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CRSS actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage or during a short circuit when the duty cycle in this
switch in nearly 100%. The term (1 + δ∆T) is generally
given for a MOSFET in the form of a normalized RDS(ON) vs
temperature curve, but δ = 0.005/°C can be used as an
approximation for low voltage MOSFETs. CRSS = QGD/
∆VDS is usually specified in the MOSFET characteristics.
The constant k = 2 can be used to estimate the contributions of the two terms in the main switch dissipation
equation.
If the charger is to operate in low dropout mode or with a
high duty cycle less than 50%, then the bottomside
N-Channel efficiency generally improves with a larger
MOSFET. Using asymmetrical MOSFETs may achieve cost
savings or efficiency gains.
Both of the LTC4101 MOSFET drivers are optimized to take
advantage of MOSFETs QG values of less than 22nC and a
TD-off delay specification of around 60ns or less. Larger
FETs may work, but you must qualify them and monitor
LTC4101 temperature rise.
4101f
23
LTC4101
U
W
U U
APPLICATIO S I FOR ATIO
Using excessively large MOSFETs relative to the IMAX
charge current they are working with will actually reduce
efficiency at lighter current levels with very limited gain at
high currents. A good place to start looking for a suitable
MOSFET in a datasheet is to look for a part with an ID rating
a little over 2 times the IMAX charge current rating. For the
LTC4101, the P-channel FET can typically be scaled down
a bit to take advantage of the lower duty cycle limits.
However make sure you never exceed the PD rating of the
device.
The Schottky diode D1, shown in the Typical Application
on the back page, conducts during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on and
storing charge during the dead-time, which could cost as
much as 1% in efficiency. A 1A Schottky is generally a
good size for 4A regulators due to the relatively small
average current. Larger diodes can result in additional
transition losses due to their larger junction capacitance.
The diode may be omitted if the efficiency loss can be
tolerated.
Calculating IC Power Dissipation
The power dissipation of the LTC4101 is dependent upon
the gate charge of the top and bottom MOSFETs (Q2 & Q3
respectively) The gate charge (QG) is determined from the
manufacturer’s data sheet and is dependent upon both the
gate voltage swing and the drain voltage swing of the
MOSFET. Use 6V for the gate voltage swing and VDCIN for
the drain voltage swing.
PD = VDCIN • (fOSC (QGQ2 + QGQ3) + IDCIN) + VDD • IDD
Example: VDCIN = 12V, fOSC = 345kHz, QGQ2 = 25nC,
QGQ3 = 15nC, IDCIN = 5mA, VDD = 5.5V,
IDD = 1mA.
Soft-Start and Undervoltage Lockout
The LTC4101 is soft-started by the 0.12µF capacitor on the
ITH pin. On start-up, ITH pin voltage will rise quickly to 0.5V,
then ramp up at a rate set by the internal 30µA pull-up
current and the external capacitor. Battery charging
current starts ramping up when ITH voltage reaches 0.8V
and full current is achieved with ITH at 2V. With a 0.12µF
capacitor, time to reach full charge current is about 2ms
and it is assumed that input voltage to the charger will
reach full value in less than 2ms. The capacitor can be
increased up to 1µF if longer input start-up times are
needed.
In any switching regulator, conventional timer-based
soft-starting can be defeated if the input voltage rises
much slower than the time out period. This happens
because the switching regulators in the battery charger
and the computer power supply are typically supplying a
fixed amount of power to the load. If input voltage comes
up slowly compared to the soft-start time, the regulators
will try to deliver full power to the load when the input
voltage is still well below its final value. If the adapter is
current limited, it cannot deliver full power at reduced
output voltages and the possibility exists for a quasi
“latch” state where the adapter output stays in a current
limited state at reduced output voltage. For instance, if
maximum charger plus computer load power is 30W, a
15V adapter might be current limited at 2.5A. If adapter
voltage is less than (30W/2.5A = 12V) when full power is
drawn, the adapter voltage will be pulled down by the
constant 30W load until it reaches a lower stable state
where the switching regulators can no longer supply full
load. This situation can be prevented by utilizing the
DCDIV resistor divider, set higher than the minimum
adapter voltage where full power can be achieved.
PD = 231mW
4101f
24
LTC4101
U
W
U U
APPLICATIO S I FOR ATIO
Input and Output Capacitors
The output capacitor (C3) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:
In the 4A Lithium Battery Charger (Typical Application on
back page), the input capacitor (C2) is assumed to absorb
all input switching ripple current in the converter, so it
must have adequate ripple current rating. Worst-case
RMS ripple current will be equal to one half of output
charging current. Actual capacitance value is not critical.
Solid tantalum low ESR capacitors have high ripple current rating in a relatively small surface mount package, but
caution must be used when tantalum capacitors are used
for input or output bypass. High input surge currents can
be created when the adapter is hot-plugged to the charger
or when a battery is connected to the charger. Solid
tantalum capacitors have a known failure mechanism
when subjected to very high turn-on surge currents. Only
Kemet T495 series of “Surge Robust” low ESR tantalums
are rated for high surge conditions such as battery to
ground.
⎛ V ⎞
0.29(VBAT )⎜ 1 – BAT ⎟
⎝ VDCIN ⎠
IRMS =
(L1)(f)
For example, VDCIN = 12V, VBAT = 4.2V, L1 = 10µH, and
f = 300kHz, IRMS = 0.26A.
EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or inductors
may be added to increase battery impedance at the300kHz
switching frequency. Switching ripple current splits between the battery and the output capacitor depending on
the ESR of the output capacitor and the battery impedance. If the ESR of C3 is 0.2Ω and the battery impedance
is raised to 4Ω with a bead or inductor, only 5% of the
current ripple will flow in the battery.
The relatively high ESR of an aluminum electrolytic for C1,
located at the AC adapter input terminal, is helpful in
reducing ringing during the hot-plug event. Refer to AN88
for more information.
Protecting SMBus Inputs
The SMBus inputs, SCL and SDA, are exposed to uncontrolled transient signals whenever a battery is connected
to the system. If the battery contains a static charge, the
SMBus inputs are subjected to transients which can cause
damage after repeated exposure. Also, if the battery’s
positive terminal makes contact to the connector before
the negative terminal, the SMBus inputs can be forced
below ground with the full battery potential, causing a
potential for latch-up in any of the devices connected to the
SMBus inputs. Therefore it is good design practice to
protect the SMBus inputs as shown in Figure 10.
The highest possible voltage rating on the capacitor will
minimize problems. Consult with the manufacturer before
use. Alternatives include new high capacity ceramic (at
least 20µF) from Tokin, United Chemi-Con/Marcon, et al.
Other alternative capacitors include OSCON capacitors
from Sanyo.
VDD
CONNECTOR
TO BATTERY
TO SYSTEM
4101 F13
Figure 10. Recommended SMBus Transient Protection
4101f
25
LTC4101
U
W
U U
APPLICATIO S I FOR ATIO
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electrical field radiation and high frequency resonant problems, proper layout of the components connected to the IC
is essential. (See Figure 11.) Here is a PCB layout priority
list for proper layout. Layout the PCB using this specific
order.
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that connect to the switching FET source pins. The IC can be
placed on the opposite side of the PCB relative to above.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
4. Place the output current sense resistor right next to
the inductor output but oriented such that the IC’s
current sense feedback traces going to resistor are not
long. The feedback traces need to be routed together
as a single pair on the same layer at any given time with
smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at the
sense resistor location.
5. Place output capacitors next to the sense resistor
output and ground.
6. Output capacitor ground connections need to feed
into same copper that connects to the input capacitor
ground before tying back into system ground.
Interfacing with a Selector
The LTC4101 is designed to be used with a true analog
multiplexer for the SafetySignal sensing path. Some selector ICs from various manufacturers may not implement
this. Consult LTC applications department for more
information.
Electronic Loads
The LTC4101 is designed to work with a real battery.
Electronic loads will create instability within the LTC4101
preventing accurate programming currents and voltages.
Consult LTC applications department for more
information.
SWITCH NODE
L1
VBAT
VIN
C2
HIGH
FREQUENCY
CIRCULATING
PATH
D1
C4
BAT
DIRECTION OF CHARGING CURRENT
RSENSE
4101 F14
4101 F15
TO CSP AND BAT
Figure 11. High Speed Switching Path
Figure 12. Kelvin Sensing of Charging Current
4101f
26
LTC4101
U
PACKAGE DESCRIPTIO
G Package
24-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
7.90 – 8.50*
(.311 – .335)
24 23 22 21 20 19 18 17 16 15 14 13
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10 11 12
2.0
(.079)
MAX
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
0.65
(.0256)
BSC
0.22 – 0.38
(.009 – .015)
TYP
0.05
(.002)
MIN
G24 SSOP 0204
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
4101f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC4101
U
TYPICAL APPLICATIO
LTC4101 Li-Ion Battery Charger ILIM = 4A/VLIM = 4.240V, Adapter Rating = 2.7A
RCL
0.033Ω
0.5W
1%
DCIN
9V TO 12V
DCIN
FROM WALL
ADAPTER
Q1
C9
0.1µF
10V
C1
0.1µF
R10
6.04k
1%
4
5
11
R11
1.21k
1%
R5
6.04k
1%
24
23
INFET CLP
CLN
TGATE
DCIN
C6, 0.12µF
10V, X7R
C7, 0.0015µF
10V, X7R
20
ITH
13
10
3V TO 5.5V
10k
6
10k
D2
7
SDA
D3
8
D4
9
SCL
Q2
C2, C3
10µF × 2
16V
PGND
3
D1
Q3
2
L1
6µH
4A
LTC4101
IDC
C8, 0.068µF
12
10V, X7R
GND
0.1µF
17
10V
VDD
14
1
DCDIV
BGATE
19
SYSTEM
LOAD
R1
4.9k
CSP
BAT
21
22
C4
0.03µF
25V
VLIM
ILIM
VSET
18
C5
0.1µF
10V
ACP
CHGEN
THA
SMBALERT
THB
SDA
SCL
D5
RSNS
0.025Ω
0.5W, 1%
16
DCIN
100k
Q4
1/2 Si790IEDN
C4,C5
10µF × 2
10V
R4
100Ω
10k
RTHA
1.13k
1%
SafetySignal
SDA
15
RTHB
54.9k
1%
D1: MBRM140T3
D2-D5: SMALL SIGNAL SCHOTTKY
Q1: 1/2 Si790IEDN
Q2: FDS6685
Q3: Si7804DN
SMART
BATTERY
SCL
4101 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1760
Smart Battery System Manager
Autonomous Power Management and Battery Charging for Two Smart
Batteries, SMBus Rev 1.1 Compliant
LTC4006
Small, High Efficiency, Fixed Voltage,
Lithium-Ion Battery Charger
Constant Current/Constant Voltage Switching Regulator with Termination
Timer, AC Adapter Current Limit and SafetySignal Sensor
in a Small 16-Pin Package
LTC4007
High Efficiency, Programmable Voltage
Battery Charger with Termination
Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter
Current Limit, SafetySignal Sensor and Indicator Outputs
LTC4008
High Efficiency, Programmable Voltage/Current
Battery Charger
Constant Current/Constant Voltage Switching Regulator; Resistor Voltage/
Current Programming, AC Adapter Current Limit and SafetySignal Sensor
LTC4010
High Efficiency Standalone Nickel Battery Charger
Complete NiMH/NiCd Charger in a 16-Pin TSSOP Package, Constant-Current
Switching Regulator
LTC4011
High Efficiency Standalone Nickel Battery Charger
Complete NiMH/NiCd Charger in a 20-Pin TSSOP Package, PowerPathTM
Control. Constant-Current Switching Regulator
LTC4060
Standalone Linear NiMH/NiCd Fast Charger
Complete NiMH/NiCd Charger in a Small Leaded or Leadless 16-Pin Package,
No Sense Resistor or Blocking Diode Required
LTC4100
Smart Battery Charger Controller
For Smart Batteries with Voltages Above 5.5V
LTC4412
Low Loss PowerPath Controller
Very Low Loss Replacement for Power Supply OR’ing Diodes Using
Minimal External Components
4101f
28
Linear Technology Corporation
LT 0606 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2006