a Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem AD608 The RF and LO bandwidths both exceed 500 MHz. In a typical IF application, the AD608 will accept the output of a 240 MHz SAW filter and downconvert it to a nominal 10.7 MHz IF with a conversion gain of 24 dB (ZIF = 165 Ω). The AD608’s logarithmic/limiting amplifier section handles any IF from LF to as high as 30 MHz. FEATURES Mixer –15 dBm 1 dB Compression Point –5 dBm IP3 24 dB Conversion Gain >500 MHz Input Bandwidth Logarithmic/Limiting Amplifier 80 dB RSSI Range 638 Phase Stability over 80 dB Range Low Power 21 mW at 3 V Power Consumption CMOS-Compatible Power-Down to 300 mW typ 200 ns Enable/Disable Time The mixer is a doubly-balanced “Gilbert-Cell” type and operates linearly for RF inputs spanning –95 dBm to –15 dBm. It has a nominal –5 dBm third-order intercept. An onboard LO preamplifier requires only –16 dBm of LO drive. The mixer’s current output drives a reverse-terminated, industry-standard 10.7 MHz 330 Ω filter. The nominal logarithmic scaling is such that the output is +0.2 V for a sinusoidal input to the IF amplifier of –75 dBm and +1.8 V at an input of +5 dBm; over this range the logarithmic conformance is typically ± 1 dB. The logarithmic slope is proportional to the supply voltage. A feedback loop automatically nulls the input offset of the first stage down to the submicrovolt level. APPLICATIONS PHS, GSM, TDMA, FM, or PM Receivers Battery-Powered Instrumentation Base Station RSSI Measurement The AD608’s limiter output provides a hard-limited signal output at 400 mV p-p. The voltage gain of the limiting amplifier to this output is more than 100 dB. Transition times are 11 ns and the phase is stable to within ± 3° at 10.7 MHz for signals from –75 dBm to +5 dBm. GENERAL DESCRIPTION The AD608 provides both a low power, low distortion, low noise mixer and a complete, monolithic logarithmic/limiting amplifier using a “successive-detection” technique. It provides both a high speed RSSI (Received Signal Strength Indicator) output with 80 dB dynamic range and a hard-limited output. The RSSI output is from a two-pole post-demodulation lowpass filter and provides a loadable output voltage of +0.2 V to +1.8 V. The AD608 operates from a single 2.7 V to 5.5 V supply at a typical power level of 21 mW at 3 V. The AD608 is enabled by a CMOS logic-level voltage input, with a response time of 200 ns. When disabled, the standby power is reduced to 300 µW within 400 ns. The AD608 is specified for the industrial temperature range of –25°C to +85°C for 2.7 V to 5.5 V supplies and –40°C to +85°C for 4.5 V to 5.5 V supplies. It comes in a 16-pin plastic SOIC. FUNCTIONAL BLOCK DIAGRAM 24dB MIXER GAIN IF INPUT –75dBm TO +15dBm2 ±6mA MAX OUTPUT (±890mV INTO 165Ω) RFHI 5 MIXER RF INPUT –95 TO –15dBm1 RFLO ≈ MXOP 7 BPF DRIVER 6 VMID LO PREAMP 10.7MHz BANDPASS FILTER 330Ω 9 5-STAGE IF AMPLIFIER (16dB PER STAGE) 330Ω 8 BIAS 1 +2.7V TO 5.5V 2 3 LO INPUT –16dBm 4 IFLO 100Ω RSSI RSSI OUTPUT 11 20mV/dB 0.2V TO 1.8V COM3 12 VPS2 14 +2.7V TO 5.5V LMOP FINAL LIMITER 10 100nF ≈ 2MHz LPF 10nF MID-SUPPLY IF BIAS COM2 7 FULL-WAVE RECTIFIER CELLS IFHI 15 LIMITER OUTPUT 400mVp-p 13 LOHI VPS1 COM1 110dB LIMITER GAIN 90dB RSSI 3dB NOMINAL INSERTION LOSS 18nF FDBK AD608 ±50µA PRUP 16 CMOS LOGIC INPUT REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. NOTES: 1 –15dBm = ±56mV MAX FOR LINEAR OPERATION 2 39.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY © Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD608–SPECIFICATIONS (@ T = + 258C, Supply = 3 V, dBm is referred to 50 V, unless otherwise noted) A Model Conditions MIXER PERFORMANCE RF and LO Frequency Range LO Power Conversion Gain Noise Figure 1 dB Compression Point Third-Order Intercept Input Resistance Input Capacitance LIMITER PERFORMANCE Gain Limiting Threshold Input Resistance Input Capacitance Phase Variation DC Level Output Level Rise and Fall Times Output Impedance RSSI PERFORMANCE Nominal Slope Nominal Intercept Minimum RSSI Voltage Maximum RSSI Voltage RSSI Voltage Intercept Logarithmic Linearity Error RSSI Response Time Output Impedance POWER-DOWN INTERFACE Logical Threshold Input Current Power-Up Response Time Power-Down Response Time Power-Down Current POWER SUPPLY Operating Range Powered Up Current OPERATING TEMPERATURE TMIN to TMAX TMIN to TMAX Min Input Terminated in 50 Ω Driving Doubly-Terminated 330 Ω IF Filter, ZIF = 165 Ω Matched Input, fRF = 100 MHz Matched Input, fRF = 240 MHz Input Terminated in 50 Ω fRF = 240 MHz and 240.02 MHz, fLO = 229.3 MHz fRF = 100 MHz (See Table I) fRF = 100 MHz (See Table I) 19 Full Temperature and Supply Range 3° rms Phase Jitter at 10.7 MHz 280 kHz IF Bandwidth –75 dBm to +5 dBm IF Input Signal at 10.7 MHz Center of Output Swing (VPOS-1) Limiter Output Driving 5 kΩ Load Driving a 5 pF Load At 10.7 MHz At VPOS = 3 V; Proportional to VPOS –75 dBm Input Signal +5 dBm Input Signal 0 dBm Input Signal –75 dBm to +5 dBm Input Signal at IFHI 90% RF to 50% RSSI At Midscale 17.27 1.57 System Active on Logical High For Logical High Active Limiter Output To 200 µA Supply Current AD608 Typ Max Units 500 –16 24 11 16 –15 –5 1.9 3 MHz dBm dB dB dB dBm dBm kΩ pF 28 110 –75 dB dBm 10 3 ±3 2 400 11 200 kΩ pF Degree V mV p-p ns Ω 20 –85 0.2 1.8 ±1 200 250 23.27 1.82 1.5 75 200 400 100 –25°C to +85°C –40°C to +85°C VPOS = 3 V 2.7 4.5 VPOS = 2.7 V to 5.5 V VPOS = 4.5 V to 5.5 V –25 –40 mV/dB dBm V V V dB ns Ω V µA ns ns µA 5.5 5.5 V V mA +85 +85 °C °C 7.3 Specifications subject to change without notice. –2– REV. B AD608 ABSOLUTE MAXIMUM RATINGS 1 PIN DESCRIPTIONS Supply Voltage VPS1, VPS2 . . . . . . . . . . . . . . . . . . . . . . +6 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW Temperature Range . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . +300°C NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 16-Pin SOIC Package: θJA = 110°C/W. ORDERING GUIDE Model AD608AR Temperature Range Package Option –25°C to +85°C, 2.7 V to 5.5 V Supplies; –40°C to +85°C, 4.5 V to 5.5 V Supplies R-16A* *R = Small Outline IC (SOIC). Pin Mnemonic Description 1 2 3 4 5 6 7 8 VPS1 COM1 LOHI COM2 RFHI RFLO MXOP VMID 9 10 11 IFHI IFLO RSSI 12 13 14 15 16 COM3 FDBK VPS2 LMOP PRUP Positive Supply Input Common Local Oscillator Input Connection Common RF Input, Noninverting RF Input, Inverting Mixer Output Midpoint Supply Bias Output IF Input, Noninverting IF Input, Inverting Received Signal Strength Indicator Output Output Common Offset-Null Feedback Loop Output Limiter Positive Supply Input Limiter Output Power-Up TERMINAL DIAGRAM VPS1 1 16 PRUP COM1 2 15 LMOP LOHI 3 COM2 4 RFHI 5 –3– 13 FDBK TOP VIEW 12 COM3 (Not to Scale) 11 RSSI RFLO 6 MXOP 7 10 IFLO VMID 8 9 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD608 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B 14 VPS2 AD608 IFHI WARNING! ESD SENSITIVE DEVICE AD608 PRUP IN TRIGGER U1A U1B 4.7k VPOS 0.1µF 47kΩ 1 VPS1 PRUP 16 2 COM1 LMOP 15 3 LOHI VPS2 14 4 COM2 FDBK 13 5 RFHI COM3 12 47kΩ NC 1nF 1 VPS1 PRUP 16 2 COM1 LMOP 15 3 LOHI VPS2 14 4 COM2 FDBK 13 5 RFHI COM3 12 6 RFLO RSSI 11 7 MXOP IFLO 10 8 VMID IFHI 9 LO IN 51.1Ω 0.1µF VPOS 0.1µF 51.1Ω 1nF 1nF 51.1Ω 1nF LMOP OUT 0.1µF RF IN 51.1Ω 1nF 18nF 100Ω RSSI OUTPUT 10nF RSSI 11 7 MXOP IFLO 10 8 VMID IFHI 9 0.1µF 0.1µF 301Ω 10nF 332Ω IF OUT 54.9Ω IF INPUT 100Ω NC 301Ω 0.1µF 332Ω 0.1µF 18nF AD608 332Ω 332Ω AD608 6 RFLO 18nF NC = NO CONNECT 54.9Ω U1 – 74HC00 Figure 2. Mixer Test Board Schematic Figure 1. IF Test Board Schematic 3.0 0 25.0 –1 2.5 –2 24.0 23.5 23.0 2.0 –3 RSSI – V RESPONSE – dB CONVERSION GAIN – dB 24.5 –4 –5 5V 1.5 1.0 3V –6 0.5 22.5 –7 –8 22.0 0 50 100 150 200 250 300 350 400 450 500 RF FREQUENCY – MHz Figure 3. Mixer Conversion Gain vs. Frequency 0 10 20 30 40 50 60 IF FREQUENCY – MHz 70 0 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT POWER AT IFHI – dBm 80 Figure 4. Mixer IF Port Bandwidth Figure 5. IF RSSI Output vs. Supply Voltage (Ambient Temperature) 4.0 3.0 3.0 +85 +25 FLUKE 6082A SYNTHESIZER –25 IF TEST BOARD 2.0 RSSI – V 2.0 IFHI 1.5 10.7 MHz 1.0 Figure 6. IF RSSI Output vs. Temperature (3 V Supply) HP34401A VPOS DCPS DMM 3V 1.0 3V 0 5V –1.0 –2.0 HP3366A 0.5 0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT POWER – dBm RSSI RSSI ERROR – dB 2.5 10 0 10 Figure 7. Test Circuit for IF RSSI Output vs. Supply Voltage (Ambient Temperature) (Figure 5) and IF RSSI Output vs. Temperature (3 V Supply) (Figure 6) and RSSI Error vs. Input Power (Figure 8) –4– –3.0 –4.0 –80 –70 –60 –50 –40 –30 –20 –10 INPUT POWER – dBm 0 10 Figure 8. RSSI Error vs. Input Power REV. B AD608 60mV/DIV RSSI 800mV/DIV LMOP 100ns/DIV PRUP 1V /DIV 100ns/DIV 20ns/DIV Figure 9. RSSI Power-Up Response FLUKE 6082A SYNTHESIZER IF TEST BOARD IFHI 10.7 MHz RSSI PRUP 0dBm TEK P6201 FET PROBE Figure 13. Limiter Rise and Fall Times HP54120A DIGITAL OSCILLOSCOPE TRIGGER FLUKE 6082A SYNTHESIZER IF TEST BOARD CH 1 IFHI CH 2 LMOP 10.7 MHz VPOS HP54120A TEK P6201 FET PROBE DIGITAL OSCILLOSCOPE VPOS 0dBm DCPS DCPS 3V 3V HP3366A HP3366A Figure 10. Test Circuit for RSSI Power-Up Response (Figure 9) Figure 14. Test Circuit for Limiter Rise and Fall Times (Figure 13) 200mV/DIV 100ns/DIV IFHI LMOP 220mV/DIV RSSI PRUP 1V/DIV 800mV/DIV 50ns/DIV 100ns/DIV Figure 11. RSSI Pulse Response/RSSI Rise Time FLUKE 6082A SYNTHESIZER CH 1 IF TEST BOARD COUPLER 10.7 MHz Figure 15. Limiter Power-Up Response Time MCL ZDC-20-1 IFHI RSSI TEK P6201 FET PROBE FLUKE 6082A SYNTHESIZER IFHI CH 2 10.7 MHz VPOS 0dBm 0dBm DCPS HP3366A 3V IF TEST BOARD HP54120A DIGITAL OSCILLOSCOPE LMOP PRUP TRIGGER TEK P6201 FET PROBE HP54120A DIGITAL OSCILLOSCOPE CH 1 CH 2 VPOS DCPS 3V HP6633A Figure 12. Test Circuit for RSSI Pulse Response/RSSI Rise Time (Figure 11) REV. B Figure 16. Test Circuit for Limiter Power-Up Response Time (Figure 15) –5– 5 10 4 9 RMS JITTER – Degrees RELATIVE PHASE – Degrees AD608 3 2 1 0 –1 –2 7 6 5 4 3 –3 2 –4 1 –5 –80 –70 –60 –50 –40 –30 –20 –10 INPUT POWER – dBm 0 0 –80 –70 –60 –50 –40 –30 –20 –10 0 INPUT POWER AT IFHI – dBm 10 Figure 17. Limiter Phase Performance vs. Input Power at IFHI MCL FLUKE 6082A SYNTHESIZER ZDC-20-1 10 Figure 19. Limiter Jitter Performance vs. Input Power at IFHI IF TEST BOARD TEK P6201 COUPLER 10.7 MHz 8 HP8494A HP8495A IFHI RSSI FET PROBE HP8447A DCPS HP3366A 3V BPF CH 1 280kHz BW 10.7MHz CF TRIG TOKO SK107MK1-A0-10 HP54120A DIGITAL OSCILLOSCOPE Figure 18. Test Circuit for Limiter Phase Performance vs. Input Power at IFHI (Figure 17) and Limiter Jitter Performance vs. Input Power at IFHI (Figure 19) –6– REV. B AD608 THEORY OF OPERATION Mixer Gain The AD608 (Figure 20) consists of a mixer followed by a logarithmic IF strip with RSSI and hard limited outputs. Each section will be described below. The mixer’s conversion gain is the product of its transconductance and the impedance seen at pin MXOP. For a 330 Ω parallel-terminated filter at 10.7 MHz, the load impedance is 165 Ω, the gain is 24 dB, and the output is 15.85 × 56.2 mV, or ± 891 mV, centered on the midpoint of the supply voltage. For other load impedances, the expression for the gain in dB is Mixer The mixer is a doubly-balanced modified Gilbert cell mixer. Its maximum input level for linear operation is ± 56.2 mV regardless of the impedance across the mixer’s inputs, or –15 dBm for a 50 Ω input termination. The input impedance of the mixer can be modeled as a simple parallel RC network; the values versus frequency are listed in Table I. The bandwidth from the RF input to the IF output at MXOP pin is –1 dB at 30 MHz and then falls off rapidly (Figure 4). RFHI MIXER ≈ MXOP 7 BPF DRIVER RFLO 6 LO PREAMP VMID 8 100nF 18nF BIAS 2 COM2 +2.7V TO 5.5V 3 LO INPUT –16dBm 4 5-STAGE IF AMPLIFIER (16dB PER STAGE) IFLO 14 +2.7V TO 5.5V LMOP FINAL LIMITER FDBK AD608 15 LIMITER OUTPUT 400mVp-p ±50µ A PRUP 16 NOTES: CMOS LOGIC INPUT 1. –15dBm = ±56mV MAX FOR LINEAR OPERATION 2. 39.76mV RMS TO 396.6mV RMS FOR ±1 dB RSSI ACCURACY Figure 20. Functional Block Diagram Table I. Mixer Input Impedance vs. Frequency REV. B RSSI OUTPUT 11 20mV/dB 0.2V TO 1.8V COM3 12 RSSI VPS2 330Ω 10nF 10 100Ω ≈ 13 LOIP 1 7 FULL-WAVE RECTIFIER CELLS +15dBm 2. IFHI 10.7MHz BANDPASS 9 FILTER 330Ω MID-SUPPLY IF BIAS VPS1 COM1 110dB LIMITER GAIN 90dB RSSI IF INPUT –75dBm TO ±6mA MAX OUTPUT (±890mV INTO 165Ω) 5 The mixer’s gain can be increased or decreased by changing RL, the load impedance at pin MXOP. The limitations on the mixer’s gain are the ± 6 mA maximum output current at MXOP and the maximum allowable voltage swing at pin MXOP, which is ± 1.0 V for a 3 V supply or 5 V supply. 3dB NOMINAL INSERTION LOSS 24dB MIXER GAIN RF INPUT –95 TO –15dBm 1. GdB = 20 log10 (0.0961 RL ) Frequency (MHz) Resistance (Ohms) Capacitance (pF) 45 70 100 200 300 400 500 2800 2600 1800 1200 760 520 330 3.1 3.1 3.1 3.1 3.2 3.4 3.6 –7– AD608 5 kΩ load. In the absence of an input signal, the limiter’s output will limit on noise fluctuations, which produces an output that continues to swing 400 mV p-p but with random zero crossings. IF Filter Terminations The AD608 was designed to drive a parallel-terminated 10.7 MHz bandpass filter with a 330 Ω impedance. With a 330 Ω parallelterminated filter, pin MXOP sees a 165 Ω termination and the gain is nominally 24 dB. Other filter impedances and gains can be accommodated by either accepting an increase or decrease in gain in proportion to the filter impedance or by keeping the impedance seen by MXOP a nominal 165 Ω (by using resistive dividers or matching networks). Figure 21 shows a simple resistive voltage divider for matching an assortment of filter impedances, and Table II lists component values. Offset Feedback Loop Because the logarithmic amplifier is dc coupled and has more than 110 dB of gain from the input to the limiter output, a dc offset at its input of even a few µV would cause the output to saturate. Thus, the AD608 uses a low frequency feedback loop to null out the input offset. Referring to Figure 21, the loop consists of a current source driven by the limiter, which sends 50 µA current pulses to pin FDBK. The pulses are low pass filtered by a π-network consisting of C1, R4, and C5. The smoothed dc voltage that results is subtracted from the input to the IF amplifier at pin IFLO. Because this is a high gain amplifier with a feedback loop, care should be taken in layout and component values to prevent oscillation. Recommended values for the common IFs of 450 kHz, 455 kHz, 6.5 MHz, and 10.7 MHz are listed in Table II. The Logarithmic IF Amplifier The logarithmic IF amplifier consists of five amplifier stages of 16 dB gain each, plus a final limiter. The IF bandwidth is 30 MHz (–1 dB) and the limiting gain is 110 dB. The phase skew is ± 3° from –75 dBm to +5 dBm (approximately 111 µV p-p to 1.1 V p-p). The limiter output impedance is 200 Ω and the limiter’s output drive is ± 200 mV (400 mV p-p) into a 110dB LIMITER GAIN 90dB RSSI 12dB NOMINAL INSERTION LOSS (ASSUMES 6dB IN FILTER) 24dB MIXER GAIN 7 FULL-WAVE RECTIFIER CELLS BANDPASS FILTER RFHI 5 MIXER ≈ RFLO 6 LO PREAMP MXOP BPF DRIVER VMID IFHI R2 7 COM2 1 2 3 4 +5V 14 VPS2 R3 8 IFLO R4 15 LMOP FINAL LIMITER 10 100nF 13 LOHI VPS1 COM1 12 COM3 5-STAGE IF AMPLIFIER (16dB PER STAGE) C5 C1 BIAS 11 RSSI 9 R1 MID-SUPPLY IF BIAS ≈ 2MHz LPF FDBK ±50µA AD608 PRUP 16 47kΩ C2 100pF C1 1µF LO INPUT –16dBm CMOS LOGIC INPUT Figure 21. Applications Diagram for Common IFs and Filter Impedances Table II. AD608 Filter Termination and Offset-Null Feedback Loop Resistor and Capacitor Values for Common IFs IF Filter Impedance Filter Termination Resistor Values1 for 24 dB of Mixer Gain 450 kHz2 455 kHz 6.5 MHz 10.7 MHz 1500 Ω 1500 Ω 1000 Ω 330 Ω R1 174 Ω 174 Ω 178 Ω 330 Ω R2 1330 Ω 1330 Ω 825 Ω 0Ω R3 1500 Ω 1500 Ω 1000 Ω 330 Ω Offset Null Feedback Loop Values R4 1000 Ω 1000 Ω 100 Ω 100 Ω C1 200 nF 200 nF 18 nF 18 nF C5 100 nF 100 nF 10 nF 10 nF NOTES 1 Resistor values were calculated so that R1 + R2 = Z FILTER and R1i(R2+ZFILTER) = 165 Ω. 2 Operation at IFs of 450 kHz and 455 kHz requires an external low pass filter with at least one pole at a cutoff frequency of 90 kHz (a decade below the ripple at 900 kHz). –8– REV. B AD608 RSSI Output Power Consumption The logarithmic amplifier uses a successive detection architecture. Each of the five stages has a full-wave detector; two additional high level detectors are driven through attenuators at the input to the limiting amplifiers, for a total of seven detector stages. Because each detector is a full-wave rectifier, the ripple component in the resulting dc is at twice the IF. The AD608’s low-pass filter has a 2 MHz cutoff frequency, which is one decade below the 21.4 MHz ripple that results from a 10.7 MHz IF. The total power-supply current of the AD608 is a nominal 7.3 mA. The power is signal-dependent, partly as the RSSI output increases (the current is increased by 200 µA at an RSSI output of +1.8 V) but mostly due to the IF BPF consumption when being driven to ± 891 mV assuming a 4 dB loss in this filter and a peak input of +5 dBm to the log-IF amp, and temperature dependent, as the biasing system used in the AD608 is proportional to absolute temperature (PTAT). For operation at lower IFs such as 450 kHz or 455 kHz, the AD608 requires an external low-pass filter with a single pole located at 90 kHz, a decade below the 900 kHz ripple frequency for these IFs. The RSSI range is from the noise level at approximately –80 dBm to overload at +15 dBm and is specified for ± 1 dB accuracy from –75 dBm to +5 dBm. The +15 dBm maximum IF input is provided to accommodate bandpass filters of lower insertion loss than the nominal 4 dB for 10.7 MHz ceramic filters. The most common causes of problems with the AD608 are incorrect component values for the offset feedback loop, poor board layout, and pickup of RFI, which all cause the AD608 to “lose” the low end (typically below –65 dBm) of its RSSI output and cause the limiter to swing randomly. Both poor board layout and incorrect component values in the offset feedback loop can cause low level oscillations. Pickup of RFI can be caused by improper layout and shielding of the circuit. Digitizing the RSSI In typical cellular radio applications, the RSSI output of the AD608 will be digitized by an A/D converter. The AD608’s RSSI output is proportional to the power-supply voltage, which not only allows the A/D converter to use the supply as a reference but also causes the RSSI output and the A/D converter’s output to track over power supply variations, reducing system errors and component costs. REV. B –9– Troubleshooting AD608 Figure 23 shows the AD608 configured for narrowband FM operation at a 450 kHz or 455 kHz with an external discriminator. The IF filter has 1500 Ω input and output impedances— the input is matched via a resistive divider and the output is terminated in 1500 Ω. The discriminator requires 1 V p-p drive from a 1 kΩ source impedance, here provided by a gain-of-2.5 Class A amplifier. Applications Figure 22 shows the AD608 configured for operation in a digital system at a 10.7 MHz IF. The filter’s input and output impedance are parallel terminated using 330 Ω resistors and the conversion gain is 24 dB. The RF port is terminated in 50 Ω; in a typical application the input would be matched to a SAW filter using the impedance data shown previously in Table I. VPOS C1 1µF SUPPLY 2.7V TO 5.5V C2 100pF LO INPUT –16dBm R5 51.1Ω RF INPUT –95dBm TO –15dBm C3 100pF R6 51.1Ω C4 100pF 1 VPS1 PRUP 16 2 COM1 LMOP 15 3 LOHI VPS2 14 4 COM2 FDBK 13 5 RFHI COM3 12 6 RFLO RSSI 11 7 MXOP IFLO 10 8 VMID IFHI R4 47kΩ LIMO C7 18nF POWER-UP 3V CMOS LIMITER OUTPUT VPOS –1V ±200mV R3 100Ω RSSI OUTPUT +0.2V TO +1.8V (20mV/dB) 9 C6 10nF AD608 10.7MHz BPF Z = 330Ω BIAS POINT AT VPOS/2 R1 330Ω OFFSET-CONTROL LOOP FILTER R2 330Ω C5 0.1µF BPF REVERSE TERMINATION BPF TERMINATION IF BIAS POINT DECOUPLING Figure 22. Application at 10.7 MHz. The Bandpass Filter Can Be a Toko Type SK107 or Murata Type SFE10.7 JUMPER PRUP +5V GND C1 0.1µF LOHI R1 51.1Ω C2 1nF RFHI R2 51.1Ω C3 1nF 1 VPS1 PRUP 16 2 COM1 LMOP 15 3 LOHI VPS2 14 4 COM2 FDBK 13 5 RFHI COM3 12 6 RFLO C4 1nF R7 1130Ω R3 374Ω R16 47kΩ C5 0.1µF C8 0.1µF R6 1kΩ C9 0.2µF RSSI 11 7 MXOP IFLO 10 8 VMID IFHI 9 R14 8.66k R15 24.9k C11 Q1 0.1µF R10 3.3kΩ F2 AUDIO R12 1k CR1 R8 1k CR2 R9 1k R5 200Ω C6 0.1µF AD608 F1 R13 402 C10 0.01µF R11 3.3k RSSI F1: TOKO HCFM2–455B F2: MURATA CFY455S CR1, CR2: 1N60 Q1: 2N3906 R4 1.5kΩ C7 0.1µF Figure 23. Narrowband FM Application at 450 kHz or 455 kHz –10– REV. B AD608 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead SOIC (R-16A) 16 9 0.1574 (4.00) 0.1497 (3.80) PIN 1 0.2440 (6.20) 0.2284 (5.80) 8 1 0.3937 (10.00) 0.0196 (0.50) 0.3859 (9.80) 0.0099 (0.25) x 45 ° 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) REV. B 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) –11– 0.0099 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) PRINTED IN U.S.A. C1990b–2–7/96 AD608 –12– REV. B