Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem AD608 The RF and local oscillator (LO) bandwidths both exceed 500 MHz. In a typical IF application, the AD608 can accept the output of a 240 MHz surface acoustic wave (SAW) filter and downconvert it to a nominal 10.7 MHz IF with a conversion gain of 24 dB (ZIF = 165 Ω). The AD608 logarithmic/limiting amplifier section handles any IF from low frequency (LF) up to 30 MHz. FEATURES Mixer −15 dBm, 1 dB compression point −5 dBm IP3 24 dB conversion gain >500 MHz input bandwidth Logarithmic/limiting amplifier 80 dB RSSI range ±3° phase stability over 80 dB range Low power 21 mW at 3 V power consumption CMOS-compatible power-down to 300 μW typical 200 ns enable/disable time The mixer is a doubly balanced gilbert-cell mixer and operates linearly for RF inputs spanning −95 dBm to −15 dBm. It has a nominal −5 dBm third-order intercept. An on-board LO preamplifier requires only −16 dBm of LO drive. The current output of the mixer drives a reverse-terminated, industry-standard 10.7 MHz, 330 Ω filter. The nominal logarithmic scaling is such that the output is +0.2 V for a sinusoidal input to the IF amplifier of −75 dBm and +1.8 V at an input of +5 dBm; over this range, the logarithmic conformance is typically ±1 dB. The logarithmic slope is proportional to the supply voltage. A feedback loop automatically nulls the input offset of the first stage down to the submicrovolt level. APPLICATIONS PHS, GSM, TDMA, FM, or PM receivers Battery-powered instrumentation Base station RSSI measurements The AD608 limiter output provides a hard-limited signal output at 400 mV p-p. The voltage gain of the limiting amplifier to this output is more than 100 dB. Transition times are 11 ns and the phase is stable to within ±3° at 10.7 MHz for signals from −75 dBm to +5 dBm. GENERAL DESCRIPTION The AD608 provides a low power, low distortion, low noise mixer as well as a complete, monolithic logarithmic/limiting amplifier that uses a successive-detection technique. In addition, the AD608 provides both a high speed received signal strength indicator (RSSI) output with 80 dB dynamic range and a hard-limited output. The RSSI output is from a two-pole postdemodulation low-pass filter and provides a loadable output voltage of 0.2 V to 1.8 V. The AD608 operates from a single 2.7 V to 5.5 V supply at a typical power level of 21 mW at 3 V. The AD608 is enabled by a CMOS logic-level voltage input, with a response time of 200 ns. When disabled, the standby power is reduced to 300 μW within 400 ns. The AD608 is specified for the industrial temperature range of −25°C to +85°C for 2.7 V to 5.5 V supplies and −40°C to +85°C for 3.0 V to 5.5 V supplies. This device comes in a 16-lead plastic SOIC. FUNCTIONAL BLOCK DIAGRAM 3dB NOMINAL INSERTION LOSS 24dB MIXER GAIN 5 MIXER RFLO MXOP 7 BPF DRIVER 6 LO PREAMP 10.7MHz BAND-PASS FILTER 330Ω 10nF 8 MIDSUPPLY IF BIAS 100nF + 2 3 4 15 LIMITER OUTPUT 400mV p-p 13 FDBK AD608 ±50µA PRUP LOHI COM2 LO INPUT –16dBm IFLO 14 +2.7V TO 5.5V LMOP 16 CMOS LOGIC INPUT 07886-001 1 2.7V TO 5.5V 18nF 0.2V TO 1.8V FINAL LIMITER 10 100Ω + BIAS VPS1 COM1 5-STAGE IF AMPLIFIER (16dB PER STAGE) RSSI OUTPUT 11 20mV/dB COM3 12 VPS2 9 330Ω VMID 2MHz LPF IFHI + RFHI RSSI 7 FULL-WAVE RECTIFIER CELLS IF INPUT –75dBm TO +15dBm2 ±6mA MAX OUTPUT (±890mV INTO 165Ω) RF INPUT –95dBm TO –15dBm 1 110dB LIMITER GAIN 90dB RSSI 1–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION. 239.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY. Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1996–2009 Analog Devices, Inc. All rights reserved. AD608 TABLE OF CONTENTS Features .............................................................................................. 1 Mixer ...............................................................................................9 Applications ....................................................................................... 1 Mixer Gain .....................................................................................9 General Description ......................................................................... 1 IF Filter Terminations ................................................................ 10 Functional Block Diagram .............................................................. 1 The Logarithmic IF Amplifier .................................................. 10 Revision History ............................................................................... 2 Offset Feedback Loop ................................................................ 10 Specifications..................................................................................... 3 RSSI Output ................................................................................ 11 Absolute Maximum Ratings............................................................ 4 Digitizing the RSSI ..................................................................... 11 Thermal Resistance ...................................................................... 4 Power Consumption .................................................................. 11 ESD Caution .................................................................................. 4 Troubleshooting.......................................................................... 11 Pin Configuration and Function Descriptions ............................. 5 Applications Information .............................................................. 12 Typical Performance Characteristics ............................................. 6 Outline Dimensions ....................................................................... 13 Test Circuits ....................................................................................... 8 Ordering Guide .......................................................................... 13 Theory of Operation ........................................................................ 9 REVISION HISTORY 2/09—Rev. B to Rev. C Updated Format .................................................................. Universal Reorganized Layout ............................................................ Universal Change to General Description Section ........................................ 1 Changes to DC Level Parameter, Operating Range Parameter, and TMIN to TMAX Parameter, Table 1 .......................................... 3 Added Typical Performance Characteristics Heading ................ 6 Added Test Circuits Heading .......................................................... 8 Changes to Figure 17 and Figure 19 ............................................... 8 Change to Figure 22 ......................................................................... 9 Changes to Table 5 ............................................................................ 9 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 Rev. C | Page 2 of 16 AD608 SPECIFICATIONS TA = 25°C, supply = 3 V, dBm is referred to 50 Ω, unless otherwise noted. Table 1. Parameter MIXER PERFORMANCE RF and LO Frequency Range LO Power Conversion Gain Noise Figure 1 dB Compression Point Third-Order Intercept Input Resistance Input Capacitance LIMITER PERFORMANCE Gain Limiting Threshold Input Resistance Input Capacitance Phase Variation DC Level Output Level Rise and Fall Times Output Impedance RSSI PERFORMANCE Nominal Slope Nominal Intercept Minimum RSSI Voltage Maximum RSSI Voltage RSSI Voltage Intercept Logarithmic Linearity Error RSSI Response Time Output Impedance POWER-DOWN INTERFACE Logic Threshold Input Current Power-Up Response Time Power-Down Response Time Power-Down Current POWER SUPPLY Operating Range Powered Up Current OPERATING TEMPERATURE TMIN to TMAX 1 Conditions 1 Min Input terminated in 50 Ω Driving doubly terminated 330 Ω IF filter, ZIF = 165 Ω Matched input, fRF = 100 MHz Matched input, fRF = 240 MHz Input terminated in 50 Ω fRF = 240 MHz and 240.02 MHz, fLO = 229.3 MHz fRF = 100 MHz (see Table 5) fRF = 100 MHz (see Table 5) 19 Full temperature and supply range 3° rms phase jitter at 10.7 MHz 280 kHz IF bandwidth −75 dBm to +5 dBm IF input signal at 10.7 MHz Center of output swing (VPOS – 1 V) Limiter output driving 5 kΩ load Driving a 5 pF load At 10.7 MHz At VPOS = 3 V; proportional to VPOS −75 dBm input signal +5 dBm input signal 0 dBm input signal −75 dBm to +5 dBm input signal at IFHI 90% RF to 50% RSSI At midscale 17.27 Typ 500 −16 24 11 16 −15 −5 1.9 3 −25°C to +85°C −40°C to +85°C VPOS = 3 V 2.7 3.0 VPOS = 2.7 V to 5.5 V VPOS = 3.0 V to 5.5 V −25 −40 28 Rev. C | Page 3 of 16 MHz dBm dB dB dB dBm dBm kΩ pF dB dBm 10 3 ±3 2 400 11 200 kΩ pF Degrees V mV p-p ns Ω 20 −85 0.2 1.8 23.27 ±1 200 250 mV/dB dBm V V V dB ns Ω 1.5 75 200 400 100 V mA ns ns μA 1.82 5.5 5.5 V V mA +85 +85 °C °C 7.3 VPOS is used to refer collectively to the VPS1 and VPS2 pins. Unit 110 −75 1.57 System active on logic high For logic high Active limiter output To 200 μA supply current Max AD608 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Supply Voltages VPS1, VPS2 Internal Power Dissipation Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating +6 V 600 mW −40°C to +85°C −65°C to +150°C 300°C Table 3. Package Type 16-Lead SOIC Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. C | Page 4 of 16 θJA 110 Unit °C/W AD608 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VPS1 1 16 PRUP COM1 2 15 LMOP LOHI 3 14 VPS2 COM2 4 AD608 RFLO 6 11 RSSI MXOP 7 10 IFLO VMID 8 9 IFHI 07886-002 13 FDBK TOP VIEW RFHI 5 (Not to Scale) 12 COM3 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Mnemonic VPS1 1 COM1 LOHI COM2 RFHI RFLO MXOP VMID IFHI IFLO RSSI COM3 FDBK VPS21 LMOP PRUP Description Positive Supply Input Common Local Oscillator Input Connection Common RF Input, Noninverting RF Input, Inverting Mixer Output Midpoint Supply Bias Output IF Input, Noninverting IF Input, Inverting Received Signal Strength Indicator Output Output Common Offset-Null Feedback Loop Output Limiter Positive Supply Input Limiter Output Power-Up VPOS is used to refer collectively to the VPS1 and VPS2 pins in this data sheet. Rev. C | Page 5 of 16 AD608 3.0 24.5 2.5 24.0 2.0 RSSI OUTPUT (V) 25.0 23.5 23.0 1.0 50 100 150 200 250 300 350 400 450 500 0 –80 RF FREQUENCY (MHz) 3 –2 2 RSSI ERROR (dB) –1 –3 –4 –5 50 60 70 –10 0 10 80 IF FREQUENCY (MHz) 10 3V 5V –3 40 –20 –1 –7 30 –30 0 –2 20 –40 1 –6 –4 –80 07886-006 MIXER RESPONSE (dB) 4 10 –50 Figure 6. IF RSSI Output vs. Input Power and Temperature, 3 V Supply (See Figure 15) 0 0 –60 INPUT POWER (dBm) Figure 3. Mixer Conversion Gain vs. RF Frequency –8 –70 07886-008 0 07886-010 0.5 22.5 22.0 +85°C +25°C –25°C 1.5 07886-005 MIXER CONVERSION GAIN (dB) TYPICAL PERFORMANCE CHARACTERISTICS –70 –60 –50 –40 –30 –20 –10 0 INPUT POWER (dBm) Figure 7. RSSI Error vs. Input Power (See Figure 15) Figure 4. Mixer IF Port Bandwidth 3.0 800mV/DIV RSSI 2.0 100ns/DIV 5V 1.5 1V/DIV 1.0 3V 0.5 –70 –60 –50 –40 –30 –20 INPUT POWER AT IFHI (dBm) –10 0 10 07886-007 100ns/DIV 0 –80 Figure 5. IF RSSI Output vs. Input Power at IFHI and Supply Voltage, Ambient Temperature (See Figure 15) Figure 8. RSSI Power-Up Response (See Figure 19) Rev. C | Page 6 of 16 07886-011 PRUP RSSI OUTPUT (V) 2.5 AD608 5 200mV/DIV 4 RSSI LIMITER PHASE (Degrees) IFHI 3 2 1 0 –1 –2 50ns/DIV –4 –5 –80 –70 –60 –50 –40 –30 –20 –10 0 10 INPUT POWER AT IFHI (dBm) Figure 9. RSSI Pulse Response/RSSI Rise Time (See Figure 16) 07886-019 800mV/DIV 07886-013 –3 Figure 12. Limiter Phase Performance vs. Input Power at IFHI (See Figure 21) 10 60mV/DIV 8 7 6 5 4 3 2 1 0 –80 –70 –60 –50 –40 –30 –20 –10 0 10 INPUT POWER AT IFHI (dBm) Figure 10. Limiter Rise and Fall Times (See Figure 20) 100ns/DIV LMOP 220mV/DIV Figure 13. Limiter RMS Jitter Performance vs. Input Power at IFHI (See Figure 21) 100ns/DIV 07886-017 PRUP 1V/DIV Figure 11. Limiter Power-Up Response Time (See Figure 17) Rev. C | Page 7 of 16 07886-021 20ns/DIV 07886-015 LMOP LIMITER RMS JITTER (Degrees) 9 AD608 TEST CIRCUITS PRUP INPUT U1A TRIGGER U1B 4.7kΩ 0.1µF VPOS 47kΩ 1nF 1nF 1nF 51.1Ω 332Ω LMOP 15 3 LOHI VPS2 14 4 COM2 FDBK 13 5 RFHI COM3 12 6 RFLO RSSI 11 7 MXOP IFLO 10 8 VMID IFHI 9 51.1Ω LMOP OUTPUT 0.1µF 1nF RF INPUT 51.1Ω 1nF 18nF 100Ω RSSI OUTPUT 10nF VPS2 14 4 COM2 FDBK 13 5 RFHI COM3 12 6 RFLO RSSI 11 7 MXOP IFLO 10 8 VMID IFHI 9 0.1µF IF OUTPUT IF INPUT 54.9Ω 07886-003 U1 – 74HC00 NC = NO CONNECT Figure 18. Mixer Test Board Schematic Figure 14. IF Test Board Schematic IF TEST BOARD RSSI IFHI 10.7MHz 0dBm DMM AGILENT HP3366A IF TEST BOARD COUPLER RSSI MCL ZDC-20-1 FET PROBE AGILENT HP3366A Figure 19. Test Circuit for RSSI Power-Up Response (Figure 8) FLUKE 6082A SYNTHESIZER CH 1 10.7MHz 0dBm IF TEST BOARD IFHI 10.7MHz 0dBm LMOP PRUP TEKRONIX P6201 FET PROBE AGILENT HP54120A FET PROBE DIGITAL OSCILLOSCOPE VPOS 3V DCPS Figure 20. Test Circuit for Limiter Rise and Fall Times (Figure 10) AGILENT HP54120A DIGITAL OSCILLOSCOPE FLUKE 6082A SYNTHESIZER MCL ZDC-20-1 IF TEST BOARD COUPLER 10.7MHz CH 1 CH 2 AGILENT HP8494A HP8495A IFHI RSSI DCPS AGILENT HP3366A VPOS 3V 3V TEKTRONIX P6201 FET PROBE AGILENT HP8447A BPF AGILENT HP3366A Figure 17. Test Circuit for Limiter Power-Up Response Time (Figure 11) CH 1 280kHz BW 10.7MHz CF TOKO SK107MK1-A0-10 07886-018 DCPS LMOP TEKRONIX P6201 AGILENT HP3366A Figure 16. Test Circuit for RSSI Pulse Response/RSSI Rise Time (Figure 9) FLUKE 6082A SYNTHESIZER IF TEST BOARD IFHI CH 2 AGILENT HP54120A DIGITAL OSCILLOSCOPE 3V 3V AGILENT HP3366A VPOS DCPS CH 2 PRUP 07886-014 10.7MHz 0dBm IFHI TEKRONIX P6201 CH 1 VPOS Figure 15. Test Circuit for IF RSSI Output vs. Input Power at IFHI and Supply Voltage, Ambient Temperature (Figure 5); IF RSSI Output vs. Input Power and Temperature, 3 V Supply (Figure 6); and RSSI Error vs. Input Power (Figure 7) FLUKE 6082A SYNTHESIZER FET PROBE RSSI DCPS 3V DCPS AGILENT HP54120A DIGITAL OSCILLOSCOPE TEKRONIX P6201 IF TEST BOARD AGILENT HP34401A VPOS DC POWER SUPPLY (DCPS) FLUKE 6082A SYNTHESIZER DIGITAL MULTIMETER (DMM) 07886-009 IFHI 10.7MHz 10nF 301Ω 54.9Ω FLUKE 6082A SYNTHESIZER 100Ω NC 07886-004 332Ω 18nF 18nF 332Ω 0.1µF 301Ω 0.1µF NC AD608 332Ω 0.1µF AD608 LMOP 15 3 LOHI 07886-012 51.1Ω 2 COM1 2 COM1 47kΩ 07886-016 0.1µF PRUP 16 PRUP 16 TRIG AGILENT HP54120A DIGITAL OSCILLOSCOPE 07886-020 0.1µF VPOS 1 VPS1 LO INPUT 1 VPS1 Figure 21. Test Circuit for Limiter Phase Performance vs. Input Power at IFHI (Figure 12) and Limiter RMS Jitter Performance vs. Input Power at IFHI (Figure 13) Rev. C | Page 8 of 16 AD608 THEORY OF OPERATION The AD608 consists of a mixer followed by a logarithmic IF strip with RSSI and hard-limited outputs (see Figure 22). MIXER GAIN The conversion gain of the mixer is the product of its transconductance and the impedance seen at Pin MXOP. For a 330 Ω parallel-terminated filter at 10.7 MHz, the load impedance is 165 Ω, the gain is 24 dB, and the output is 15.85 × 56.2 mV (or ±891 mV) centered on the midpoint of the supply voltage. For other load impedances, the expression for the gain in decibels is MIXER The mixer is a doubly balanced, modified gilbert-cell mixer. Its maximum input level for linear operation is either ±56.2 mV, regardless of the impedance across the mixer inputs, or −15 dBm for a 50 Ω input termination. The input impedance of the mixer can be modeled as a simple parallel RC network; the resistance and capacitance values vs. frequency are listed in Table 5. The bandwidth from the RF input to the IF output at the MXOP pin is −1 dB at 30 MHz and then rapidly decreases as frequency increases (see Figure 4). 5 MIXER MXOP 7 BPF DRIVER 6 10.7MHz BAND-PASS FILTER 330Ω 100nF MIDSUPPLY IF BIAS + + LOHI COM2 1 2.7V TO 5.5V 2 3 LO INPUT –16dBm 4 15 FINAL LIMITER IFLO LIMITER OUTPUT 400mV p-p 13 FDBK AD608 ±50µA PRUP 16 CMOS LOGIC INPUT 1–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION. 239.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY. Figure 22. Functional Block Diagram Table 5. Mixer Input Impedance vs. Frequency Frequency (MHz) 45 70 100 200 300 400 500 14 2.7V TO 5.5V 07886-022 VPS1 COM1 0.2V TO 1.8V COM3 12 VPS2 10 RSSI OUTPUT 11 20mV/dB LMOP 5-STAGE IF AMPLIFIER (16dB PER STAGE) 100Ω 18nF BIAS 2MHz LPF IFHI 10nF 8 RSSI 7 FULL-WAVE RECTIFIER CELLS 330Ω VMID LO PREAMP 110dB LIMITER GAIN 90dB RSSI 9 + RFLO The gain of the mixer can be increased or decreased by changing RL. The limitations on the gain are the ±6 mA maximum output current at MXOP and the maximum allowable voltage swing at Pin MXOP, which is ±1.0 V for a 3 V supply or 5 V supply. IF INPUT –75dBm TO +15dBm 2 ±6mA MAX OUTPUT (±890mV INTO 165Ω) RF INPUT –95dBm TO –15dBm 1 where: GdB is the gain in decibels. RL is the load impedance at Pin MXOP. 3dB NOMINAL INSERTION LOSS 24dB MIXER GAIN RFHI GdB = 20 log10(0.0961 RL) Resistance (Ω) 2800 2600 1900 1200 760 520 330 Capacitance (pF) 3.1 3.1 3.0 3.1 3.2 3.4 3.6 Rev. C | Page 9 of 16 AD608 limiter output drive is ± 200 mV (400 mV p-p) into a 5 kΩ load. In the absence of an input signal, the limiter output limits noise fluctuations, producing an output that continues to swing 400 mV p-p, but with random zero crossings. IF FILTER TERMINATIONS The AD608 was designed to drive a parallel-terminated 10.7 MHz band-pass filter (BPF) with a 330 Ω impedance. With a 330 Ω parallel-terminated filter, Pin MXOP sees a 165 Ω termination, and the gain is nominally 24 dB. Other filter impedances and gains can be accommodated by either accepting an increase or decrease in gain in proportion to the filter impedance or by keeping the impedance seen by MXOP at a nominal 165 Ω (by using resistive dividers or matching networks). Figure 23 shows a simple resistive voltage divider for matching an assortment of filter impedances, and Table 6 lists component values. OFFSET FEEDBACK LOOP Because the logarithmic amplifier is dc-coupled and has more than 110 dB of gain from the input to the limiter output, a dc offset at its input of even a few microvolts causes the output to saturate. Therefore, the AD608 uses a low frequency feedback loop to null the input offset. Referring to Figure 23, the loop consists of a current source driven by the limiter, which sends 50 μA current pulses to Pin FDBK. The pulses are low-pass filtered by a π-network consisting of C1, R4, and C5. The smoothed dc voltage that results is subtracted from the input to the IF amplifier at Pin IFLO. Because this is a high gain amplifier with a feedback loop, care should be taken in layout and component values to prevent oscillation. Recommended values for the common IFs of 450 kHz, 455 kHz, 6.5 MHz, and 10.7 MHz are listed in Table 6. THE LOGARITHMIC IF AMPLIFIER The logarithmic IF amplifier consists of five amplifier stages of 16 dB gain each, plus a final limiter. The IF bandwidth is 30 MHz (−1 dB), and the limiting gain is 110 dB. The phase skew is ±3° from −75 dBm to +5 dBm (approximately 111 μV p-p to 1.1 V p-p). The limiter output impedance is 200 Ω, and the 12dB NOMINAL INSERTION LOSS (ASSUMES 6dB IN FILTER) 24dB MIXER GAIN 110dB LIMITER GAIN 90dB RSSI 7 FULL-WAVE RECTIFIER CELLS BAND-PASS FILTER 5 R2 MIXER RFLO MXOP 7 BPF DRIVER 6 C5 8 100nF + + 5V C1 1µF 2 LOHI 3 COM2 4 C2 100pF LO INPUT –16dBm IFLO 13 FDBK AD608 ±50µA PRUP 16 47kΩ 07886-023 1 15 LMOP FINAL LIMITER 10 R4 C1 BIAS VPS1 COM1 14 VPS2 5-STAGE IF AMPLIFIER (16dB PER STAGE) R3 R1 MIDSUPPLY IF BIAS 12 COM3 9 VMID LO PREAMP 11 RSSI 2MHz LPF IFHI + RFHI CMOS LOGIC INPUT Figure 23. Applications Diagram for Common IFs and Filter Impedances Table 6. AD608 Filter Termination and Offset-Null Feedback Loop Resistor and Capacitor Values for Common IFs IF 450 kHz 2 455 kHz 6.5 MHz 10.7 MHz 1 2 Filter Impedance 1500 Ω 1500 Ω 1000 Ω 330 Ω Filter Termination Resistor Values 1 for 24 dB of Mixer Gain R1 R2 R3 174 Ω 1330 Ω 1500 Ω 174 Ω 1330 Ω 1500 Ω 178 Ω 825 Ω 1000 Ω 330 Ω 0Ω 330 Ω R4 1000 Ω 1000 Ω 100 Ω 100 Ω Offset-Null Feedback Loop Values C1 C5 200 nF 100 nF 200 nF 100 nF 18 nF 10 nF 18 nF 10 nF Resistor values were calculated so that R1 + R2 = ZFILTER and R1||(R2 + ZFILTER) = 165 Ω. Operation at IFs of 450 kHz and 455 kHz requires use of an external low-pass filter with at least one pole at a cutoff frequency of 90 kHz (a decade below the ripple at 900 kHz). Rev. C | Page 10 of 16 AD608 RSSI OUTPUT The logarithmic amplifier uses a successive-detection architecture. Each of the five stages has a full-wave detector; two additional high level detectors are driven by attenuators at the input to the limiting amplifiers, for a total of seven detector stages. Because each detector is a full-wave rectifier, the ripple component in the resulting dc is at twice the IF. The AD608 low-pass filter has a 2 MHz cutoff frequency, which is one decade below the 21.4 MHz ripple that results from a 10.7 MHz IF. For operation at lower IFs, such as 450 kHz or 455 kHz, the AD608 requires an external low-pass filter with a single pole located at 90 kHz, a decade below the 900 kHz ripple frequency for these IFs. The RSSI range is from the noise level at approximately −80 dBm to overload at +15 dBm and is specified for ±1 dB accuracy from −75 dBm to +5 dBm. The +15 dBm maximum IF input is provided to accommodate band-pass filters of lower insertion loss than the nominal 4 dB for 10.7 MHz ceramic filters. DIGITIZING THE RSSI In typical cellular radio applications, the RSSI output of the AD608 is digitized by an analog-to-digital converter (ADC). The RSSI output of the AD608 is proportional to the power supply voltage, which not only allows the ADC to use the supply as a reference, but also causes the RSSI output and the ADC output to track over power supply variations, reducing system errors and component costs. POWER CONSUMPTION The total power supply current of the AD608 is a nominal 7.3 mA. The power is signal dependent, partly because the RSSI output increases (the current is increased by 200 μA at an RSSI output of +1.8 V), but mostly due to the IF consumption of the band-pass filter when driven to ±891 mV, assuming a 4 dB loss in this filter and a peak input of +5 dBm to the log-IF amp. In addition, the power is temperature dependent because the biasing system used in the AD608 is proportional to the absolute temperature (PTAT). TROUBLESHOOTING The most common causes of problems with the AD608 are incorrect component values for the offset feedback loop, poor board layout, and pickup of radio frequency interference (RFI), which all cause the AD608 to lose the low end (typically below −65 dBm) of its RSSI output and cause the limiter to swing randomly. Both poor board layout and incorrect component values in the offset feedback loop can cause low level oscillations. Pickup of RFI can be caused by improper layout and shielding of the circuit. Rev. C | Page 11 of 16 AD608 APPLICATIONS INFORMATION Figure 25 shows the AD608 configured for narrow-band FM operation at a 450 kHz or 455 kHz with an external discriminator. The IF filter has 1500 Ω input and output impedances—the input is matched via a resistive divider, and the output is terminated in 1500 Ω. The discriminator requires a 1 V p-p drive from a 1 kΩ source impedance, which in Figure 25 is provided by a Class A amplifier with a gain of 2.5. Figure 24 shows the AD608 configured for operation in a digital system at a 10.7 MHz IF. The input and output impedance of the filter are parallel terminated using 330 Ω resistors, and the conversion gain is 24 dB. The RF port is terminated in 50 Ω; in a typical application, the input is matched to a SAW filter using the impedance data provided in Table 5. VPOS SUPPLY 2.7V TO 5.5V PRUP 16 C2 100pF 2 COM1 LMOP 15 3 LOHI VPS2 14 4 COM2 FDBK 13 5 RFHI COM3 12 + 6 RFLO RSSI 11 C4 100pF 7 MXOP IFLO 10 8 VMID IFHI + 1 VPS1 + C1 1µF + R5 51.1Ω C3 100pF RF INPUT –95dBm TO –15dBm R6 51.1Ω AD608 9 R4 47kΩ POWER-UP 3V CMOS LIMO + C7 18nF R3 100Ω LIMITER OUTPUT VPOS –1V ±200mV RSSI OUTPUT +0.2V TO +1.8V (20mV/dB) + C6 10nF 10.7MHz BPF Z = 330Ω BIAS POINT AT VPOS/2 OFFSET-CONTROL LOOP FILTER R2 330Ω R1 330Ω + C5 0.1µF BPF REVERSE TERMINATION BPF TEMINATION 07886-024 LO INPUT –16dBm IF BIAS POINT DECOUPLING Figure 24. Application at 10.7 MHz (the Band-Pass Filter Can Be a Toko SK107 or Murata SFE10.7) JUMPER PRUP C1 0.1µF LOHI R1 51.1Ω C2 1nF 1 VPS1 PRUP 16 2 COM1 LMOP 15 3 LOHI VPS2 14 4 COM2 FDBK 13 5 RFHI RFHI R2 51.1Ω C3 1nF C4 1nF R7 1130Ω R3 374Ω COM3 12 6 RFLO RSSI 11 7 MXOP IFLO 10 8 VMID IFHI 9 AD608 F1 R16 47kΩ R13 402Ω R14 C5 0.1µF 8.66kΩ R10 3.3kΩ F2 Q1 C8 0.1µF R15 24.9kΩ R6 1kΩ C9 0.2µF R12 1kΩ C11 0.1µF R5 200Ω C6 0.1µF CR1 R8 1kΩ CR2 R9 1kΩ AUDIO C10 0.01µF R11 3.3kΩ RSSI F1: TOKO HCFM2–455B F2: MURATA CFY455S CR1, CR2: 1N60 Q1: 2N3906 R4 1.5kΩ C7 0.1µF Figure 25. Narrow-Band FM Application at 450 kHz or 455 kHz Rev. C | Page 12 of 16 07886-025 +5V GND AD608 OUTLINE DIMENSIONS 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 9 16 1 8 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 0.25 (0.0098) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 060606-A COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 26. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model AD608AR AD608AR-REEL AD608ARZ 1 AD608ARZ-RL1 EVAL-AD608EBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] 16-Lead Standard Small Outline Package [SOIC_N] Evaluation Board Z = RoHS Compliant Part. Rev. C | Page 13 of 16 Package Option R-16 R-16 R-16 R-16 AD608 NOTES Rev. C | Page 14 of 16 AD608 NOTES Rev. C | Page 15 of 16 AD608 NOTES ©1996–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07886-0-2/09(C) Rev. C | Page 16 of 16