www.fairchildsemi.com ML2036 Serial Input Programmable Sine Wave Generator with Digital Gain Control Features General Description • Programmable output frequency – DC to 50kHz • Low gain error and total harmonic distortion • 3-wire SPI compatible serial microprocessor interface with double buffered data latch • Fully integrated solution – no external components required • Frequency resolution of 1.5Hz (±0.75Hz) with a 12MHz clock input • Onboard 3 to 12MHz crystal oscillator • Clock outputs of 1/2 or 1/8 of the input clock frequency • Synchronous or asynchronous data loading capability • Compatible with ML2004 logarithmic gain/attenuator The ML2036 is a monolithic sine wave generator whose output is programmable from DC to 50kHz. No external components are required. The frequency of the sinewave output is derived from either an external crystal or clock input, providing a stable and accurate frequency reference. The frequency is programmed by a 16-bit serial data word. The ML2036 provides for a VOUT amplitude of either ±VREF or ±VREF/2. Also included with the ML2036 is an inhibit function which allows the sinewave output to be held at zero volts after completing the last half cycle of the sine wave in progress. Two digital clock outputs are provided to drive other devices with one half or one eighth of the input clock frequency. The ML2036 is intended for telecommunications and modem applications that need low cost and accurate generation of precise test tones, call progress tones, and signaling tones. Block Diagram (Pin configuration shown for 14-Pin PDIP Version) 9 13 GAIN VREF CLK IN 14 CRYSTAL OSCILLATOR CLK OUT 1 3 ÷2 ÷2 CLK OUT 2 4 ÷2 8-BIT DAC 7 SCK SMOOTHING FILTER 5kΩ VOUT + VCC ZERO DETECT 8 AGND 11 DGND 16-BIT DATA LATCH 12 16 5 SID 10 8 PHASE ACCUMULATOR & 512 POINT SINE LOOK-UP TABLE 16 LATI 5kΩ VSS 16-BIT SHIFT REGISTER 1 3 PDN-INH 2 REV. 1.0.2 7/26/01 ML2036 PRODUCT SPECIFICATION Pin Configuration ML2036 16-Pin Wide SOIC (S16W) ML2036 14-Pin PDIP (P14) VSS 1 PDN-INH 2 CLK OUT 1 3 14 CLK IN 13 GAIN 12 DGND CLK OUT 2 4 11 AGND SCK 5 10 VOUT NC 1 16 CLK IN VSS 2 15 GAIN PDN-INH 3 14 NC CLK OUT 1 4 13 DGND CLK OUT 2 5 12 AGND SCK 6 11 VOUT SID 6 9 VREF SID 7 10 VREF LATI 7 8 VCC LATI 8 9 VCC TOP VIEW TOP VIEW Pin Description (Pin Number in Paranthesis is for SOIC Version) PIN NAME 1 (2) VSS 2 (3) PDN-INH 3 (4) CLK OUT 1 1 CLK OUT 2 2 4 (5) 2 FUNCTION Negative supply (-5V). Three level input which controls the inhibit and power down modes. Current source pull-up to VCC. Digital clock output from the internal clock generator that can drive other devices at fCLK OUT = fCLK IN/2. Digital clock output from the internal clock generator that can drive other devices at fCLK OUT = fCLK IN/8. 5 (6) SCK Serial clock. Digital input which clocks in serial data on its rising edges. 6 (7) SID Serial input data which programs the frequency of VOUT. 7 (8) LATI Digital input which latches serial data into the internal data latch on falling edges. 8 (9) VCC Positive supply (5V). 9 (10) VREF Reference input. The voltage on this pin determines the peak-to-peak swing of VOUT. VREF can be tied to VCC. 10 (11) VOUT Analog output. 11 (12) AGND Analog ground. All analog inputs and outputs are referenced to this point. 12 (13) DGND Digital ground. All digital inputs and outputs are referenced to this point. 13 (15) GAIN Sets VOUT peak amplitude to VREF or VREF/2. Current source pull-down to DGND. 14 (16) CLK IN Clock input. The internal clock can be generated by tying a 3 to 12MHz crystal from this pin to DGND, or by applying a digital clock signal directly to the pin. REV. 1.0.2 7/26/01 PRODUCT SPECIFICATION ML2036 Absolute Maximum Ratings Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Parameter Min. VCC VSS VOUT Voltage on any other pin Input Current Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 sec) Thermal Resistance (θJA) 14-Pin PDIP 16-Pin Wide SOIC VSS - 0.3 GND - 0.3 –65 Max. 6.5 -6.5 VCC + 0.3 VCC + 0.3 ±25 150 150 260 Units V V V V mA °C °C °C 88 105 °C/W °C/W Operating Conditions Parameter Min. Max. Units Temperature Range ML2036CX ML2036IX 0 -40 70 85 °C °C VCC Range 4.5 5.5 V VSS Range -4.5 -5.5 V Electrical Characteristics Unless otherwise specified, VCC = 4.5V to 5.5V, VSS = -4.5V to -5.5V, VREF = 2.5V to VCC, CLK IN = 12.352MHz, CL = 100pF, RL = 1kΩ, TA = Operating Temperature Range (Note 1) Symbol Output HD SND Parameter Harmonic Distortion (Note 2) (2nd and 3rd Harmonic) Signal to Noise + Distortion (Note 2) VGN Gain Error (Note 2) ICN Idle Channel Noise PSRR Power Supply Rejection Ratio VOS VOUT Offset Voltage (Note 3) VP-P Peak-to-Peak Output Voltage (Note 2) RREF VOUT Swing Reference Input Resistance REV. 1.0.2 7/26/01 Conditions Min. 20Hz to 5kHz 5kHz to 50kHz 200Hz to 3.4kHz, fOUTBW = 200Hz to 4kHz 20Hz to 50kHz, fOUT BW = 20 Hz to 150kHz 20Hz < fOUT < 5kHz 5kHz < fOUT < 50kHz Power Down Mode, Cmsg Weighted Power Down Mode, 1kHz Inhibit Mode, 1kHz 200mVP-P, 0 - 10kHz VCC Sine, Measured on VSS VOUT Typ. -20 Max. Units -45 -40 -45 dB dB dB -40 dB ±0.15 ±0.3 0 dB dB dBrnc -40 -40 nV/ Hz nV/ Hz dB dB 50 500 ±(2.5+ VP-P)/100 GAIN = VCC GAIN = DGND GAIN = VCC ±VREF ±VREF/2 VSS +1.5 1 VCC -1.5 6 V V V V MΩ 3 ML2036 PRODUCT SPECIFICATION Electrical Characteristics (continued) Unless otherwise specified, VCC = 4.5V to 5.5V, VSS = -4.5V to -5.5V, VREF = 2.5V to VCC, CLK IN = 12.352MHz, CL = 100pF, RL = 1kΩ, TA = Operating Temperature Range (Note 1) Symbol Oscillator VIL CLK VIH CLK IIL CLK IIH CLK CIN CLK tCKI t1R, t2R t1F, t2F Logic VIL VIH VI1 VI2 VI3 IIL-PDN IIH-GAIN IIL IIH CIN VOL VOH tSCK tDS tDH tLPW tLH tLS Supply ICC ISS Parameter CLK IN Input Low Voltage CLK IN Input High Voltage CLK IN Input Low Current CLK IN Input High Current CLK IN Input Capacitance CLK IN On/Off Period CLK OUT 1/CLK IN Frequency Ratio CLK OUT 2/CLK IN Frequency Ratio CLK OUT 1, CLK OUT 2 Rise Time CLK OUT 1, CLK OUT 2 Fall Time Input Low Voltage (LATI, SCK, SID, GAIN) Input High Voltage (LATI, SCK, SID, GAIN) Input Low Voltage - PDN-INH Inhibit Stage Voltage - PDN-INH Input High Voltage - PDN-INH PDN-INH Input Low Current GAIN Input High Current Input Low Current (LATI, SCK, SID, GAIN) Input High Current (LATI, SCK, SID, GAIN) Input Capacitance Output Low Voltage Output High Voltage Serial Clock On/Off Period SID Data Setup Time SID Data Hold Time LATI Pulse Width LATI Hold Time LATI Setup Time VCC Current VSS Current Conditions Min. Typ. Max. Units 1.5 V V µA µA pF ns 3.5 -250 250 12 tR = tF = 10ns, 2.5V Midpoint See Figure 2 30 0.49 0.51 See Figure 2 0.122 0.128 CL = 40pF, 10% to 90% CL = 100pF, 0.8V to 2.0V Transition CL = 40pF, 90% to 10% CL = 100pF, 2.0V to 0.8V Transition 20 20 ns ns 20 20 ns ns 0.8 V 2.0 V -0.5 PDN-INH = 0V GAIN = VCC VIN = 0V 2.0 -70 5 -1 0.8 VSS + 0.5 -20 20 VIN = VCC -5 70 1 5 IOL = -2mA IOH = 2mA No Load, VCC = VREF = 5.5V No Load, Power Down Mode No Load, VCC = VREF = 5.5V, VSS = -5.5V No Load, Power Down Mode 0.4 4.0 100 50 50 50 50 50 V V V µA µA µA µA pF V V ns ns ns ns ns ns 5.5 2 -3.5 mA mA mA -100 µA Notes: 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. 2. Maximum peak-to-peak voltage for the output sine wave is: VOUT(P-P) ≤ (125kV x Hz)/fOUT. For example, at 50kHz, the maximum output voltage swing is 2.5VP-P. 3. Offset voltage is a function of the peak-to-peak output voltage. For example, if VOUT(P-P) = 2.5V, VOS= ±50mV max. 4 REV. 1.0.2 7/26/01 PRODUCT SPECIFICATION ML2036 tCKI tCKI tSCK tSCK CLK IN SCK tDS tDH SID tLH tLS LATI tLPW Figure 1. Serial Interface Timing. fCLKIN CLKIN t1R fCLK1 t1F CLKOUT1 fCLK2 CLKOUT2 t2R t2F fCLK PARAMETERS REFERRED TO 1.4V MIDPOINT Figure 2. Digital Clock Output Timing 100 75 INPUT CURRENT (µA) 50 25 0 -25 -50 -75 -100 0 1 2 3 4 5 INPUT VOLTAGE (V) Figure 3. CLK IN Input Current vs. Input Voltage. REV. 1.0.2 7/26/01 5 ML2036 PRODUCT SPECIFICATION 16-BIT SHIFT REGISTER SID (16 BITS) • • • 16-BIT DATA LATCH LATI (16 BITS) • • • ••• – – A16 A0 21-BIT B0–B20 A20 A15 ADDER BINARY PHASE ACCUMULATOR SUM (21 BITS) • • • fREF 21-BIT LATCH Q0 ••• Q20 ••• LEAST SIGNIFICANT (12 BITS) PHASE SAMPLES (7 BITS) CLKIN CRYSTAL OSCILLATOR SIGN BIT INPUT TO QUADRANT COMPLEMENTOR QUADRANT BIT T= QUADRANT COMPLEMENTER ÷4 • • • (7 BITS) SIGN BIT READ-ONLY MEMORY (128 X 7) SIGN COMPLEMENTOR fREF PICTORIAL PRESENTATION OF DIGITAL DATA INPUT TO OUTPUT LATCH SIGN BIT OUTPUT LATCH • • • (7BITS) INPUT TO ROM INPUT TO SIGN COMPLEMENTOR • • • (7 BITS) • • • (7 BITS) 1 fREF INPUT TO D/A CONVERTER SIGN BIT 8-BIT DIGITAL-TO-ANALOG CONVERTER LOW-PASS FILTER SINEWAVE OUTPUT INPUT TO LOW-PASS FILTER (ANALOG SIGNAL) OUTPUT OF LOW-PASS FILTER (ANALOG SIGNAL) Figure 4. Detailed Block Diagram of the ML2036 6 REV. 1.0.2 7/26/01 PRODUCT SPECIFICATION ML2036 Functional Description The ML2036 has a VREF input that can be tied to VCC or generated from an external voltage. With the GAIN input equal to a logic “1”, the sine wave peak-to-peak voltage is equal to ±VREF; with the GAIN equal to a logic “0”, the peak voltage is ±VREF/2. However, the overall output voltage swing is limited to no closer than 1.5V to either rail. This means that to avoid clipping, VREF can only be tied to VCC when GAIN is a logic “0”. The sinewave output is referenced to AGND. The ML2036 is composed of a programmable frequency generator, a sine wave generator, a crystal oscillator, and a serial digital interface. The ML2036 frequency and sine wave generator functional block diagram is shown in Figure 4. Programmable Frequency Generator The programmable frequency generator produces a digital output whose frequency is determined by a 16-bit digital word. The analog section is designed to operate over a range from DC to 50kHz. Due to slew rate limitations, the peak-to-peak output voltage must be limited to VOUT(P-P) ≤ (125kV x Hz)/fOUT. For example, an output at 50kHz must be limited to 2.5VP-P. VOUT can drive a 1kΩ, 100pF load and swing to within 1.5V of VCC and VSS, provided the slew rate limitations mentioned above are not exceeded. The frequency generator is composed of a phase accumulator which is clocked at fCLK IN/4. The value stored in the data latch is added to the phase accumulator every 4 cycles of CLK IN. The frequency of the analog output is equal to the rate at which the accumulator overflows and is given by the equation: f CLKIN X ( D15 – D0 ) DEC f OUT = -------------------------------------------------------------23 2 The output offset voltage, VOS, is a function of the peak-topeak output voltage and is specified as: 2.5 + V OUT ( P – P ) V OS ( MAX ) = ± -------------------------------------------- 100 (1) The frequency resolution and the minimum frequency are the same and is given by the following equation: f CLKIN ∆f MIN = ---------------23 2 (3) For example, if VOUT(P-P) = 2.5V: 2.5 + 2.5 V OS ( MAX ) = ± ----------------------- = ± 50mV 100 (2) Crystal Oscillator When fCLK IN = 12.352MHz, ∆fMIN = 1.5Hz (±0.75Hz). Lower frequencies are obtained by using a lower input clock frequency. The crystal oscillator generates an accurate reference clock for the programmable frequency generator. The internal clock can be generated with a crystal or external clock. Due to the phase quantization nature of the frequency generator, spurious tones can be present in the output range of –55dB relative to fundamental. The energy from these tones is included in the signal to noise + distortion specification. The frequency of these tones can be very close to the fundamental. Therefore, it is not practical to filter them out. If a crystal is used, it must be placed between CLK IN and DGND of the ML2036. An on-chip crystal oscillator will then generate the internal clock. No other external capacitors or components are required. The crystal should be a parallelresonant type with a frequency between 3MHz to 12.4MHz. It should be placed physically as close as possible to the CLK IN and DGND. Sinewave Generator The sinewave generator is composed of a sine look-up table, a DAC, and an output smoothing filter. The sine look-up table is addressed by the phase accumulator. The DAC is driven by the output of the look-up table and generates a staircase representation of a sine wave. An external clock can drive CLK IN directly if desired. The frequency of this clock can be anywhere between 0 and 12MHz. The output filter smoothes the analog output by removing the high frequency sampling components. The resultant voltage on VOUT is a sinusoid with the second and third harmonic distortion components at least 45dB below the fundamental. SCK SID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LATI Figure 5. Serial Interface Timing. REV. 1.0.2 7/26/01 7 ML2036 The crystal must have the following characteristics: 1. Parallel resonant type 2. Frequency: 3MHz to 12.4MHz 3. Maximum equivalent series resistance of 15Ω at a drive levels of 1µW to 200µW, and 30Ω at drive levels of 10nW to 1µW 4. Typical load capacitance: 18pF 5. Maximum case capacitance: 7pF The frequency of oscillation will be a function of the crystal parameters and PC board capacitance. Crystals that meet these requirements at 12.352000MHz are M-tron 3709-010 12.352 for 0°C to 70°C and 3709-020 12.352 for -40°C to 85°C operation. The ML2036 has two clock outputs that can be used to drive other external devices. The CLK OUT 1 output is a buffered output from the oscillator divided by 2. The CLK OUT 2 output is a buffered output from the oscillator divided by 8. Serial Digital Interface The digital interface consists of a shift register and data latch. The serial 16-bit data word on SID is clocked into a 16-bit shift register on rising edges of the serial shift clock, SCK. The LSB should be shifted in first and the MSB last as shown in Figure 4. The data that has been shifted into the shift register is loaded into a 16-bit data latch on the falling edge of LATI. To insure that true data is loaded into the data latch from the shift register, LATI falling edge should occur when SCK is low, as shown in figure 1. LATI should be low while shifting data into the shift register to avoid inadvertently entering the power down mode. Note that all data is entered and latched on the edges, not levels, of SCK and LATI. 8 PRODUCT SPECIFICATION Inhibit and Power Down Modes The ML2036 has an inhibit mode and a power down mode which are controlled by the three-level PDN–INH input as described in Table 1. If a logic “1”, (VI3) is applied to the PDN–INH pin, the power down mode is entered by entering all zeros in the shift register and applying a logic “1” to LATI and holding it high. A zero data detect circuit detects when all bits in the shift register are zeros. In this state, the power consumption is reduced to 11.5mW max, and VOUT goes to 0V as shown in Figure 6 and appears as 10kΩ to AGND. CLK IN can be left active or removed during power down mode. Also, the ML2036 can be placed in the power down mode by applying a logic “0” to the PDN–INH pin, regardless of the contents of the shift register and the state of LATI. If VSS to VSS + 0.5V (VI2) is applied to the PDN–INH pin, the inhibit mode is entered by shifting all zeros into the shift register and applying a logic “1” to the LATI pin. Once the inhibit mode is entered VOUT will complete the last half cycle of the sinewave and then be held at approximately VOS, such that no voltage step occurs, as shown in Figure 6. Power Supplies The analog circuits in ML2036 are powered from VCC to VSS and are referenced to AGND. The digital circuits in the device are powered from VCC to DGND. It is recommended that AGND and DGND be connected together close to the device, and have a good connection back to the power source. It is recommended that the power supplies to the device should be bypassed by placing decoupling capacitors from VCC to AGND and VSS to AGND as physically close to the device as possible. REV. 1.0.2 7/26/01 PRODUCT SPECIFICATION ML2036 Table 1. Three Level PDN-INH Functions. PDN-INH MODE PDN-INH PIN DATA IN SHIFT REG. LATI SINE WAVE OUTPUT VI1, Logic “0” X X VOUT = 0V (10kΩ to AGND) Inhibit VI2, Inhibit State Voltage, VSS to VSS + 0.5V All 0’s Logic “1” VOUT goes to approximately VOS at the next VOS crossing (See Figure 6) PDN(1) VI3, Logic “1” All 0’s Logic “1” VOUT = 0V (10kΩ to AGND) (1) PDN Note: 1. In the power down mode, the oscillator, CLK OUT 1 and CLK OUT 2, shift register, and data latch are all functional. VOS POWER DOWN MODE 0V VX VOS INHIBIT MODE |VX| = VPEAK , FOR f fCLK OUT ≤ 256 2048 |VX| ≤ VPEAK + V 8 π fOUT + π PEAK SIN 256 fCLK 512 0V FOR fOUT > fCLK 2048 SCK SID 0 1 2 3 4 5 6 7 8 9 10 11 12 131415 LATI Figure 6. Power Down Mode Waveforms. REV. 1.0.2 7/26/01 9 PRODUCT SPECIFICATION ML2036 Typical Applications ML2003 ML2004 ATTENUATION /GAIN RECEIVE LINE INTERFACE TONE DETECTOR ML2021 LINE EQUALIZER LOOPBACK RELAY µP ML2003 ML2004 ATTENUATION /GAIN TRANSMIT LINE INTERFACE ML2036 TONE GENERATOR Figure 7. 4-Wire Termination Equipment. 5V ML2036 VCC GAIN 0.1µF GND VOUT 0.1µF VSS VREF 2.5V REF –5V Figure 8. Sine Wave Generator with ± 2.5VP-P. REV. 1.0.2 7/26/01 10 PRODUCT SPECIFICATION ML2036 Mechanical Dimensions Inches (Millimeters) Package: P14 14-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 14 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.25) PIN 1 ID 1 0.070 MIN (1.77 MIN) (4 PLACES) 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.016 - 0.022 (0.40 - 0.56) 0.125 MIN (3.18 MIN) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S16W 16-Pin Wide SOIC 0.400 - 0.414 (10.16 - 10.52) 16 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.090 - 0.094 (2.28 - 2.39) REV. 1.0.2 7/26/01 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.009 - 0.013 (0.22 - 0.33) 11 ML2036 PRODUCT SPECIFICATION Ordering Information Part Number Temperature Range Package ML2036CP ML2036CS 0°C to 70°C 0°C to 70°C 14-Pin PDIP (P14) 16-Pin Wide SOIC (S16W) ML2036IP -40°C to 85°C 14-Pin PDIP (P14) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 7/26/01 0.0m 003 Stock#DS30002008 © 2001 Fairchild Semiconductor Corporation