FUJITSU SEMICONDUCTOR DATA SHEET DS04-21309-2E ASSP Serial Input PLL Frequency Synthesizer MB1511 ■ DESCRIPTION The Fujitsu MB1511 is a single chip serial input PLL frequency synthesizer designed for VHF tuner and cellular telephone applications. It contains a 1.1 GHz dual modulus prescaler which enables pulse swallow function, and an analog switch to speed up lock up time. It operates supply voltage of 3.0 V typ. and dissipates 7 mA typ. of current realized through the use of Fujitsu's unique U-ESBIC Bi-CMOS technology. The MB1511 is housed in SSOP package, this enables high integration. ■ FEATURES • • • • • Low power supply voltage: VCC = 2.7 to 5.5 V High operating frequency: fIN MAX = 1.1 GHz (VIN MIN = –10dBm) Pulse swallow function: 64/65 or 128/129 Low supply current: ICC = 7 mA typ. Serial input 18-bit programmable divider consisting of: Binary 7-bit swallow counter: 0 to 127 Binary 11-bit programmable counter: 16 to 2047 • Serial input 15-bit programmable reference divider consisting of: Binary 14-bit programmable reference counter: 8 to 16383 1-bit switch counter (SW) sets divide ratio of prescaler (Continued) ■ PACKAGE 20 pin, Plastic SSOP (FPT-20P-M03) 1 MB1511 (Continued) • On-chip analog switch achieves fast lock up time • 2 types of phase detector output On-chip charge pump (Bipolar type) Output for external charge pump • Wide operating temperature: –40°C to +85°C • 20-pin Plastic Shrink Small Outline Package (Suffix: –PFV) ■ PIN ASSIGNMENT (TOP VIEW) OSC IN 1 20 φR NC 2 19 NC OSC OUT 3 18 φP VP 4 17 fout V CC 5 16 BiSW DO 6 15 FC GND 7 14 LE LD 8 13 Data NC 9 12 NC fin 10 11 Clock (FPT-20P-M03) 2 MB1511 ■ PIN DESCRIPTION Pin No. Pin Name I/O 1 OSCIN I 3 OSCOUT O Oscillator input. Oscillator output. A crystal is placed between OSCIN and OSCOUT. 4 VP — Power supply input for charge pump and analog switch. 5 VCC — Power supply voltage input. 6 DO O Charge pump output. The characteristics of charge pump is reversed depending upon FC input. 7 GND — Ground. 8 LD O Phase comparator output. Normally this pin outputs high level. While the phase difference of fr and fp exists, this pin outputs low level. 10 fIN I Prescaler input. The connection with an external VCO should be AC connection. 11 Clock I Clock input for 19-bit shift register and 16-bit shift register. On rising edge of the clock shifts one bit of data into the shift registers. I Binary serial data input. The last bit of the data is a control bit which specified destination of shift registers. When this bit is high level and LE is high level, the data stored in shift register is transferred to 15-bit latch. When this bit is low level and LE is high level, the data is transferred to 18-bit latch. 13 Data Functions 14 LE I Load enable input (with internal pull up resistor). When LE is high or open, the data stored in shift register is transferred into latch depending upon the control bit. At the time, internal charge pump output is connected to BISW pin because internal analog switch becomes ON state. 15 FC I Phase select input of phase comparator (with internal pull up resistor). When FC is low level, the characteristics of charge pump, phase comparator is reversed. FC input signal controls fout pin (test pin) output level, fr or fp. 16 BISW O Analog switch output. Usually BISW pin is set high-impedance state. When internal analog switch is ON (LE pin is high level), this pin outputs internal charge pump output. Minitor pin of phase comparator input. fout pin outputs either programmable reference divider output (fr) or programmable divider output (fp) depending upon FC pin input level. FC = H: It is the same as fr output level. FC = L: It is the same as fp output level. 17 fOUT O 18 φP O 20 φR O Output for external charge pump. The characteristics are reversed according to FC input. φP pin is N-channel open drain output. 2, 9 12, 19 NC — No connection. 3 MB1511 ■ BLOCK DIAGRAM 16 bit shift register V CC 5 16 bit shift register 17 fOUT GND 7 15 bit latch Monitor frequency changing circuit Programmable reference divider OSC IN 1 Cristal oscillator 15 FC 8 LD fr Binary 14-bit S reference counter W fp OSC OUT 3 Phase comparator 15 bit latch LE 14 20 φR 18 φP Analog switch 16 BISW Charge pump 4 VP 19 bit shift register 19 bit shift register 6 DO 18 bit latch fIN 10 Prescaler 7 bit latch 11 bit latch Programmable Binary 7 bit swallow counter Data 13 Binary 11 bit programmable counter Control 1 bit latch Control circuit Clock 11 : Data signal : Control signal 4 MB1511 ■ FUNCTIONAL DESCRIPTIONS 1. Pulse Swallow Function The divide ratio is set using the following equation. fVCO = [(M × N) + A] × fOSC ÷ R fVCO : Output frequency of external voltage controlled oscillator (VCO) M : Preset modulus of external dual modulus prescaler (64 or 128) N : Preset divide ratio of binary 11-bit programmable counter (16 to 2047) A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N) fOSC : Output frequency of the external reference frequency oscillator R : Preset divide ratio of binary 14-bit programmable reference counter (8 to 16383) 2. Serial Data Input Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15bit programmable reference divider and 18-bit programmable divider, respectively. Binary serial data is input to Data pin. On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored data is transferred into latch depending upon the control bit. Control data "H" data is transferred into 15-bit latch. Control data "L" data is transferred into 18-bit latch. 5 MB1511 (1) Programmable Reference Divider Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is shown below. Control bit Divide ratio of prescaler setting bit LSB C MSB S S S S S S S S S S S S S S S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 W Divide ratio of programmable reference counter setting bit Divide Ratio S S S S S S S S S S S S S S R 14 13 12 11 10 9 8 7 6 5 4 3 2 1 8 0 0 0 0 0 0 0 0 0 0 1 0 0 0 9 0 0 0 0 0 0 0 0 0 0 1 0 0 1 … … … … … … … … … … … … … … … • 14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16383 NOTES: Divide ratio less than 8 is prohibited. Divide ratio: 8 to 16383 SW: This bit selects divide ratio of prescaler. SW = H: 64/65 SW = L: 128/129 S1 to S14: These bits select divide ratio of programmable reference divider. C: Control bit (sets as high level). Data is input from MSB side. 6 MB1511 (2) Programmable Divider Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter. Serial 19-bit data format is shown following page. Control bit LSB C MSB S S S S S S S S S S S S S S S S S S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Divide ratio of swallow counter setting bit Divide ratio of programmable counter setting bit • 7-bit Swallow Counter Divide Ratio A 7 6 5 4 3 2 1 N 18 17 16 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 16 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1 17 0 0 0 0 0 0 1 0 0 0 1 … … … S … S … S … S … S … S … S … S … S … S … Divide Ratio S … S … S … S … S … S … S … Divide Ratio S • 11-bit Programmable Counter Divide Ratio 1 1 1 1 1 1 1 2047 1 1 1 1 1 1 1 1 1 1 1 127 Note: Divide ratio: 0 to 127 Notes: Divide ratio less than 16 is prohibited. Divide ratio: 16 to 2047 S1 to S7: Swallow counter divide ratio setting bit. (0 to 127) S8 to S18: Programmable counter divide ratio setting bit. (16 to 2047) C: Control bit (sets as low level). Data is input from MSB side. 3. Serial Data Input Timing t 1~t 5 ≤ 1 µs Data S18 = MSB * (SW) S17 S10 (S14) (S8) S9 S1 = LSB (S7) (S1) C : CONTROL BIT (C : CONTROL BIT) Clock LE t 1 t2 t3 t4 t5 Notes: Paranthesis data is used for setting divide ratio of programmable reference divider. On rising edge of clock shifts one bit of data in the shift register. 7 MB1511 4. Phase Characteristics FC pin is provided to change phase characteristics of phase comparator. Characteristics of internal charge pump output level (DO), phase comparator output level (φR, φP) are reversed depending upon FC pin input level. Also, monitor pin (fOUT) output level of phase comparator is controlled by FC pin input level. The relation between outputs (DO, φR, φP) and FC input level are shown below. FC : “H” or open FC : “L” DO φR φP fOUT DO φR φP fOUT fr > fp H L L (fr) L H Z (fp) fr = fp Z L Z (fr) Z L Z (fp) fr < fp L H Z (fr) H L L (fp) Note: Z = (High impedance) • When VCO characteristics are like (1), FC should be set High or open circuit; When VCO characteristics are like (2), FC should be set Low. VCO Output Frequency Depending upon VCO characteristics, FC pin should be set accordingly: (1) (2) VCO Input Voltage 8 MB1511 Phase comparator output waveforms are shown below. fr fp LD H DO Z fr > fp L fr < fp fr = fp fr < fp fr < fp Notes: Phase difference detection range: –2π to +2π Spike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band. When fr>fp or fr<fp, spike might not appear depending upon charge rump characteristics. 5. Analog Switch ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (DO) is connected to BISW pin. When the analog switch is OFF, BISW pin is set to high-impedance state. LE Analog Switch H (Changing the divide ratio of internal prescaler) ON L (Normal operationg mode) OFF When an analog switch is inserted between LP1 and LP2, faster lock up times is achieved to reduce LPF time constant during PLL channal switching. DO CHARGE PUMP LPF-1 LPF-2 VCO BISW ANALOG SW (CONTROL SIGNAL LE) 9 MB1511 ■ ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Symbol Rating Unit VCC –0.5 to 7.0 V VP VCC to 10.0 V Output voltage VOUT –0.5 to VCC +0.5 V Open-drain voltage VOOP –0.5 to 8.0 V Output current IOUT ±10 mA Storage temperature TSTG –55 to +125 °C Power supply voltage WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Value Unit Min. Typ. Max. VCC 2.7 3.0 5.5 V VP VCC — 8.0 V Input voltage VIN GND — VCC V Operating temperature Ta –40 — +85 °C Power supply voltage HANDLING PRECAUTIONS • This device should be transported and stored in anti-static containers. • This is static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. • Always turn the power supply off before inserting or removing the device from its socket. • Protect leads with a conductive sheet when handing or transporting PC boards with devices. 10 MB1511 ■ ELECTRICAL CHARACTERINSTICS (VCC = 2.7 V to 5.5 V, Ta = –40°C to +85°C) Parameter Symbol Input sensitivity High-level input voltage Low-level input voltage High-level input current Low-level input current Input current High-level output current Unit Min. Typ. Max. ICC — 7.0 — mA fIN 10 — 1100 MHz OSCIN fOSC — 12 20 MHz fin-1* 3 Vfin1 –4 — 6 dBm fin-2* 4 Vfin2 –10 — 6 dBm OSCIN VOSC 0.5 — — Vp-p VIH VCC×0.7 — — V VIL — — VCC×0.3 V IIH — 1.0 — µA IIL — –1.0 — µA OSCIN IOSC — ±50 — µA LE, FC ILE — –60 — µA VOH*5 2.2 — — V VOL — — 0.4 V Power supply current*1 Operating frequency Values fin*2 Except fin and OSCIN Data clock Low-level output current Except DO and OSCOUT N-channel open drain cutoff current DO, φP*6 IOFF — — 1.1 µA Output current Except DO and OSCOUT IOH –1.0 — — mA IOL 1.0 — — mA RON — 50 — Ω Analog switch on resistance Notes: *1 *2 *3 *4 *5 *6 fin =1.1 GHz, OSCIN=12 MHz, VCC=3V. Inputs are grounded and outputs are open. AC coupling. Minimum operating frequency is measured when a capacitor 1000pF. VCC=4.0 to 5.5V, 50 Ω VCC=2.7 to 4.0V, 50 Ω VCC=3V VP=VCC to 8V, VOOP=GND to 8V 11 MB1511 ■ MEASURMENT CIRCUIT VCC = 3 V X'tal VP = 6 V 1000 pF 0.1 µF P•G 50 Ω 10 11 12 7 13 14 5 4 17 3 1 Oscilloscope MB1511 ■ TYPICAL APPLICATION EXAMPLE VPX (6V) 10 kΩ L P F 12 kΩ OUTPUT V C O 12 kΩ From Controller 10 kΩ 47 kΩ 20 φR 18 φP 17 fout 16 BiSW 15 FC 14 LE 13 Data 11 Clock 47 kΩ MB1511 OSC IN OSC OUT VP V CC DO GND LD fin 1 3 4 5 6 7 8 10 X'tal C1 6V C2 1000 pF 3V V CC (3 V) 0.1 µF 100 kΩ 33 kΩ 0.01 µF VPX, VP : 8V max. C1 , C2 Depends on crystal oscillator : LE, FC : With internal pull up resistor φP Open drain output : Lock Detector 10 kΩ 13 MB1511 ■ PACKAGE DIMENSION 20 pin, Plastic SSOP (FPT-20P-M03) *: This dimension does not include resin protruction. +0.20 * 6.50±0.10(.256±.004) 1.25 –0.10 +.008 .049 –.004 0.10(.004) INDEX *4.40±0.10 6.40±0.20 (.173±.004) (.252±.008) 0.65±0.12 (.0256±.0047) 5.85(.230)REF C 14 1994 FUJITSU LIMITED F20012S-2C-4 +0.10 0.22 –0.05 +.004 .009 –.002 "A" 5.40(.213) NOM +0.05 0.15 –0.02 +.002 .006 –.001 Details of "A" part 0.10±0.10(.004±.004) (STAND OFF) 0 10° 0.50±0.20 (.020±.008) Dimensions in mm (inches). MB1511 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. 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