March 1997 ML2036* Serial Input Programmable Sine Wave Generator with Digital Gain Control GENERAL DESCRIPTION FEATURES The ML2036 is a monolithic sine wave generator whose output is programmable from DC to 50kHz. No external components are required. The frequency of the sinewave output is derived from either an external crystal or clock input, providing a stable and accurate frequency reference. The frequency is programmed by a 16-bit serial data word. ■ Programmable output frequency - DC to 50kHz ■ Low gain error and total harmonic distortion ■ 3-wire SPI compatible serial microprocessor interface with double buffered data latch ■ Fully integrated solution - no external components required ■ Frequency resolution of 1.5Hz (±0.75Hz) with a 12MHz clock input ■ Onboard 3 to 12MHz crystal oscillator ■ Clock outputs of 1/2 or 1/8 of the input clock frequency ■ Synchronous or asynchronous data loading capability ■ Compatible with ML2031 and ML2032 tone detectors and ML2004 logarithmic gain/attenuator The ML2036 provides for a VOUT amplitude of either ±VREF or ±VREF/2. Also included with the ML2036 is an inhibit function which allows the sinewave output to be held at zero volts after completing the last half cycle of the sine wave in progress. Two digital clock outputs are provided to drive other devices with one half or one eighth of the input clock frequency. The ML2036 is intended for telecommunications and modem applications that need low cost and accurate generation of precise test tones, call progress tones, and signaling tones. BLOCK DIAGRAM (Pin Configuration Shown for 14-Pin PDIP Version) 9 13 VREF CLK IN 14 CLK OUT 1 3 CRYSTAL OSCILLATOR ÷2 ÷2 CLK OUT 2 4 GAIN 8-BIT DAC 5kΩ SMOOTHING FILTER 5kΩ VOUT - 10 + 8 PHASE ACCUMULATOR & 512 POINT SINE LOOK-UP TABLE ÷2 VCC ZERO DETECT 8 AGND 11 16 LATI DGND 16-BIT DATA LATCH 4 SCK 12 16 2 SID VSS 16-BIT SHIFT REGISTER 1 3 PDN-INH 2 * Some Packages Are Obsolete 1 ML2036 PIN CONFIGURATION ML2036 16-Pin Wide SOIC (S16W) ML2036 14-Pin PDIP (P14) VSS 1 PDN-INH 2 14 CLK IN 13 GAIN NC 1 16 CLK IN VSS 2 15 GAIN PDN-INH 3 14 NC CLK OUT 1 4 13 DGND CLK OUT 2 5 12 AGND SCK 6 11 VOUT CLK OUT 1 3 12 DGND CLK OUT 2 4 11 AGND SCK 5 10 VOUT SID 6 9 VREF SID 7 10 VREF LATI 7 8 VCC LATI 8 9 VCC TOP VIEW TOP VIEW PIN DESCRIPTION (Pin Number in Parentheses is for SOIC Version) PIN NAME FUNCTION PIN NAME FUNCTION 1 (2) VSS Negative supply (-5V). 8 (9) VCC Positive supply (5V). 2 (3) PDN-INH Three level input which controls the inhibit and power down modes. Current source pull-up to VCC. 9 (10) VREF Reference input. The voltage on this pin determines the peak-topeak swing of VOUT. VREF can be tied to VCC. 3 (4) CLK OUT 1 Digital clock output from the internal clock generator that can drive other devices at fCLK OUT 1 = fCLK IN/2. 10 (11) VOUT Analog output. 11 (12) AGND Analog ground. All analog inputs and outputs are referenced to this point. 12 (13) DGND Digital ground. All digital inputs and outputs are referenced to this point. 4 (5) CLK OUT 2 Digital clock output from the internal clock generator that can drive other devices at fCLK OUT 2 = fCLK IN/8. 5 (6) SCK Serial clock. Digital input which clocks in serial data on its rising edges. 13 (15) GAIN Sets VOUT peak amplitude to VREF or VREF/2. Current source pulldown to DGND. 6 (7) SID Serial input data which programs the frequency of VOUT. 14 (16) CLK IN 7 (8) LATI Digital input which latches serial data into the internal data latch on falling edges. Clock input. The internal clock can be generated by tying a 3 to 12MHz crystal from this pin to DGND, or by applying a digital clock signal directly to the pin. 2 ML2036 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Thermal Resistance (qJA) 14-Pin PDIP ..................................................... 88ºC/W 16-Pin Wide SOIC .......................................... 105ºC/W VCC .............................................................................................. 6.5V VSS ............................................................................................. -6.5V VOUT .................................................... VSS - 0.3V to VCC + 0.3V Voltage on any other pin ........ GND - 0.3V to VCC + 0.3V Input Current ........................................................ ±25mA Junction Temperature .............................................. 150ºC Storage Temperature Range ...................... –65ºC to 150ºC Lead Temperature (Soldering, 10 sec) ...................... 260ºC OPERATING CONDITIONS Temperature Range ML2036CX ................................................. 0ºC to 70ºC ML2036IX ............................................... -40ºC to 85ºC VCC Range ................................................... 4.5V to 5.5V VSS Range ................................................. -4.5V to -5.5V ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 4.5V to 5.5V, VSS = -4.5V to -5.5V, VREF = 2.5V to VCC, CLK IN = 12.352MHz, CL = 100pF, RL = 1kW, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS OUTPUT HD SND VGN ICN PSRR Harmonic Distortion (Note 2) 20Hz to 5kHz -45 dB (2nd and 3rd Harmonic) 5kHz to 50kHz -40 dB Signal to Noise + Distortion (Note 2) 200Hz to 3.4kHz, fOUT BW = 200Hz to 4kHz -45 dB 20Hz to 50kHz, fOUT BW = 20 Hz to 150kHz -40 dB 20Hz < fOUT < 5kHz ±0.15 dB 5kHz < fOUT < 50kHz ±0.3 dB 0 dBrnc Gain Error (Note 2) Idle Channel Noise Power Supply Rejection Ratio VOS VOUT Offset Voltage (Note 3) VP-P Peak-to-Peak Output Voltage (Note 2) Power Down Mode, Cmsg Weighted -20 Power Down Mode, 1kHz 50 nV/ÖHz Inhibit Mode, 1kHz 500 nV/ÖHz 200mVP-P, 0 - 10kHz VCC -40 dB Sine, Measured on VOUT VSS -40 dB ±(2.5+VP-P) 100 V GAIN = VCC GAIN = DGND VOUT Swing RREF Reference Input Resistance GAIN = VCC ±VREF V ±VREF/2 V VSS + 1.5 1 VCC -1.5 6 V MW OSCILLATOR VIL CLK CLK IN Input Low Voltage 1.5 VIH CLK CLK IN Input High Voltage 3.5 V IIL CLK CLK IN Input Low Current -250 µA IIH CLK CLK IN Input High Current CIN CLK CLK IN Input Capacitance 250 12 V µA pF 3 ML2036 ELECTRICAL CHARACTERISTICS SYMBOL (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS OSCILLATOR (Continued) tCKI t1R, t2R t1F, t2F CLK IN On/Off Period tR = tF = 10ns, 2.5V Midpoint CLK OUT 1/CLK IN Frequency Ratio See Figure 2 0.49 0.51 CLK OUT 2/CLK IN Frequency Ratio See Figure 2 0.122 0.128 CLK OUT 1, CLK OUT 2 Rise Time CL = 40pF, 10% to 90% 20 ns CL = 100pF, 0.8V to 2.0V Transition 20 ns CL = 40pF, 90% to 10% 20 ns CL = 100pF, 2.0V to 0.8V Transition 20 ns 0.8 V CLK OUT 1, CLK OUT 2 Fall Time 30 ns LOGIC VIL Input Low Voltage (LATI, SCK, SID, GAIN) VIH Input High Voltage (LATI, SCK, SID, GAIN) 2.0 VI1 Input Low Voltage - PDN-INH -0.5 VI2 Inhibit Stage Voltage - PDN-INH VI3 Input High Voltage - PDN-INH IIL-PDN 0.8 V VSS + 0.5 V 2.0 PDN-INH Input Low Current PDN-INH = 0V GAIN Input High Current IIL Input Low Current (LATI, SCK, SID, GAIN) IIH Input High Current (LATI, SCK, SID, GAIN) VIN = VCC CIN Input Capacitance VOL Output Low Voltage IOL = -2mA VOH Output High Voltage IOH = 2mA tSCK IIH-GAIN V V -70 -20 -5 µA GAIN = VCC 5 20 70 µA VIN = 0V -1 µA 1 5 µA pF 0.4 V 4.0 V Serial Clock On/Off Period 100 ns tDS SID Data Setup Time 50 ns tDH SID Data Hold Time 50 ns tLPW LATI Pulse Width 50 ns tLH LATI Hold Time 50 ns tLS LATI Setup Time 50 ns SUPPLY ICC ISS VCC Current VSS Current No Load, VCC = VREF = 5.5V 5.5 mA No Load, Power Down Mode 2 mA No Load, VCC = VREF = 5.5V, VSS = -5.5V -3.5 mA No Load, Power Down Mode -100 µA Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Note 2: Maximum peak-to-peak voltage for the output sine wave is: VOUT(P-P) £ (125kV x Hz)/fOUT. For example, at 50kHz, the maximum output voltage swing is 2.5V P-P. Note 3: Offset voltage is a function of the peak-to-peak output voltage. For example, if VOUT(P-P) = 2.5V, VOS = ±50mV max. 4 ML2036 tCKI tCKI tSCK tSCK CLK IN SCK tDS tDH SID tLH tLS LATI tLPW Figure 1. Serial Interface Timing. fCLKIN CLKIN t1R fCLK1 t1F CLKOUT1 fCLK2 CLKOUT2 t2R t2F fCLK PARAMETERS REFERRED TO 1.4V MIDPOINT Figure 2. Digital Clock Output Timing. 100 75 INPUT CURRENT (µA) 50 25 0 -25 -50 -75 -100 0 1 2 3 4 5 INPUT VOLTAGE (V) Figure 3. CLK IN Input Current vs. Input Voltage. 5 ML2036 16-BIT SHIFT REGISTER SID (16 BITS) • • • 16-BIT DATA LATCH LATI (16 BITS) • • • ••• 21-BIT ADDER – – A16 A0 A20 A15 BINARY PHASE ACCUMULATOR B0–B20 SUM (21 BITS) • • • fREF 21-BIT LATCH Q0 LEAST SIGNIFICANT (12 BITS) ••• SIGN BIT PHASE SAMPLES (7 BITS) CLKIN CRYSTAL OSCILLATOR Q20 ••• INPUT TO QUADRANT COMPLEMENTOR QUADRANT BIT T= QUADRANT COMPLEMENTER ÷4 • • • (7 BITS) SIGN BIT READ-ONLY MEMORY (128 X 7) SIGN COMPLEMENTOR fREF SIGN BIT INPUT TO D/A CONVERTER SIGN BIT 8-BIT DIGITAL-TO-ANALOG CONVERTER LOW-PASS FILTER SINEWAVE OUTPUT Figure 4. Detailed Block Diagram of the ML2036. 6 PICTORIAL PRESENTATION OF DIGITAL DATA INPUT TO OUTPUT LATCH OUTPUT LATCH • • • (7BITS) INPUT TO ROM INPUT TO SIGN COMPLEMENTOR • • • (7 BITS) • • • (7 BITS) 1 fREF INPUT TO LOW-PASS FILTER (ANALOG SIGNAL) OUTPUT OF LOW-PASS FILTER (ANALOG SIGNAL) ML2036 FUNCTIONAL DESCRIPTION The ML2036 has a VREF input that can be tied to VCC or generated from an external voltage. With the GAIN input equal to a logic "1", the sine wave peak-to-peak voltage is equal to ±VREF; with the GAIN equal to a logic "0", the peak voltage is ±VREF/2. However, the overall output voltage swing is limited to no closer than 1.5V to either rail. This means that to avoid clipping, VREF can only be tied to VCC when GAIN is a logic "0". The sinewave output is referenced to AGND. The ML2035 is composed of a programmable frequency generator, a sine wave generator, a crystal oscillator, and a serial digital interface. The ML2036 frequency and sine wave generator functional block diagram is shown in Figure 4. PROGRAMMABLE FREQUENCY GENERATOR The programmable frequency generator produces a digital output whose frequency is determined by a 16-bit digital word. The analog section is designed to operate over a range from DC to 50kHz. Due to slew rate limitations, the peakto-peak output voltage must be limited to VOUT(P-P) £ (125kV x Hz)/fOUT. For example, an output at 50kHz must be limited to 2.5VP-P. VOUT can drive a 1kW, 100pF load and swing to within 1.5V of VCC and VSS, provided the slew rate limitations mentioned above are not exceeded. The frequency generator is composed of a phase accumulator which is clocked at fCLK IN/4. The value stored in the data latch is added to the phase accumulator every 4 cycles of CLK IN. The frequency of the analog output is equal to the rate at which the accumulator overflows and is given by the equation: fOUT = 0 5 fCLKIN × D15 − D0 223 DEC The output offset voltage, VOS, is a function of the peak-topeak output voltage and is specified as: (1) VOS0MAX5 = ± The frequency resolution and the minimum frequency are the same and is given by the following equation: ∆fMIN = 25. + V 0 5 100 OUT P −P (3) For example, if VOUT(P-P) = 2.5V: fCLKIN (2) 223 VOS0 MAX5 = ± When fCLK IN = 12.352MHz, DfMIN = 1.5Hz (±0.75Hz). Lower frequencies are obtained by using a lower input clock frequency. 25. + 25. = ±50mV 100 CRYSTAL OSCILLATOR The crystal oscillator generates an accurate reference clock for the programmable frequency generator. The internal clock can be generated with a crystal or external clock. Due to the phase quantization nature of the frequency generator, spurious tones can be present in the output range of –55dB relative to fundamental. The energy from these tones is included in the signal to noise + distortion specification. The frequency of these tones can be very close to the fundamental. Therefore, it is not practical to filter them out. If a crystal is used, it must be placed between CLK IN and DGND of the ML2036. An on-chip crystal oscillator will then generate the internal clock. No other external capacitors or components are required. The crystal should be a parallel-resonant type with a frequency between 3MHz to 12.4MHz. It should be placed physically as close as possible to the CLK IN and DGND. SINE WAVE GENERATOR The sine wave generator is composed of a sine look-up table, a DAC, and an output smoothing filter. The sine look-up table is addressed by the phase accumulator. The DAC is driven by the output of the look-up table and generates a staircase representation of a sine wave. An external clock can drive CLK IN directly if desired. The frequency of this clock can be anywhere between 0 and 12MHz. The output filter smoothes the analog output by removing the high frequency sampling components. The resultant voltage on VOUT is a sinusoid with the second and third harmonic distortion components at least 45dB below the fundamental. SCK SID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LATI Figure 5. Serial Interface Timing. 7 ML2036 FUNCTIONAL DESCRIPTION (Continued) The crystal must have the following characteristics: INHIBIT AND POWER DOWN MODES 1. Parallel resonant type The ML2036 has an inhibit mode and a power down mode which are controlled by the three-level PDN–INH input as described in Table 1. If a logic "1", (VI3) is applied to the PDN–INH pin, the power down mode is entered by entering all zeros in the shift register and applying a logic "1" to LATI and holding it high. A zero data detect circuit detects when all bits in the shift register are zeros. In this state, the power consumption is reduced to 11.5mW max, and VOUT goes to 0V as shown in Figure 6 and appears as 10kW to AGND. CLK IN can be left active or removed during power down mode. Also, the ML2036 can be placed in the power down mode by applying a logic “0” to the PDN–INH pin, regardless of the contents of the shift register and the state of LATI. 2. Frequency: 3MHz to 12.4MHz 3. Maximum equivalent series resistance of 15W at a drive levels of 1µW to 200µW, and 30W at drive levels of 10nW to 1µW 4. Typical load capacitance: 18pF 5. Maximum case capacitance: 7pF The frequency of oscillation will be a function of the crystal parameters and PC board capacitance. Crystals that meet these requirements at 12.352000MHz are M-tron 3709-010 12.352 for 0ºC to 70ºC and 3709-020 12.352 for -40ºC to 85ºC operation. The ML2036 has two clock outputs that can be used to drive other external devices. The CLK OUT 1 output is a buffered output from the oscillator divided by 2. The CLK OUT 2 output is a buffered output from the oscillator divided by 8. If VSS to VSS + 0.5V (VI2) is applied to the PDN–INH pin, the inhibit mode is entered by shifting all zeros into the shift register and applying a logic “1” to the LATI pin. Once the inhibit mode is entered VOUT will complete the last half cycle of the sinewave and then be held at approximately VOS, such that no voltage step occurs, as shown in Figure 6. POWER SUPPLIES SERIAL DIGITAL INTERFACE The digital interface consists of a shift register and data latch. The serial 16-bit data word on SID is clocked into a 16-bit shift register on rising edges of the serial shift clock, SCK. The LSB should be shifted in first and the MSB last as shown in Figure 4. The data that has been shifted into the shift register is loaded into a 16-bit data latch on the falling edge of LATI. To insure that true data is loaded into the data latch from the shift register, LATI falling edge should occur when SCK is low, as shown in figure 1. LATI should be low while shifting data into the shift register to avoid inadvertently entering the power down mode. Note that all data is entered and latched on the edges, not levels, of SCK and LATI. 8 The analog circuits in ML2036 are powered from VCC to VSS and are referenced to AGND. The digital circuits in the device are powered from VCC to DGND. It is recommended that AGND and DGND be connected together close to the device, and have a good connection back to the power source. It is recommended that the power supplies to the device should be bypassed by placing decoupling capacitors from VCC to AGND and VSS to AGND as physically close to the device as possible. ML2036 PDN–INH MODE PDN–INH PIN DATA IN SHIFT REG. LATI SINE WAVE OUTPUT PDN(1) VI1, Logic "0" X X VOUT = 0V (10kW to AGND) Inhibit VI2, Inhibit State Voltage, VSS to VSS + 0.5V All 0‘s Logic "1" VOUT goes to approximately VOS at the next VOS crossing (See Figure 6) PDN(1) VI3, Logic "1" All 0‘s Logic "1" VOUT = 0V (10kW to AGND) Note 1: In the power down mode, the oscillator, CLK OUT 1 and CLK OUT 2, shift register, and data latch are all functional. Table 1. Three Level PDN-INH Functions. VOS POWER DOWN MODE 0V VX VOS INHIBIT MODE V f |VX| = PEAK , FOR fOUT ≤ CLK 256 2048 0V |VX| ≤ FOR fOUT > fCLK 2048 SCK SID VPEAK + V 8 π fOUT + π PEAK SIN 256 fCLK 512 0 1 2 3 4 5 6 7 8 9 10 11 12 131415 LATI Figure 6. Power Down and Inhibit Mode Waveforms. 9 ML2036 TYPICAL APPLICATIONS ML2003 ML2004 ML2008 ML2009 ATTENUATION /GAIN RECEIVE LINE INTERFACE ML2020 ML2021 LINE EQUALIZER ML2031 ML2032 TONE DETECTOR LOOPBACK RELAY µP ML2036 TONE GENERATOR ML2003 ML2004 ML2008 ML2009 ATTENUATION /GAIN TRANSMIT LINE INTERFACE Figure 7. 4-Wire Termination Equipment. 5V ML2036 VCC GAIN GND VOUT 0.1µF 0.1µF VSS VREF 2.5V REF –5V Figure 8. Sine Wave Generator with ±2.5VP-P. 10 ML2036 PHYSICAL DIMENSIONS inches (millimeters) Package: P14 14-Pin PDIP 0.740 - 0.760 (18.79 - 19.31) 14 0.240 - 0.260 0.295 - 0.325 (6.09 - 6.61) (7.49 - 8.25) PIN 1 ID 1 0.070 MIN (1.77 MIN) (4 PLACES) 0.050 - 0.065 (1.27 - 1.65) 0.100 BSC (2.54 BSC) 0.015 MIN (0.38 MIN) 0.170 MAX (4.32 MAX) 0.016 - 0.022 (0.40 - 0.56) 0.125 MIN (3.18 MIN) SEATING PLANE 0º - 15º 0.008 - 0.012 (0.20 - 0.31) Package: S16W 16-Pin Wide SOIC 0.400 - 0.414 (10.16 - 10.52) 16 0.291 - 0.301 0.398 - 0.412 (7.39 - 7.65) (10.11 - 10.47) PIN 1 ID 1 0.024 - 0.034 (0.61 - 0.86) (4 PLACES) 0.050 BSC (1.27 BSC) 0.095 - 0.107 (2.41 - 2.72) 0º - 8º 0.090 - 0.094 (2.28 - 2.39) 0.012 - 0.020 (0.30 - 0.51) SEATING PLANE 0.005 - 0.013 (0.13 - 0.33) 0.022 - 0.042 (0.56 - 1.07) 0.009 - 0.013 (0.22 - 0.33) 11 ML2036 ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE ML2036CP ML2036CS 0ºC to 70ºC 0ºC to 70ºC 14-Pin PDIP (P14) 16-Pin Wide SOIC (S16W) ML2036IP ML2036IS (Obsolete) -40ºC to 85ºC -40ºC to 85ºC 14-Pin PDIP (P14) 16-Pin Wide SOIC (S16W) © Micro Linear 1997. is a registered trademark of Micro Linear Corporation. Products described in this document may be covered by one or more of the following patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376. Other patents are pending. Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application. 12 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 DS2036-01