TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS110B – JANUARY 1995 – REVISED APRIL 1997 D D D D D D D D D D OR N PACKAGE (TOP VIEW) Four 8-Bit Voltage Output DACs 3-V Single-Supply Operation Serial Interface High-Impedance Reference Inputs Programmable for 1 or 2 Times Output Range Simultaneous Update Facility Internal Power-On Reset Low-Power Consumption Half-Buffered Output GND REFA REFB REFC REFD DATA CLK 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VDD LDAC DACA DACB DACC DACD LOAD applications D D D D D D Programmable Voltage Sources Digitally Controlled Amplifiers/Attenuators Mobile Communications Automatic Test Equipment Process Monitoring and Control Signal Synthesis description The TLV5620C and TLV5620I are quadruple 8-bit voltage output digital-to-analog converters (DACs) with buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either one or two times the reference voltages and GND; and, the DACs are monotonic. The device is simple to use, because it runs from a single supply of 3 V to 3.6 V. A power-on reset function is incorporated to ensure repeatable start-up conditions. Digital control of the TLV5620C and TLV5620I is over a simple three-wire serial bus that is CMOS compatible and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word comprises eight bits of data, two DAC select bits, and a range bit, the latter allowing selection between the times 1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be written to the device, then all DAC outputs update simultaneously through control of LDAC. The digital inputs feature Schmitt triggers for high noise immunity. The 14-terminal small-outline (SO) package allows digital control of analog functions in space-critical applications. The TLV5620C is characterized for operation from 0°C to 70°C. The TLV5620I is characterized for operation from – 40°C to 85°C. The TLV5620C and TLV5620I do not require external trimming. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE (D) PLASTIC DIP (N) 0°C to 70°C TLV5620CD TLV5620CN – 40°C to 85°C TLV5620ID TLV5620IN Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS110B – JANUARY 1995 – REVISED APRIL 1997 functional block diagram REFA 2 + – DAC 8 REFB 3 Latch + – DAC 8 REFC 4 DATA LOAD Latch Latch 8 DAC Latch ×2 + – 12 ×2 + – 11 ×2 + – 10 ×2 + – 9 DACA DACB DACC 5 + – DAC 8 CLK Latch 8 + – 8 REFD Latch 8 Latch Latch 8 DACD 7 6 Serial Interface 8 13 LDAC Power-On Reset Terminal Functions TERMINAL I/O DESCRIPTION 7 I Serial interface clock. The input digital data is shifted into the serial interface register on the falling edge of the clock applied to the CLK terminal. DACA 12 O DAC A analog output DACB 11 O DAC B analog output DACC 10 O DAC C analog output DACD 9 O DAC D analog output DATA 6 I Serial interface digital data input. The digital code for the DAC is clocked into the serial interface register serially. Each data bit is clocked into the register on the falling edge of the clock signal. GND 1 I Ground return and reference terminal LDAC 13 I Load DAC. When this signal is high, no DAC output updates occur when the input digital data is read into the serial interface. The DAC outputs are only updated when LDAC is taken from high to low. LOAD 8 I Serial interface load control. When the LDAC terminal is low, the falling edge of the LOAD signal latches the digital data into the output latch and immediately produces the analog voltage at the DAC output terminal. REFA 2 I Reference voltage input to DAC A. This voltage defines the output analog range. REFB 3 I Reference voltage input to DAC B. This voltage defines the analog output range. REFC 4 I Reference voltage input to DAC C. This voltage defines the analog output range. REFD 5 I Reference voltage input to DAC D. This voltage defines the analog output range. 14 I Positive supply voltage NAME CLK VDD 2 NO. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS110B – JANUARY 1995 – REVISED APRIL 1997 detailed description The TLV5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with 256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use of the resistor strings. Linearity depends upon the matching of the resistor segments and upon the performance of the output buffer. Since the inputs are buffered, the DACs always presents a high-impedance load to the reference source. Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times 1 or times 2 gain. On power up, the DACs are reset to CODE 0. Each output voltage is given by: V (DACA|B|C|D) O + REF CODE 256 (1 ) RNG bit value) where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word. Table 1. Ideal Output Transfer D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 OUTPUT VOLTAGE GND 0 0 0 0 0 0 0 1 (1/256) × REF (1+RNG) • • • • • • • • • • • • • • • • • • 0 1 1 1 1 1 1 1 (127/256) × REF (1+RNG) 1 0 0 0 0 0 0 0 (128/256) × REF (1+RNG) • • • • • • • • • • • • • • • • • • 1 1 1 1 1 1 1 1 (255/256) × REF (1+RNG) data interface With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When LDAC is high during serial programming, the new value is stored within the device and can be transferred to the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered MSB first. Data transfers using two 8-clock-cycle periods are shown in Figures 3 and 4. Table 2 lists the A1 and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output range. When RNG = low, the output range is between the applied reference voltage and GND, and when RNG = high, the range is between twice the applied reference voltage and GND. Table 2. Serial Input Decode A1 A0 DAC UPDATED 0 0 DACA 0 1 DACB 1 0 DACC 1 1 DACD POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS110B – JANUARY 1995 – REVISED APRIL 1997 CLK tsu(DATA-CLK) tsu(LOAD-CLK) tv(DATA-CLK) DATA A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0 tsu(CLK-LOAD) tw(LOAD) LOAD DAC Update Figure 1. LOAD-Controlled Update (LDAC = Low) CLK tsu(DATA-CLK) tv(DATA-CLK) DATA A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0 tsu(LOAD-LDAC) LOAD tw(LDAC) LDAC DAC Update Figure 2. LDAC-Controlled Update 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CLK Low CLK DATA ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ A1 A0 ÎÎÎÎ ÎÎÎÎ RNG D7 D6 D5 D4 D3 ÎÎÎÎ ÎÎÎÎ D2 D1 D0 D2 D1 D0 LOAD LDAC Figure 3. Load Controlled Update Using 8-Bit Serial Word (LDAC = Low) CLK DATA ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ A1 A0 ÎÎÎ ÎÎÎ RNG D7 D6 D5 D4 D3 ÎÎÎÎÎ ÎÎÎÎÎ LOAD LDAC Figure 4. LDAC Controlled Update Using 8-Bit Serial Word SLAS110B – JANUARY 1995 – REVISED APRIL 1997 5 TLV5620C, TLV5620I QUADRUPLE 8-DIGITAL-TO-ANALOG CONVERTERS POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CLK Low TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS110B – JANUARY 1995 – REVISED APRIL 1997 linearity, offset, and gain error using single-end supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output voltage may not change with the first code depending on the magnitude of the offset voltage. The output amplifier, therefore, attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 5. Output Voltage 0V DAC Code Negative Offset Figure 5. Effect of Negative Offset (Single Supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below ground. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single-supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. The code is calculated from the maximum specification for the negative offset. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS110B – JANUARY 1995 – REVISED APRIL 1997 equivalent inputs and outputs INPUT CIRCUIT OUTPUT CIRCUIT VDD VDD Input from Decoded DAC Register String Vref Input _ + DAC Voltage Output ×1 84 kΩ Output Range × 2 Select To DAC Resistor String ISINK 60 µA Typical 84 kΩ GND GND absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD – GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to VDD + 0.3 V Reference input voltage range, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5620C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV5620I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions Supply voltage, VDD High-level input voltage, VIH MIN NOM MAX UNIT 2.7 3.3 5.25 V 0.8 VDD Low-level input voltage, VIL V 0.8 Reference voltage, Vref [A|B|C|D], x1 gain VDD – 1.5 V V Load resistance, RL 10 kΩ Setup time, data input, tsu(DATA-CLK) (see Figures 1 and 2) 50 ns Valid time, data input valid after CLK↓, tv(DATA-CLK) (see Figures 1 and 2) 50 ns Setup time, CLK eleventh falling edge to LOAD, tsu(CLK-LOAD) (see Figure 1) 50 ns Setup time, LOAD↑ to CLK↓, tsu(LOAD-CLK) (see Figure 1) 50 ns Pulse duration, LOAD, tw(LOAD) (see Figure 1) 250 ns Pulse duration, LDAC, tw(LDAC) (see Figure 2) 250 ns 0 ns Setup time, LOAD↑ to LDAC↓, tsu(LOAD-LDAC) (see Figure 2) CLK frequency Operating free-air free air temperature, temperature TA 1 TLV5620C TLV5620I POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 70 – 40 85 MHz °C 7 TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS110B – JANUARY 1995 – REVISED APRIL 1997 electrical characteristics over recommended operating free-air temperature range, VDD = 3 V to 3.6 V, Vref = 2 V, × 1 gain output range (unless otherwise noted) PARAMETER IIH IIL High-level input current IO(sink) IO(source) Output sink current Ci TEST CONDITIONS Low-level input current Each DAC output Output source current Linearity error (end point corrected) EZS Zero-scale error Zero-scale error temperature coefficient Full-scale error Full-scale error temperature coefficient Power-supply sensitivity ± 10 µA µA VDD = 3.3 V VDD = 3.3 V, Vref = 1.5 V Vref = 1.25 V, × 2 gain, See Note 1 Vref = 1.25 V, × 2 gain, See Note 2 Vref = 1.25 V, × 2 gain, See Note 3 Differential linearity error µA mA 15 Reference input current UNIT ± 10 1 15 EL ED MAX 20 Reference input capacitance Supply current PSRR TYP Input capacitance IDD Iref EFS MIN VI = VDD VI = 0 V pF 2 0 mA ± 10 µA ±1 LSB ± 0.9 LSB 30 mV Vref = 1.25 V, × 2 gain, See Note 4 Vref = 1.25 V, × 2 gain, See Note 5 10 µV/°C Vref = 1.25 V, × 2 gain, See Note 6 See Notes 7 and 8 ± 25 µV/°C 0.5 mV/V ± 60 mV NOTES: 1. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects of zero code and full-scale errors). 2. Differential nonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 4. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(Tmax) – ZSE(Tmin)]/Vref × 106/(Tmax – Tmin). 5. Full-scale error is the deviation from the ideal full-scale output (Vref – 1 LSB) with an output load of 10 kΩ. 6. Full-scale error temperature coefficient is given by: FSETC = [FSE(Tmax) – FSE (Tmin)]/Vref × 106/(Tmax – Tmin). 7. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the VDD voltage from 4.5 V to 5.5 V dc and measuring the effect of this signal on the zero-code output voltage. 8. Full-scale error rejection ratio (FSE-RR) is measured by varing the VDD voltage from 3 V to 3.6 V dc and measuring the effect of this signal on the full-scale output voltage. operating characteristics over recommended operating free-air temperature range, VDD = 3 V to 3.6 V, Vref = 2 V, × 1 gain output range (unless otherwise noted) TEST CONDITIONS Output slew rate CL = 100 pF RL = 10 kΩ Output settling time To ± 0.5 LSB, CL = 100 pF, Large-signal bandwidth Digital crosstalk MIN TYP MAX UNIT 1 V/µs 10 µs Measured at – 3 dB point 100 kHz CLK = 1-MHz square wave measured at DACA-DACD – 50 dB Reference feedthrough See Note 10 – 60 dB Channel-to-channel isolation See Note 11 – 60 dB Reference input bandwidth See Note 12 100 kHz RL = 10 kΩ, See Note 9 NOTES: 9. Settling time is the time between a LOAD falling edge and the DAC output reaching full-scale voltage within ± 0.5 LSB starting from an initial output voltage equal to zero. 10. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a Vref input = 1 V dc + 1 VPP at 10 kHz. 11. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex with Vref input = 1 V dc + 1 VPP at 10 kHz. 12. Reference bandwidth is the –3 dB bandwidth with an input at Vref = 1.25 V dc + 2 VPP and with a digital input code of full-scale. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS110B – JANUARY 1995 – REVISED APRIL 1997 PARAMETER MEASUREMENT INFORMATION TLV5620 DACA DACB DACC DACD 10 kΩ CL = 100 pF Figure 6. Slew, Settling Time, and Linearity Measurements TYPICAL CHARACTERISTICS NEGATIVE FALL TIME AND SETTLING TIME 3 3 2.5 2.5 2 2 VO – Output Voltage – V VO – Output Voltage – V POSITIVE RISE TIME AND SETTLING TIME 1.5 1 VDD = 3 V TA = 25°C Code 00 to FF Hex Range = ×2 Vref = 1.25 V (see Note A) 0.5 0 – 0.5 VDD = 3 V TA = 25°C Code FF to 00 Hex Range = ×2 Vref = 1.25 V (see Note A) 1.5 1 0.5 0 – 0.5 –1 –1 0 2 4 6 8 10 12 14 16 18 20 0 2 Time – µs 4 6 8 10 12 14 16 18 20 Time – µs NOTE A: Rise time = 2.05 µs, positive slew rate = 0.96 V/µs, settling time = 4.5 µs. NOTE A: Fall time = 4.25 µs, negative slew rate = 0.46 V/µs, settling time = 8.5 µs. Figure 7 Figure 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS110B – JANUARY 1995 – REVISED APRIL 1997 TYPICAL CHARACTERISTICS DAC OUTPUT VOLTAGE vs OUTPUT LOAD DAC OUTPUT VOLTAGE vs OUTPUT LOAD 1.6 3 1.4 VO – DAC Output Voltage – V VO – DAC Output Voltage – V 2.8 2.6 2.4 2.2 2 1.8 1.6 VDD = 3 V, Vref = 1.5 V, Range = 2x 1.4 1.2 1 0.8 0.6 0.4 VDD = 3 V, Vref = 1.5 V, Range = 1x 0.2 1.2 0 1 0 10 20 30 40 50 60 70 80 RL – Output Load – kΩ 0 90 100 10 20 30 40 Figure 10 SUPPLY CURRENT vs TEMPERATURE 1.2 Range = × 2 Input Code = 255 VDD = 3 V Vref = 1.25 V 1.15 I DD – Supply Current – mA 60 1.1 1.05 1 0.95 0.9 0.85 0.8 – 50 70 RL – Output Load – kΩ Figure 9 0 50 t – Temperature – °C Figure 11 10 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 100 80 90 100 TLV5620C, TLV5620I QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS SLAS110B – JANUARY 1995 – REVISED APRIL 1997 APPLICATION INFORMATION _ TLV5620 DACA DACB DACC DACD + VO R NOTE A: Resistor R w 10 kΩ Figure 12. Output Buffering Scheme POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TLV5620CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLV5620C TLV5620CDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLV5620C TLV5620CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLV5620C TLV5620CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 TLV5620C TLV5620CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TLV5620CN TLV5620CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 TLV5620CN TLV5620ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5620I TLV5620IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5620I TLV5620IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5620I TLV5620IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 TLV5620I TLV5620IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TLV5620IN TLV5620INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 TLV5620IN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLV5620IDR Package Package Pins Type Drawing SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 9.0 2.1 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV5620IDR SOIC D 14 2500 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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