MICROCHIP TC9400

TC9400/9401/9402
Voltage-to-Frequency/Frequency-to-Voltage Converters
Features
General Description
VOLTAGE-TO-FREQUENCY
The TC9400/TC9401/TC9402 are low cost voltage-tofrequency (V/F) converters, utilizing low power CMOS
technology. The converters accept a variable analog
input signal and generate an output pulse train, whose
frequency is linearly proportional to the input voltage.
• Choice of Linearity
- TC9401: 0.01%
- TC9400: 0.05%
- TC9402: 0.25%
• DC to 100kHz (F/V) or 1Hz to 100kHz (V/F)
• Low Power Dissipation: 27mW (Typ.)
• Single/Dual Supply Operation
- +8V to +15V or ±4V to ±7.5V
• Gain Temperature Stability: ±25 ppm/°C (Typ.)
• Programmable Scale Factor
14-Pin Plastic DIP/CERDIP
• Operation: DC to 100kHz
• Choice of Linearity
- TC9401: 0.02%
- TC9400: 0.05%
- TC9402: 0.25%
• Programmable Scale Factor
IBIAS 1
IIN 3
VSS 4
VREF OUT 5
µP Data Acquisition
13-bit Analog-to-Digital Converters
Analog Data Transmission and Recording
Phase Locked Loops
Frequency Meters/Tachometer
Motor Control
FM Demodulation
Device Selection Table
Linearity
(V/F)
TC9400COD
0.05%
Package
14-Pin SOIC
(Narrow)
14 VDD
ZERO ADJ 2
Applications
Part
Number
A complete V/F or F/V system only requires the addition of two capacitors, three resistors, and reference
voltage.
Package Type
FREQUENCY-TO-VOLTAGE
•
•
•
•
•
•
•
The devices can also be used as highly accurate frequency-to-voltage (F/V) converters, accepting virtually
any input frequency waveform and providing a linearly
proportional voltage output.
Temperature
Range
0°C to +70°C
13 NC
12 AMPLIFIER OUT
TC9400
TC9401
TC9402
THRESHOLD
11 DETECTOR
10 FREQ/2 OUT
GND 6
9 OUTPUT COMMON
VREF 7
8 PULSE FREQ OUT
14-Pin SOIC
IBIAS
1
14
VDD
ZERO ADJ
2
13
NC
IIN
3
12
AMPLIFIER OUT
11
THRESHOLD
DETECTOR
10
FREQ/2 OUT
VSS
4
VREF OUT
5
TC9400
TC9401
TC9402
TC9400CPD
0.05%
14-Pin PDIP
0°C to +70°C
GND
6
9
OUTPUT COMMON
TC9400EJD
0.05%
14-Pin CerDIP
-40°C to +85°C
VREF
TC9401CPD
0.01%
14-Pin PDIP
0°C to +70°C
7
8
PULSE FREQ OUT
TC9401EJD
0.01%
14-Pin CerDIP
-40°C to +85°C
TC9402CPD
0.25%
14-Pin PDIP
0°C to +70°C
TC9402EJD
0.25%
14-Pin CerDIP
°C to +85°C
 2002 Microchip Technology Inc.
NC = No Internal Connection
DS21483B-page 1
TC9400/9401/9402
Functional Block Diagram
Integrator
Capacitor
Input
Voltage
Integrator
Op Amp
Threshold
Detector
One
Shot
RIN
IIN
Pulse Output
÷2
Reference
Capacitor
Pulse/2 Output
TC9400
IREF
Reference
Voltage
DS21483B-page 2
 2002 Microchip Technology Inc.
TC9400/9401/9402
1.0
ELECTRICAL
CHARACTERISTICS
*Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. These
are stress ratings only and functional operation of the device
at these or any other conditions above those indicated in the
operation sections of the specifications is not implied.
Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
Absolute Maximum Ratings*
VDD – VSS ........................................................... +18V
IIN ........................................................................ 10mA
VOUTMAX – VOUT Common...................................... 23V
VREF – VSS ..........................................................-1.5V
Storage Temperature Range .............. -65°C to +150°C
Operating Temperature Range:
C Device ........................................... 0°C to +70°C
E Device......................................... -40°C to +85°C
Package Dissipation (TA ≤ 70°C):
8-Pin CerDIP .............................................. 800mW
8-Pin Plastic DIP ........................................ 730mW
8-Pin SOIC ................................................. 470mW
TC940X ELECTRICAL SPECIFICATIONS
Electrical Characteristics: VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100kΩ, Full Scale = 10kHz, unless otherwise
specified. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device).
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
Test Conditions
Voltage-to-Frequency
Accuracy
TC9400
TC9401
TC9402
Linearity 10kHz
—
0.01
0.05
—
0.004
0.01
—
0.05
0.25
%
Output Deviation from
Full Scale Straight Line Between
Normalized Zero and
Full Scale Input
Linearity 100kHz
—
0.1
0.25
—
0.04
0.08
—
0.25
0.5
%
Output Deviation from
Full Scale Straight Line Between
Normalized Zero Reading and Full Scale Input
Gain Temperature
Drift (Note 1)
—
±25
±40
—
±25
±40
—
±50
±100
ppm/°C Variation in Gain A due
Full Scale to Temperature Change
Gain Variance
—
±10
—
—
±10
—
—
±10
—
% of
Nominal
Zero Offset
(Note 2)
—
±10
±50
—
±10
±50
—
±20
±100
mV
Correction at Zero
Adjust for Zero Output
when Input is Zero
Zero Temperature
Drift (Note 1)
—
±25
±50
—
±25
±50
—
±50
±100
µV/°C
Variation in Zero Offset
Due to Temperature
Change
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
Variation from Ideal
Accuracy
Full temperature range; not tested.
IIN = 0.
Full temperature range, IOUT = 10mA.
IOUT = 10µA.
Threshold Detect = 5V, Amp Out = 0V, full temperature range.
10Hz to 100kHz; not tested.
5µsec minimum positive pulse width and 0.5µsec minimum negative pulse width.
tR = tF = 20nsec.
RL ≥ 2kΩ, tested @ 10kΩ.
Full temperature range, VIN = -0.1V.
 2002 Microchip Technology Inc.
DS21483B-page 3
TC9400/9401/9402
TC940X ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100kΩ, Full Scale = 10kHz, unless otherwise
specified. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device).
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
Test Conditions
IIN Full Scale
—
10
—
—
10
—
—
10
—
µA
Full Scale Analog Input
Current to achieve
Specified Accuracy
IIN Over Range
—
—
50
—
—
50
—
—
50
µA
Over Range Current
Response Time
—
2
—
—
2
—
—
2
—
Cycle
Settling Time to 0.1%
Full Scale
Analog Input
Digital Section
TC9400
TC9401
TC9402
VSAT @ IOL = 10mA
—
0.2
0.4
—
0.2
0.4
—
0.2
0.4
V
Logic "0" Output
Voltage (Note 3)
VOUTMAX – VOUT
Common (Note 4)
—
—
18
—
—
18
—
—
18
V
Voltage Range
Between Output and
Common
Pulse Frequency
Output Width
—
3
—
—
3
—
—
3
—
µsec
Frequency-to-Voltage
Supply Current
IDD Quiescent
(Note 5)
—
1.5
6
—
1.5
6
—
3
10
mA
Current Required from
Positive Supply during
Operation
ISS Quiescent
(Note 5)
—
-1.5
-6
—
-1.5
-6
—
-3
-10
mA
Current Required from
Negative Supply during
Operation
VDD Supply
4
—
7.5
4
—
7.5
4
—
7.5
V
Operating Range of
Positive Supply
VSS Supply
-4
—
-7.5
-4
—
-7.5
-4
—
-7.5
V
Operating Range of
Negative Supply
-2.5
—
—
-2.5
—
—
-2.5
—
—
V
Range of Voltage
Reference Input
Non-Linearity
(Note 10)
—
0.02
0.05
—
0.01
0.02
—
0.05
0.25
Input Frequency
Range
(Notes 7 and 8)
10
—
100k
10
—
100k
10
—
100k
Reference Voltage
VREF – VSS
Accuracy
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
%
Deviation from ideal
Full Scale Transfer Function as a
Percentage Full Scale
Voltage
Hz
Frequency Range for
Specified Non-Linearity
Full temperature range; not tested.
IIN = 0.
Full temperature range, IOUT = 10mA.
IOUT = 10µA.
Threshold Detect = 5V, Amp Out = 0V, full temperature range.
10Hz to 100kHz; not tested.
5µsec minimum positive pulse width and 0.5µsec minimum negative pulse width.
tR = tF = 20nsec.
RL ≥ 2kΩ, tested @ 10kΩ.
Full temperature range, VIN = -0.1V.
DS21483B-page 4
 2002 Microchip Technology Inc.
TC9400/9401/9402
TC940X ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100kΩ, Full Scale = 10kHz, unless otherwise
specified. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device).
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
Test Conditions
Positive Excursion
0.4
—
VDD
0.4
—
VDD
0.4
—
VDD
V
Voltage Required to
Turn Threshold
Detector On
Negative Excursion
-0.4
-2
-0.4
—
-2
-0.4
—
-2
V
Voltage Required to
Turn Threshold
Detector Off
Frequency Input
Minimum Positive
Pulse Width
(Note 8)
—
5
—
—
5
—
—
5
—
µsec
Time between
Threshold Crossings
Minimum Negative
Pulse Width
(Note 8)
—
0.5
—
—
0.5
—
—
0.5
—
µsec
Time Between
Threshold Crossings
Input Impedance
—
10
—
—
10
—
—
10
MΩ
Analog Outputs
TC9400
TC9401
TC9402
Output Voltage
(Note 9)
—
VDD – 1
—
—
VDD – 1
—
—
VDD – 1
—
V
Output Loading
2
—
—
2
—
—
2
—
—
kΩ
Resistive Loading at
Output of Op Amp
Supply Current
TC9400
TC9401
IDD Quiescent
(Note 10)
—
1.5
6
ISS Quiescent
(Note 10)
—
-1.5
-6
VDD Supply
4
—
7.5
VSS Supply
-4
—
-2.5
—
—
Voltage Range of Op
Amp Output for Specified Non-Linearity
TC9402
1.5
6
—
3
10
mA
Current Required from
Positive Supply During
Operation
-1.5
-6
—
-3
-10
mA
Current Required from
Negative Supply
During Operation
4
—
7.5
4
—
7.5
V
Operating Range of
Positive Supply
-7.5
-4
—
-7.5
-4
—
-7.5
V
Operating Range of
Negative Supply
—
-2.5
—
—
-2.5
—
—
V
Range of Voltage
Reference Input
Reference Voltage
VREF – VSS
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
Full temperature range; not tested.
IIN = 0.
Full temperature range, IOUT = 10mA.
IOUT = 10µA.
Threshold Detect = 5V, Amp Out = 0V, full temperature range.
10Hz to 100kHz; not tested.
5µsec minimum positive pulse width and 0.5µsec minimum negative pulse width.
tR = tF = 20nsec.
RL ≥ 2kΩ, tested @ 10kΩ.
Full temperature range, VIN = -0.1V.
 2002 Microchip Technology Inc.
DS21483B-page 5
TC9400/9401/9402
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Pin No.
14-Pin PDIP/CERDIP
14-Pin SOIC (Narrow)
Symbol
1
IBIAS
2
ZERO ADJ
3
IIN
Description
This pin sets bias current in the TC9400. Connect to VSS through a 100kΩ resistor.
Low frequency adjustment input.
Input current connection for the V/F converter.
Negative power supply voltage connection, typically -5V.
4
VSS
5
VREF OUT
6
GND
Analog ground.
7
VREF
Voltage reference input, typically -5V.
8
PULSE FREQ
OUT
9
OUTPUT
COMMON
10
FREQ/2 OUT
This open drain output is a square wave at one-half the frequency of the pulse output
(Pin 8). Output transitions of this pin occur on the rising edge of Pin 8.
11
THRESHOLD
DETECTOR
Input to the Threshold Detector. This pin is the frequency input during F/V operation.
12
Reference capacitor connection.
Frequency output. This open drain output will pulse LOW each time the Freq.
Threshold Detector limit is reached. The pulse rate is proportional to input voltage.
Source connection for the open drain output FETs.
AMPLIFIER OUT Output of the integrator amplifier.
13
NC
No internal connection.
14
VDD
Positive power supply connection, typically +5V.
DS21483B-page 6
 2002 Microchip Technology Inc.
TC9400/9401/9402
3.0
DETAILED DESCRIPTION
3.1
Voltage-to-Frequency (V/F) Circuit
Description
input is balanced out by fixed charges from the reference voltage. As the input voltage is increased, the
number of reference pulses required to maintain balance increases, which causes the output frequency to
also increase. Since each charge increment is fixed, the
increase in frequency with voltage is linear. In addition,
the accuracy of the output pulse width does not directly
affect the linearity of the V/F. The pulse must simply be
long enough for full charge transfer to take place.
The TC9400 V/F converter operates on the principal of
charge balancing. The operation of the TC9400 is easily understood by referring to Figure 3-1. The input voltage (VIN) is converted to a current (IIN) by the input
resistor. This current is then converted to a charge on
the integrating capacitor and shows up as a linearly
decreasing voltage at the output of the Op Amp. The
lower limit of the output swing is set by the threshold
detector, which causes the reference voltage to be
applied to the reference capacitor for a time period long
enough to charge the capacitor to the reference voltage. This action reduces the charge on the integrating
capacitor by a fixed amount (q = CREF x VREF), causing
the Op Amp output to step up a finite amount.
The TC9400 contains a "self-start" circuit to ensure the
V/F converter always operates properly when power is
first applied. In the event that, during power-on, the Op
Amp output is below the threshold and CREF is already
charged, a positive voltage step will not occur. The Op
Amp output will continue to decrease until it crosses the
-3.0V threshold of the "self-start" comparator. When
this happens, an internal resistor is connected to the
Op Amp input, which forces the output to go positive
until the TC9400 is in its Normal Operating mode.
At the end of the charging period, CREF is shorted out.
This dissipates the charge stored on the reference
capacitor, so that when the output again crosses zero,
the system is ready to recycle. In this manner, the continued discharging of the integrating capacitor by the
FIGURE 3-1:
The TC9400 utilizes low power CMOS processing for
low input bias and offset currents, with very low power
dissipation. The open drain N-channel output FETs
provide high voltage and high current sink capability.
10Hz TO 10kHz V/F CONVERTER
+5V
+5V
14
VDD
Threshold
11 Detect
RL
10kΩ
FOUT 8
3µsec
Delay
+5V
Threshold
Detector
FOUT/2 10
SelfStart
÷2
RL
10kΩ
9
-3V
Output
Common
12 AMP OUT
5 VREF OUT
CINT
820pF
RIN
1MΩ
INPUT
VIN
0V –10V
+5V
20kΩ
CREF
180pF
3 IIN
510kΩ
50kΩ
Zero Adjust
2
60pF
–
Op Amp
+
IBIAS
-5V
Offset
Adjust
TC9400
TC9401
TC9402
12pF
10kΩ
1
VSS
VREF
4
7
RBIAS
100kΩ
GND
6
Reference Voltage
(Typically -5V)
-5V
 2002 Microchip Technology Inc.
DS21483B-page 7
TC9400/9401/9402
3.2
Voltage-to-Time Measurements
The TC9400 output can be measured in the time
domain as well as the frequency domain. Some microcomputers, for example, have extensive timing capability, but limited counter capability. Also, the response
time of a time domain measurement is only the period
between two output pulses, while the frequency measurement must accumulate pulses during the entire
counter time-base period.
Time measurements can be made from either the
TC9400's PULSE FREQ OUT output, or from the
FREQ/2 OUT output. The FREQ/2 OUT output
changes state on the rising edge of PULSE FREQ
OUT, so FREQ/2 OUT is a symmetrical square wave at
one-half the pulse output frequency. Timing measurements can, therefore, be made between successive
PULSE FREQ OUT pulses, or while FREQ/2 OUT is
high (or low).
4.0
PIN FUNCTIONS
4.1
Threshold Detector Input
In the V/F mode, this input is connected to the AMPLIFIER OUT output (Pin 12) and triggers a 3µsec pulse
when the input voltage passes through its threshold. In
the F/V mode, the input frequency is applied to this
input.
The nominal threshold of the detector is half way
between the power supplies, or (VDD + VSS)/2 ±400mV.
The TC9400's charge balancing V/F technique is not
dependent on a precision comparator threshold,
because the threshold only sets the lower limit of the
Op Amp output. The Op Amp's peak-to-peak output
swing, which determines the frequency, is only
influenced by external capacitors and by V REF.
4.2
Pulse Freq Out
This output is an open drain N-channel FET, which provides a pulse waveform whose frequency is proportional to the input voltage. This output requires a pullup resistor and interfaces directly with MOS, CMOS,
and TTL logic (see Figure 4-1).
FIGURE 4-1:
OUTPUT WAVEFORMS
3µsec
Typ.
FOUT
1/f
FOUT/2
VREF
Amp Out
CREF
CINT
0V
Notes: 1. To adjust FMIN, set VIN = 10mV and adjust the 50kΩ offset for 10Hz output.
2. To adjust FMAX, set VIN = 10V and adjust RIN or VREF for 10kHz output.
3. To increase FOUTMAX to 100kHz, change CREF to 2pF and CINT to 75pF.
4. For high performance applications, use high stability components for RIN, CREF, VREF (metal film
resistors and glass capacitors). Also, separate output ground (Pin 9) from input ground (Pin 6).
DS21483B-page 8
 2002 Microchip Technology Inc.
TC9400/9401/9402
4.3
Freq/2 Out
This output is an open drain N-channel FET, which provides a square wave one-half the frequency of the
pulse frequency output. The FREQ/2 OUT output will
change state on the rising edge of PULSE FREQ OUT.
This output requires a pull-up resistor and interfaces
directly with MOS, CMOS, and TTL logic.
4.4
Output Common
The sources of both the FREQ/2 OUT and the PULSE
FREQ OUT are connected to this pin. An output level
swing from the drain voltage to ground, or to the V SS
supply, may be obtained by connecting this pin to the
appropriate point.
4.5
R BIAS
An external resistor, connected to V SS, sets the bias
point for the TC9400. Specifications for the TC9400 are
based on RBIAS = 100kΩ ±10%, unless otherwise
noted.
Increasing the maximum frequency of the TC9400
beyond 100kHz is limited by the pulse width of the
pulse output (typically 3µsec). Reducing RBIAS will
decrease the pulse width and increase the maximum
operating frequency, but linearity errors will also
increase. RBIAS can be reduced to 20kΩ, which will
typically produce a maximum full scale frequency of
500kHz.
4.6
Amplifier Out
This pin is the output stage of the operational amplifier.
During V/F operation, a negative going ramp signal is
available at this pin. In the F/V mode, a voltage
proportional to the frequency input is generated.
4.7
4.8
IIN
The inverting input of the operational amplifier and the
summing junction when connected in the V/F mode. An
input current of 10µA is specified, but an over range
current up to 50µA can be used without detrimental
effect to the circuit operation. IIN connects the summing
junction of an operational amplifier. Voltage sources
cannot be attached directly, but must be buffered by
external resistors.
4.9
VREF
A reference voltage from either a precision source, or
the VSS supply is applied to this pin. Accuracy of the
TC9400 is dependent on the voltage regulation and
temperature characteristics of the reference circuitry.
Since the TC9400 is a charge balancing V/F converter,
the reference current will be equal to the input current.
For this reason, the DC impedance of the reference
voltage source must be kept low enough to prevent linearity errors. For linearity of 0.01%, a reference impedance of 200W or less is recommended. A 0.1µF bypass
capacitor should be connected from VREF to ground.
4.10
VREF Out
The charging current for CREF is supplied through this
pin. When the Op Amp output reaches the threshold
level, this pin is internally connected to the reference
voltage and a charge, equal to VREF x CREF, is removed
from the integrator capacitor. After about 3µsec, this pin
is internally connected to the summing junction of the
Op Amp to discharge CREF. Break-before-make switching ensures that the reference voltage is not directly
applied to the summing junction.
Zero Adjust
This pin is the non-inverting input of the operational
amplifier. The low frequency set point is determined by
adjusting the voltage at this pin.
 2002 Microchip Technology Inc.
DS21483B-page 9
TC9400/9401/9402
5.1
VOLTAGE-TO-FREQUENCY
(V/F) CONVERTER DESIGN
INFORMATION
FIGURE 5-1:
Input/Output Relationships
VDD = +5V
VSS = -5V
RIN = 1MΩ
VIN = +10V
TA = +25°C
400
The output frequency (FOUT) is related to the analog
input voltage (VIN) by the transfer equation:
EQUATION 5-1:
Frequency Out =
RECOMMENDED
CREF VS. VREF
500
CREF (pF) +12pF
5.0
VIN
1
,x
(VREF)(VREF)
RIN
300
10kHz
200
100
100kHz
5.2
5.2.1
0
External Component Selection
R IN
The value of this component is chosen to give a full
scale input current of approximately 10µA:
EQUATION 5-2:
RIN ≅
VIN FULLSCALE
10µA
EQUATION 5-3:
RIN ≅
10V
= 1MΩ
10µA
5.2.4
5.2.2
C INT
The exact value is not critical but is related to CREF by
the relationship:
3CREF ≤ CINT ≤ 10CREF
Improved stability and linearity are obtained when
CINT ≤ 4CREF. Low leakage types are recommended,
although mica and ceramic devices can be used in
applications where their temperature limits are not
exceeded. Locate as close as possible to Pins 12
and 13.
5.2.3
C REF
The exact value is not critical and may be used to trim
the full scale frequency (see Section 7.1, Input/Output
Relationships). Glass film or air trimmer capacitors are
recommended because of their stability and low leakage. Locate as close as possible to Pins 5 and 3 (see
Figure 5-1).
DS21483B-page 10
-3
-4
VREF (V)
-5
-6
-7
VDD, VSS
Power supplies of ±5V are recommended. For high
accuracy requirements, 0.05% line and load regulation
and 0.1µF disc decoupling capacitors, located near the
pins, are recommended.
5.3
Adjustment Procedure
Figure 3-1 shows a circuit for trimming the zero location. Full scale may be trimmed by adjusting RIN, VREF,
or CREF. Recommended procedure for a 10kHz full
scale frequency is as follows:
1.
Note that the value is an approximation and the exact
relationship is defined by the transfer equation. In practice, the value of RIN typically would be trimmed to
obtain full scale frequency at VIN full scale (see
Section 5.3, Adjustment Procedure). Metal film resistors with 1% tolerance or better are recommended for
high accuracy applications because of their thermal
stability and low noise generation.
-1
-2
2.
Set VIN to 10mV and trim the zero adjust circuit
to obtain a 10Hz output frequency.
Set VIN to 10V and trim either RIN, VREF, or CREF
to obtain a 10kHz output frequency.
If adjustments are performed in this order, there should
be no interaction and they should not have to be
repeated.
5.4
Improved Single Supply V/F
Converter Operation
A TC9400, which operates from a single 12 to 15V variable power source, is shown in Figure 5-2. This circuit
uses two Zener diodes to set stable biasing levels for
the TC9400. The Zener diodes also provide the reference voltage, so the output impedance and temperature coefficient of the Zeners will directly affect power
supply rejection and temperature performance. Full
scale adjustment is accomplished by trimming the input
current. Trimming the reference voltage is not recommended for high accuracy applications unless an
Op Amp is used as a buffer, because the TC9400
requires a low impedance reference (see Section 4.9,
VREF pin description, for more information).
The circuit of Figure 5-2 will directly interface with
CMOS logic operating at 12V to 15V. TTL or 5V CMOS
logic can be accommodated by connecting the output
pull-up resistors to the +5V supply. An optoisolator can
also be used if an isolated output is required; also, see
Figure 5-3.
 2002 Microchip Technology Inc.
TC9400/9401/9402
FIGURE 5-2:
VOLTAGE TO FREQUENCY
+12 to +15V
1.2k
14
VDD
1µF
R4
100k
R1
910k
11 Threshold
Detect
12
Amp Out
CREF 5
C
CINT
D2
5.1VZ
10k
10k
REF
R3
Gain
TC9400
FOUT 8
3 IIN
2 Zero Adjust
100k
R2
910k
Input
Voltage
(0 to 10V)
6 GND
R5
91k
D1
5.1VZ
FOUT/2
0.1µ
Output
Frequency
Output 9
Common
7 V
REF
1 I
Rp
Offset
20k
10
BIAS
VSS
100k
Digital
Ground
4
Analog Ground
Component Selection
CREF
CINT
F/S FREQ.
2200pF 4700pF
1kHz
180pF
470pF
10kHz
27pF
75pF
100kHz
FIGURE 5-3:
FIXED VOLTAGE - SINGLE SUPPLY OPERATION
V+ = 8V to 15V (Fixed)
R2
14
V2
0.9
R1
Gain
Adjust
Offset
Adjust
RIN
1MΩ
8
8.2
kΩ
0.01
µF
2
kΩ
7
VREF
0.01 11
µF
0.2
R1
FOUT
TC9400
10kΩ
10
FOUT/2
12
5
820
pF
180
pF 3
IIN
VIN
0V–10V
10kΩ
2
6
5V
IIN
1
4
9
100kΩ
V+
10V
12V
15V
R1
R2
1MΩ
1.4MΩ
2MΩ
10kΩ
14kΩ
20kΩ
FOUT = IIN
IIN =
 2002 Microchip Technology Inc.
1
(V2 – V7) (CREF)
(VIN – V2)
RIN
+
(V+ – V2)
(0.9R1 + 0.2R1)
DS21483B-page 11
TC9400/9401/9402
6.0
FREQUENCY-TO-VOLTAGE
(F/V) CIRCUIT DESCRIPTION
CINT can be increased to lower the ripple. Values of 1µF
to 100µF are perfectly acceptable for low frequencies.
When used as an F/V converter, the TC9400 generates
an output voltage linearly proportional to the input
frequency waveform.
Each zero crossing at the threshold detector's input
causes a precise amount of charge (q = CREF ∞ VREF)
to be dispensed into the Op Amp's summing junction.
This charge, in turn, flows through the feedback resistor, generating voltage pulses at the output of the Op
Amp. A capacitor (C INT) across R INT averages these
pulses into a DC voltage, which is linearly proportional
to the input frequency.
7.0
7.1
F/V CONVERTER DESIGN
INFORMATION
Input/Output Relationships
The output voltage is related to the input frequency
(FIN) by the transfer equation:
EQUATION 7-1:
VOUT = [V REF C REF RINT] FIN
The response time to a change in FIN is equal to (RINT
CINT). The amount of ripple on VOUT is inversely
proportional to CINT and the input frequency.
FIGURE 7-1:
When the TC9400 is used in the Single Supply mode,
VREF is defined as the voltage difference between Pin 7
and Pin 2.
7.2
Input Voltage Levels
The input frequency is applied to the Threshold Detector input (Pin 11). As discussed in the V/F circuit section
of this data sheet, the threshold of Pin 11 is approximately (VDD + VSS)/2 ±400mV. Pin 11's input voltage
range extends from VDD to about 2.5V below the threshold. If the voltage on Pin 11 goes more than 2.5 volts
below the threshold, the V/F mode start-up comparator
will turn on and corrupt the output voltage. The Threshold Detector input has about 200mV of hysteresis.
In ±5V applications, the input voltage levels for the
TC9400 are ±400mV, minimum. If the frequency
source being measured is unipolar, such as TTL or
CMOS operating from a +5V source, then an AC coupled level shifter should be used. One such circuit is
shown in Figure 7-1(a).
The level shifter circuit in Figure 7-1(b) can be used in
single supply F/V applications. The resistor divider
ensures that the input threshold will track the supply
voltages. The diode clamp prevents the input from
going far enough in the negative direction to turn on the
start-up comparator. The diode's forward voltage
decreases by 2.1mV/°C, so for high ambient temperature operation, two diodes in series are recommended;
also, see Figure 7-2.
FREQUENCY INPUT LEVEL SHIFTER
+8V to +5V
+5V
14
14
VDD
VDD
10k
TC9400
TC9400
Frequency
Input
33k
+5V
0.01µF
11
IN914
Frequency
Input
DET
+5V
1.0M
33k
0.01µF
11
IN914
DET
1.0M
0V
0V
GND
VSS
6
4
0.1µF
10k
VSS
4
-5V
(a) ±5V Supply
DS21483B-page 12
(b) Single Supply
 2002 Microchip Technology Inc.
TC9400/9401/9402
FIGURE 7-2:
F/V SINGLE SUPPLY F/V CONVERTER
V+ = 10V to 15V
14
10k
VDD
6 GND
TC9400
.01µF
6.2V
10k
VREF OUT 5
500k
2 Zero
Adjust
100k
47pF
IIN 3
V+
Offset
Adjust
33k
Frequency
Input
1M
1.0k
0.01µF
11 DET
GND
IN914
0.1µF
.001µF
Amp Out 12
1.0M
IBIAS
VOUT
6
VREF VSS
7
4
1.0k
100k
Note: The output is referenced to Pin 6, which is at 6.2V (Vz). For frequency meter applications,
a 1mA meter with a series scaling resistor can be placed across Pins 6 and 12.
7.3
Input Buffer
FOUT and FOUT/2 are not used in the F/V mode. However, these outputs may be useful for some applications, such as a buffer to feed additional circuitry. Then,
FOUT will follow the input frequency waveform, except
that FOUT will go high 3µsec after FIN goes high;
FOUT/2 will be square wave with a frequency of
one-half FOUT.
If these outputs are not used, Pins 8, 9 and 10 should be
connected to ground (see Figure 7-3 and Figure 7-4).
 2002 Microchip Technology Inc.
FIGURE 7-3:
0.5µsec
Min
F/V DIGITAL OUTPUTS
5.0µsec
Min
Input
FOUT
Delay = 3µsec
FOUT/2
DS21483B-page 13
TC9400/9401/9402
FIGURE 7-4:
DC - 10kHz CONVERTER
+5V
V+
14
VDD
TC9400A
TC9401A
TC9402A
"Frequency
Input Level
Shifter"
FIN
Threshold
Detect 11
42
V+
Output
Common 9 *
*
FOUT 8
3µsec
Delay
*Optional/If
Buffer is Needed
Threshold
Detector
VREF
OUT
5
12pF
Offset
Adjust
IIN 3
+5V
100kΩ
2kΩ
2 Zero Adjust
2.2kΩ
60pF
–
Op
Amp
+
IBIAS
VSS
1
4
VREF
Amp
Out 12
CREF
56pF
RINT
1MΩ
CINT
1000pF
+
See
Figure 7-1:
*
FOUT/2 10
VOUT
GND
6
7
10kΩ
VREF
(Typically -5V)
-5V
7.4
Output Filtering
The output of the TC9400 has a sawtooth ripple superimposed on a DC level. The ripple will be rejected if the
TC9400 output is converted to a digital value by an integrating analog-to-digital converter, such as the TC7107
or TC7109. The ripple can also be reduced by increasing the value of the integrating capacitor, although this
will reduce the response time of the F/V converter.
The sawtooth ripple on the output of an F/V can be
eliminated without affecting the F/V's response time by
using the circuit in Figure 7-5. The circuit is a capacitance multiplier, where the output coupling capacitor is
multiplied by the AC gain of the Op Amp. A moderately
fast Op Amp, such as the TL071, should be used.
FIGURE 7-5:
RIPPLE FILTER
VREF OUT 5
47pF
TC9400
IIN 3
1M
AMP OUT 12
.001µF
200
.01µF 1M
GND
6
0.1µF
+5
2
3
1M
–
+
7
VOUT
6
TL071
4
-5
DS21483B-page 14
 2002 Microchip Technology Inc.
TC9400/9401/9402
8.0
F/V POWER-ON RESET
In some cases, however, the TC9400 output must be
zero at power-on without a frequency input. In such
cases, a capacitor connected from Pin 11 to VDD will
usually be sufficient to pulse the TC9400 and provide a
Power-on Reset (see Figure 8-1 (a) and (b)). Where
predictable power-on operation is critical, a more complicated circuit, such as Figure 8-1 (b), may be
required.
In F/V mode, the TC9400 output voltage will occasionally be at its maximum value when power is first
applied. This condition remains until the first pulse is
applied to FIN. In most frequency measurement applications, this is not a problem because proper operation
begins as soon as the frequency input is applied.
FIGURE 8-1:
POWER-ON OPERATION/RESET
(a)
(b)
VDD
VDD
14
1000pF
FIN
1kΩ
3
11
Threshold
Detector
 2002 Microchip Technology Inc.
1µF
5
2
B
R
1
C
CLRA
100kΩ
CD4538
4
TC9400
16
VCC
Q
6
To TC9400
A
VSS
8
FIN
DS21483B-page 15
TC9400/9401/9402
9.0
PACKAGE INFORMATION
9.1
Package Marking Information
Package marking data is not available at this time.
9.2
Taping Form
Component Taping Orientation for 14-Pin SOIC (Narrow) Devices
User Direction of Feed
PIN 1
W
P
Standard Reel Component Orientation
for TR Suffix Device
Carrier Tape, Reel Size, and Number of Components Per Reel
Package
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
12 mm
8 mm
2500
13 in
14-Pin SOIC (N)
9.3
Package Dimensions
14-Pin CDIP (Narrow)
PIN 1
.300 (7.62)
.230 (5.84)
.098 (2.49) MAX.
.030 (0.76) MIN.
.780 (19.81)
.740 (18.80)
.320 (8.13)
.290 (7.37)
.040 (1.02)
.020 (0.51)
.200 (5.08)
.160 (4.06)
.200 (5.08)
.125 (3.18)
.150 (3.81)
MIN.
.110 (2.79)
.090 (2.29)
.065 (1.65)
.045 (1.14)
.020 (0.51)
.016 (0.41)
.015 (0.38)
.008 (0.20)
3° MIN.
.400 (10.16)
.320 (8.13)
Dimensions: inches (mm)
DS21483B-page 16
 2002 Microchip Technology Inc.
TC9400/9401/9402
9.3
Package Dimensions (Continued)
14-Pin PDIP (Narrow)
PIN 1
.260 (6.60)
.240 (6.10)
.310 (7.87)
.290 (7.37)
.770 (19.56)
.745 (18.92)
.200 (5.08)
.140 (3.56)
.040 (1.02)
.020 (0.51)
.150 (3.81)
.115 (2.92)
.015 (0.38)
.008 (0.20)
3° MIN.
.400 (10.16)
.310 (7.87)
.110 (2.79)
.090 (2.29)
.070 (1.78)
.045 (1.14)
.022 (0.56)
.015 (0.38)
Dimensions: inches (mm)
14-Pin SOIC (Narrow)
PIN 1
.157 (3.99) .244 (6.20)
.150 (3.81) .228 (5.79)
.050 (1.27) TYP.
.344 (8.74)
.337 (8.56)
.069 (1.75)
.053 (1.35)
.018 (0.46)
.014 (0.36)
.010 (0.25)
.004 (0.10)
.010 (0.25)
.007 (0.18)
8° MAX.
.050 (1.27)
.016 (0.40)
Dimensions: inches (mm)
 2002 Microchip Technology Inc.
DS21483B-page 17
TC9400/9401/9402
SALES AND SUPPORT
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
DS21483B-page 18
 2002 Microchip Technology Inc.
TC9400/9401/9402
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro ® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
 2002 Microchip Technology Inc.
DS21483B-page 19
WORLDWIDE SALES AND SERVICE
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03/01/02
*DS21483B*
DS21483B-page 20
 2002 Microchip Technology Inc.