MICROCHIP TC514CPJ

TC500/A/510/514
Precision Analog Front Ends
Package Types
Features
• Precision (up to 17-bits) A/D Converter "Front End"
• 3-Pin Control Interface to Microprocessor
• Flexible: User Can Trade-off Conversion Speed
for Resolution
• Single Supply Operation (TC510/TC514)
• 4 Input, Differential Analog MUX (TC514)
• Automatic Input Voltage Polarity Detection
• Low Power Dissipation:
- (TC500/TC500A): 10mΩ
- (TC510/TC514): 18mΩ
• Wide Analog Input Range: ±4.2V (TC500A/TC510)
• Directly Accepts Bipolar and Differential
Input Signals
Applications
• Precision Analog Signal Processor
• Precision Sensor Interface
• High Accuracy DC Measurements
Device Selection Table
Part
Number
Package
Temperature
Range
TC500ACOE
16-Pin SOIC (Wide)
0°C to +70°C
TC500ACPE
16-Pin PDIP (Narrow)
0°C to +70°C
TC500COE
16-Pin SOIC (Wide)
0°C to +70°C
16-Pin SOIC
16 Pin-PDIP
CINT
1
VSS
2
CAZ
3
BUF
4
ACOM
5
CREF–
6
CREF+
7
VREF
8
16 VDD
15 DGND
TC500/ 14 CMPTR OUT
TC500A
13 B
COE
TC500/ 12 A
TC500A
11 VIN+
CPE
10 VIN–
9
VREF+
24-Pin SOIC
24-Pin PDIP
VOUT-
1
24 CAP-
CINT
2
23 DGND
CAZ
3
22 CAP+
BUF
4
ACOM
5
21 VDD
20 OSC
CREF-
6
CREF+
7
TC510COG 19 CMPTR OUT
TC510CPF 18 A
VREF+
8
17 B
VREF-
9
16 VIN+
N/C 10
15 VIN-
N/C 11
14 N/C
N/C 12
13 N/C
TC500CPE
16-Pin PDIP (Narrow)
0°C to +70°C
TC510COG
24-Pin SOIC (Wide)
0°C to +70°C
TC510CPF
24-Pin PDIP (Narrow)
0°C to +70°C
VOUT-
1
28 CAP-
TC514COI
28-Pin SOIC (Wide)
0°C to +70°C
CINT
2
27 DGND
TC514CPJ
28-Pin PDIP (Narrow)
0°C to +70°C
CAZ
3
26 CAP+
BUF
4
25 VDD
ACOM
5
24 OSC
CREF-
6
23 CMPTR OUT
CREF+
7
VREF-
8
VREF+
9
20 A0
CH4- 10
19 A1
 2002 Microchip Technology Inc.
28-Pin SOIC
28-Pin PDIP
TC514COI
TC514CPJ
22 A
21 B
CH3- 11
18 CH1+
CH2- 12
CH1- 13
17 CH2+
16 CH3+
N/C 14
15 CH4+
DS21428B-page 1
TC500/A/510/514
offset voltages in the TC5XX are corrected by a closed
loop feedback mechanism. The input voltage is applied
to the integrator during the Integrate phase. This
causes an integrator output dv/dt directly proportional
to the magnitude of the input voltage. The higher the
input voltage, the greater the magnitude of the voltage
stored on the integrator during this phase. At the start
of the De-integrate phase, an external voltage reference is applied to the integrator and, at the same time,
the external host processor starts its on-board timer.
The processor maintains this state until a transition
occurs on the CMPTR output, at which time the processor halts its timer. The resulting timer count is the converted analog data. Integrator Zero (the final phase of
conversion) removes any residue remaining in the
integrator in preparation for the next conversion.
General Description
TheTC500/A/510/514 family are precision analog front
ends that implement dual slope A/D converters having
a maximum resolution of 17-bits plus sign. As a minimum, each device contains the integrator, zero crossing comparator and processor interface logic. The
TC500 is the base (16-bit max) device and requires
both positive and negative power supplies. The
TC500A is identical to the TC500 with the exception
that it has improved linearity, allowing it to operate to a
maximum resolution of 17-bits. The TC510 adds an onboard negative power supply converter for single supply operation. The TC514 adds both a negative power
supply converter and a 4 input differential analog
multiplexer.
Each device has the same processor control interface
consisting of 3 wires: control inputs (A and B) and zerocrossing comparator output (CMPTR). The processor
manipulates A, B to sequence the TC5XX through four
phases of conversion: Auto Zero, Integrate, De-integrate and Integrator Zero. During the Auto Zero phase,
The TC500/A/510/514 offer high resolution (up to 17bits), superior 50Hz/60Hz noise rejection, low power
operation, minimum I/O connections, low input bias
currents and lower cost compared to other converter
technologies having similar conversion speeds.
Typical Application
Control Logic
RINT
CINT
CREF
A0
VREF+
A1
VREF-
CREF+
CH1+
CH2+
CH3+
CH4+
CH1CH2CH3CH4-
CAZ
CREFBuffer
SWR SWR
DIF.
MUX
(TC514)
BUF
CINT
CAZ
CMPTR 1
CMPTR 2
+
–
–
+
–
+
SWRI- SWRI-
SWZ
+
VSS
OSC
TC500
TC500A
TC510
TC514
Level
Shift
CMPTR
Output
Polarity
Detection
SW1
DC-TO-DC
Converter
(TC510 & TC514)
Analog
Switch
Control
Signals
VOUT-
VSS
COUT-
Phase
Decoding
Logic
DGND
CAP- CAP+
1.0µF
DS21428B-page 2
Converter Sate
Zero Integrator Output
Auto-Zero
Signal Integrate
Deintegrate
SWIZ SWZ
SWRI+ SWRI-
ACOM
SWI
B
0
1
0
1
Integrator
-
SWI
A
0
0
1
1
1.0µF
(TC500
TC500A)
A
B
Control Logic
 2002 Microchip Technology Inc.
TC500/A/510/514
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings*
TC510/TC514 Positive Supply Voltage
(VDD to GND) ......................................... +10.5V
TC500/TC500A Supply Voltage
(VDD to V SS) .............................................. +18V
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. These are stress ratings only and functional
operation of the device at these or any other conditions
above those indicated in the operation sections of the
specifications is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may
affect device reliability.
TC500/TC500A Positive Supply Voltage
(VDD to GND) ............................................ +12V
TC500/TC500A Negative Supply Voltage
(VSS to GND)................................................-8V
Analog Input Voltage (VIN+ or VIN-) ............VDD to VSS
Logic Input Voltage...............VDD +0.3V to GND - 0.3V
Voltage on OSC:
........................... -0.3V to (VDD +0.3V) for V DD < 5.5V
Ambient Operating Temperature Range:
................................................................ 0°C to +70°C
Storage Temperature Range: ............. -65°C to +150°C
TC500/A/510/514 ELECTRICAL SPECIFICATIONS
Electrical Characteristics: TC510/TC514: VDD = +5V, TC500/TC500A: VSS = ±5V unless otherwise specified.
CAZ = CREF = 0.47µF.
Symbol
TA = +25°C
Parameter
TA = 0°C to 70°C
Unit
Test Conditions
Min
Typ
Max
Min
Typ
Max
Resolution
60
—
—
—
—
—
µV
ZSE
Zero Scale Error
with Auto Zero Phase
—
—
—
—
0.005
0.003
—
—
0.005
0.003
0.012
0.009
% F.S.
TC500/510/514
TC500A
ENL
End Point Linearity
—
—
0.005
—
0.015
0.010
—
—
0.015
0.010
0.060
0.045
% F.S.
% F.S.
TC500/510/514,
Note 1, Note 2,
TC500A
NL
Best Case Straight
Line Linearity
—
0.003
0.008
—
—
—
% F.S.
TC500/510/514,
Note 1, Note 2
—
—
0.005
—
—
—
% F.S.
TC500A
Analog
Note 1
ZS TC
Zero-Scale Temp.
Coefficient
—
—
—
—
1
2
µV/°C
Over Operating
Temperature Range
SYE
Full-Scale Symmetry
Error (Roll-Over Error)
—
0.01
—
—
0.03
—
% F.S.
Note 3
FS TC
Full-Scale Temperature Coefficient
—
—
—
—
10
—
ppm/°C Over Operating
Temperature Range;
External Reference
TC = 0 ppm/°C
IIN
Input Current
—
6
—
—
—
—
pA
VIN = 0V
Note 1: Integrate time ≥ 66msec, auto zero time ≥ 66msec, VINT (peak) ≈ 4V.
2: End point linearity at ±1/4, ±1 /2, ±3/4 F.S. after full-scale adjustment.
3: Roll-over error is related to C INT, CREF, C AZ characteristics.
 2002 Microchip Technology Inc.
DS21428B-page 3
TC500/A/510/514
TC500/A/510/514 ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: TC510/TC514: VDD = +5V, TC500/TC500A: VSS = ±5V unless otherwise specified.
CAZ = CREF = 0.47µF.
Symbol
TA = +25°C
Parameter
Min
Typ
Common Mode
Voltage Range
VSS +1.5
—
Integrator Output
Swing
VSS +0.9
Analog Input SignalRange
TA = 0°C to 70°C
Max
Min
Unit
Test Conditions
Typ
Max
VDD – 1.5 VSS + 1.5
—
VDD – 1.5
V
—
VDD – 0.9
VSS +0.9
—
VSS +0.9
V
VSS +1.5
—
VDD – 1.5 VSS +1.5
—
VSS +1.5
V
ACOM = GND = 0V
VSS +1
—
VDD – 1
VSS +1
—
VDD – 1
V
VREF - VREF+
Analog (Continued)
VCMR
VREF
Voltage Reference
Range
Digital
VOH
Comparator Logic 1,
Output High
4
—
—
4
—
—
V
ISOURCE = 400µA
VOL
Comparator Logic 0,
Output Low
—
—
0.4
—
—
0.4
V
ISINK = 2.1mA
VIH
Logic 1, Input High
Voltage
3.5
—
—
3.5
—
—
V
VIL
Logic 0, Input Low
Voltage
—
—
1
—
—
1
V
IL
Logic Input Current
—
—
—
—
0.3
tD
Comparator Delay
—
2
—
—
3
—
µsec
-2.5
—
2.5
-2.5
—
2.5
V
VDD = 5V
—
6
10
—
—
—
kΩ
VDD = 5V
µA
Logic 1 or 0
Multiplexer (TC514 Only)
Maximum Input
Voltage
RDSON
Drain/Source ON
Resistance
Power (TC510/TC514 Only)
IS
Supply Current
—
1.8
2.4
—
—
3.5
mA
VDD = 5V, A = 1, B = 1
PD
Power Dissipation
—
18
—
—
—
—
mW
VDD = 5V
VDD
Positive Supply Operating Voltage Range
4.5
—
5.5
4.5
—
5.5
V
ROUT
Operating Source
Resistance
—
60
85
—
—
100
Ω
Oscillator Frequency
—
100
—
—
—
—
kHz
(Note 3)
Maximum Current Out
—
—
-10
—
—
-10
mA
VDD = 5V
—
1
1.5
—
—
2.5
mA
VS = ±5V, A = B = 1
VDD = 5V, VSS = -5V
IOUT
IOUT = 10mA
Power (TC500/TC500A Only)
IS
Supply Current
PD
Power Dissipation
—
10
—
—
—
—
mW
VDD
Positive Supply Operating Range
4.5
—
7.5
4.5
—
7.5
V
VSS
Negative Supply
Operating Range
-4.5
—
-7.5
- 4.5
—
-7.5
V
Note 1: Integrate time ≥ 66msec, auto zero time ≥ 66msec, VINT (peak) ≈ 4V.
2: End point linearity at ±1/4, ±1 /2, ±3/4 F.S. after full-scale adjustment.
3: Roll-over error is related to C INT, CREF, C AZ characteristics.
DS21428B-page 4
 2002 Microchip Technology Inc.
TC500/A/510/514
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Pin Number
(TC500,
TC500A)
1
2
PIN FUNCTION TABLE
Pin
Number
(TC510)
Pin
Number
(TC514)
Symbol
2
2
CINT
Integrator output. Integrator capacitor connection.
VSS
Negative power supply input (TC500/TC500A only).
Not Used Not Used
Description
3
3
3
CAZ
Auto Zero input. The Auto Zero capacitor connection.
4
4
4
BUF
Buffer output. The Integrator capacitor connection.
5
5
5
ACOM
6
6
6
CREF-
Input. Negative reference capacitor connection.
7
7
7
CREF+
Input. Positive reference capacitor connection.
8
8
8
VREF-
Input. External voltage reference (-) connection.
This pin is grounded in most applications. It is recommended that ACOM and the
input common pin (Ven- or CHn-) be within the analog common mode range (CMR).
9
9
9
VREF+
10
15
Not Used
VIN-
Negative analog input.
Input. External voltage reference (+) connection.
Positive analog input.
11
16
Not Used
VIN +
12
18
22
A
Input. Converter phase control MSB. (See input B.)
13
17
21
B
Input. Converter phase control LSB. The states of A, B place the TC5XX in one of
four required phases. A conversion is complete when all four phases have been
executed:
Phase control input pins: AB = 00: Integrator Zero
01: Auto Zero
10: Integrate
11: De-integrate
14
19
23
CMPTR Zero crossing comparator output. CMPTR is HIGH during the Integration phase
OUT
when a positive input voltage is being integrated and is LOW when a negative input
voltage is being integrated. A HIGH-to-LOW transition on CMPTR signals the processor that the De-integrate phase is completed. CMPTR is undefined during the
Auto Zero phase. It should be monitored to time the Integrator Zero phase.
15
23
27
DGND
16
21
25
VDD
22
26
CAP+
24
28
CAP-
Input. Negative power supply converter capacitor (-) connection.
1
1
VOUT-
Output. Negative power supply converter output and reservoir capacitor connection.
This output can be used to power other devices in the circuit requiring a negative
bias voltage.
20
24
OSC
Oscillator control input. The negative power supply converter normally runs at a frequency of 100kHz. The converter oscillator frequency can be slowed down
(to reduce quiescent current) by connecting an external capacitor between this pin
and VDD (see Section 9.0, Typical Characteristics Curves).
18
CH1+
Positive analog input pin. MUX channel 1.
13
CH1-
Negative analog input pin. MUX channel 1.
17
CH2+
Positive analog input pin. MUX channel 2.
12
CH2-
Negative analog input pin. MUX channel 2.
16
CH3+
Positive analog input pin. MUX channel 3.
11
CH3-
Negative analog input pin. MUX channel 3.
15
CH4+
Positive analog input pin. MUX channel 4.
10
CH4-
Negative analog input pin. MUX channel 4
20
A0
Multiplexer input channel select input LSB (see A1).
19
A1
Multiplexer input channel select input MSB.
Phase control input pins: A1, A0 = 00 = Channel 1
01 = Channel 2
10 = Channel 3
11 = Channel 4
 2002 Microchip Technology Inc.
Input. Digital ground.
Input. Power supply positive connection.
Input. Negative power supply converter capacitor (+) connection.
DS21428B-page 5
TC500/A/510/514
DETAILED DESCRIPTION
3.1
Dual Slope Conversion Principles
Actual data conversion is accomplished in two phases:
input signal Integration and reference voltage
De-integration.
The integrator output is initialized to 0V prior to the start
of Integration. During Integration, analog switch S1
connects VIN to the integrator input where it is maintained for a fixed time period (TINT). The application of
VIN causes the integrator output to depart 0V at a rate
determined by the magnitude of VIN and a direction
determined by the polarity of VIN. The De-integration
phase is initiated immediately at the expiration of TINT.
During De-integration, S1 connects a reference voltage
(having a polarity opposite that of VIN) to the integrator
input. At the same time, an external precision timer is
started. The De-integration phase is maintained until
the comparator output changes state, indicating the
integrator has returned to its starting point of 0V. When
this occurs, the precision timer is stopped. The De-integration time period (TDEINT), as measured by the precision timer, is directly proportional to the magnitude of
the applied input voltage (see Figure 3-3).
A simple mathematical equation relates the Input Signal, Reference Voltage and Integration time:
the integration period are, theoretically, completely
removed, since the average value of a sine wave of
frequency (1/T) averaged over a period (T) is zero.
Integrating converters often establish the integration
period to reject 50/60Hz line frequency interference
signals. The ability to reject such signals is shown by a
normal mode rejection plot (Figure 3-1). Normal mode
rejection is limited in practice to 50 to 65dB, since the
line frequency can deviate by a few tenths of a percent
(Figure 3-2).
FIGURE 3-1:
Normal Mode Rejection (dB)
3.0
INTEGRATING
CONVERTER NORMAL
MODE REJECTION
30
T = Measurment
Period
20
10
0
0.1/T
1/T
Input Frequency
10/T
EQUATION 3-1:
TINT
V
T
1
∫
VIN(T)DT = REF DEINT
RINTCINT 0
RINTCINT
FIGURE 3-2:
LINE FREQUENCY
DEVIATION
Where:
VREF = Reference Voltage
TINT = Signal Integration time (fixed)
tDEINT = Reference Voltage Integration time (variable)
For a constant VIN:
EQUATION 3-2:
TDEINT
VIN = V REF
TINT
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle.
Normal Mode Rejeciton (dB)
80
70
t = 0.1 sec
60
50
40
30
DEV
SIN 60 p t (1 ± 100 )
60 p t (1 ± DEV)
100
DEV = Deviation from 60Hz
t = Integration Period
Normal Mode = 20 LOG
REJECTION
20
0.01
0.1
1.0
Line Frequency Deviation from 60 Hz (%)
An inherent benefit is noise immunity. Input noise
spikes are integrated (averaged to zero) during the
integration periods. Integrating ADCs are immune to
the large conversion errors that plague successive
approximation converters in high noise environments.
Integrating converters provide inherent noise rejection
with at least a 20dB/decade attenuation rate. Interference signals with frequencies at integral multiples of
DS21428B-page 6
 2002 Microchip Technology Inc.
TC500/A/510/514
FIGURE 3-3:
BASIC DUAL SLOPE CONVERTER
CINT
RINT
Analog
Input (VIN)
TC510
Integrator
–
VINT
–
Comparator
+
CMPTR Out
+
S1
±
REF
VOLTAGE
Switch Driver
Phase
Control
Control
Logic
Polarity Control
Integrator
Output
A
VIN ≈ VREF
VIN ≈ 1/2 VREF
TINT
VSUPPLY
VINT
B
I/O
Microcomputer
ROM
Timer
RAM
Counter
TDEINT
 2002 Microchip Technology Inc.
DS21428B-page 7
TC500/A/510/514
4.0
TC500/A/510/514 CONVERTER
OPERATION
The internal analog switch status for each of these
phases is summarized in Table 4-1. This table
references the Typical Application.
The TC500/A/510/514 incorporates an Auto Zero and
Integrator phase in addition to the input signal Integrate
and reference De-integrate phases. The addition of
these phases reduce system errors, calibration steps
and shorten overrange recovery time. A typical measurement cycle uses all four phases in the following
order:
1.
2.
3.
4.
Auto Zero
Input signal integration
Reference deintegration
Integrator output zero
TABLE 4-1:
INTERNAL ANALOG GATE STATUS
Conversion Phase
SWI
SWR+
SWR-
Auto Zero (A = 0, B = 1)
Input Signal Integration (A = 1, B = 0)
SWIZ
Closed
Closed
Closed
Closed
*Assumes a positive polarity input signal. SW–RI would be closed for a negative input signal.
Auto Zero Phase (AZ)
During this phase, errors due to buffer, integrator and
comparator offset voltages are nulled out by charging
CAZ (auto zero capacitor) with a compensating error
voltage.
The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The
internal input points connect to analog common. The
reference capacitor is charged to the reference voltage
potential through SWR. A feedback loop, closed around
the integrator and comparator, charges the C AZ capacitor with a voltage to compensate for buffer amplifier,
integrator and comparator offset voltages.
4.2
SW1
Closed
Closed*
Integrator Output Zero (A = 0, B = 0)
4.1
SWR
Closed
Closed
Reference Voltage De-integration
(A =1, B = 1)
Note:
SWZ
Closed
Analog Input Signal Integration
Phase (INT)
The TC5XX integrates the differential voltage between
the (V IN+) and (VIN–) inputs. The differential voltage
must be within the device's Common mode range
VCMR. The input signal polarity is normally checked via
software at the end of this phase: CMPTR = 1 for
positive polarity; CMPTR = 0 for negative polarity.
DS21428B-page 8
4.3
Reference Voltage De-integration
Phase (DINT)
The previously charged reference capacitor is connected with the proper polarity to ramp the integrator
output back to zero. An externally-provided, precision
timer is used to measure the duration of this phase.
The resulting time measurement is proportional to the
magnitude of the applied input voltage.
4.4
Integrator Output Zero Phase (IZ)
This phase ensures the integrator output is at 0V when
the Auto Zero phase is entered and that only system
offset voltages are compensated. This phase is used at
the end of the reference voltage de-integration phase
and MUST be used for ALL TC5XX applications having
resolutions of 12-bits or more. If this phase is not used,
the value of the Auto Zero capacitor (CAZ) must be
about 2 to 3 times the value of the Integration capacitor
(CINT) to reduce the effects of charge sharing. The Integrator Output Zero phase should be programmed to
operate until the output of the comparator returns
"HIGH". The overall timing system is shown in
Figure 4-1.
 2002 Microchip Technology Inc.
TC500/A/510/514
FIGURE 4-1:
TYPICAL DUAL SLOPE A/D CONVERTER SYSTEM TIMING
TTIME
Converter Status
Auto-Zero
Integrate
Full Scale Input
Reference
De-integrate
Overshoot Integrator
Output
Zero
Integrator 0
Voltage VINT
Comparator Delay
Comparator
Output
A
Undefined
0 For Negative Input
1 For Postive Input
A=1
A=0
A=1
B=1
B=0
B=1
B=0
Time Input
Integration
Phase
Capture
De-integration
Time
Integrator
Output
Zero Phase
Complete
A=0
AB Inputs
B
Controller
Operation
Begin Conversion with
Auto-Zero Phase
Ready for Next
Conversion
(Auto-Zero is
Idle State)
Sample Input Polarity
Typically = TINT
TINT
(Positive Input Shown)
Comparator Delay +
Processor Latency
Minimizing
Overshoot
will Minimize
I.O.Z. Time
Notes: The length of this phase is chosen almost arbitrarily
but needs to be long enough to null out worst case errors
(see text).
 2002 Microchip Technology Inc.
DS21428B-page 9
TC500/A/510/514
5.0
ANALOG SECTION
5.1
Differential Inputs (VIN+, VIN–)
The difference in reference for (+) or (-) input voltages
will cause a rollover error. This error can be minimized
by using a large reference capacitor in comparison to
the stray capacitance.
The TC5XX operates with differential voltages within
the input amplifier Common mode range. The amplifier
Common mode range extends from 1.5V below positive supply to 1.5V above negative supply. Within this
Common mode voltage range, Common mode rejection is typically 80dB. Full accuracy is maintained, however, when the inputs are no less than 1.5V from either
supply.
5.4
Phase Control Inputs (A, B)
The A, B unlatched logic inputs select the TC5XX operating phase. The A, B inputs are normally driven by a
microprocessor I/O port or external logic.
5.5
Comparator Output
The integrator output also follows the Common mode
voltage. The integrator output must not be allowed to
saturate. A worst case condition exists, for example,
when a large, positive Common mode voltage, with a
near full scale negative differential input voltage, is
applied. The negative input signal drives the integrator
positive when most of its swing has been used up by
the positive Common mode voltage. For these critical
applications, the integrator swing can be reduced. The
integrator output can swing within 0.9V of either supply
without loss of linearity.
By monitoring the comparator output during the fixed
signal integrate time, the input signal polarity can be
determined by the microprocessor controlling the
conversion. The comparator output is HIGH for positive
signals and LOW for negative signals during the signal
integrate phase (see Figure 5-1).
5.2
The internal comparator delay is 2µsec, typically.
Figure 5-1 shows the comparator output for large
positive and negative signal inputs. For signal inputs at
or near zero volts, however, the integrator swing is very
small. If Common mode noise is present, the comparator can switch several times during the beginning of the
signal integrate period. To ensure that the polarity
reading is correct, the comparator output should be
read and stored at the end of the signal integrate
phase.
Analog Common
Analog common is used as VIN return during system
zero and reference de-integrate. If VIN– is different from
analog common, a Common mode voltage exists in the
system. This signal is rejected by the excellent CMR of
the converter. In most applications, VIN– will be set at a
fixed known voltage (i.e., power supply common). A
Common mode voltage will exist when VIN– is not
connected to analog common.
5.3
Differential Reference
(VREF+, VREF–)
The reference voltage can be anywhere within 1V of
the power supply voltage of the converter. Rollover
error is caused by the reference capacitor losing or
gaining charge due to stray capacitance on its nodes.
FIGURE 5-1:
During the reference de-integrate phase, the comparator output will make a HIGH-to-LOW transition as the
integrator output ramp crosses zero. The transition is
used to signal the processor that the conversion is
complete.
The comparator output is undefined during the Auto
Zero phase and is used to time the Integrator Output
Zero phase. (See Section 7.6, Integrator Output Zero
Phase).
COMPARATOR OUTPUT
Signal
Integrate
Reference
Deintegrate
Signal
Integrate
Reference
De-integrate
Integrator
Output
Zero
Crossing
Integrator
Output
Zero
Crossing
Comparator
Output
Comparator
Output
A. Positive Input Signal
DS21428B-page 10
B. Negative Input Signal
 2002 Microchip Technology Inc.
TC500/A/510/514
6.0
TYPICAL APPLICATIONS
TABLE 6-1:
6.1
Component Value Selection
Conversions
Per Second
The procedure outlined below allows the user to arrive
at values for the following TC5XX design variables:
1.
2.
3.
4.
Integration Phase Timing
Integrator Timing Components (RINT, CINT)
Auto Zero and Reference Capacitors
Voltage Reference
6.2
6.3
DINT and IZ Phase Timing
The duration of the DINT phase is a function of the
amount of voltage stored on the integrator during TINT
and the value of VREF. The DINT phase must be initiated immediately following INT and terminated when
an integrator output zero-crossing is detected. In general, the maximum number of counts chosen for DINT
is twice that of INT (with VREF chosen at VIN(MAX) /2).
6.4
The value of RINT is therefore directly calculated in the
following equation:
EQUATION 6-1:
RINT(in MΩ) =
0.1
0.22
SMR5 224K50J02L4
2 or less
0.47
SMR5 474K50J04L4
Note:
6.6
Calculate Integrating Capacitor
(CINT)
The integrating capacitor must be selected to maximize
integrator output voltage swing. The integrator output
voltage swing is defined as the absolute value of VDD
(or VSS) less 0.9V (i.e., IVDD - 0.9VI or IVSS + 0.9VI).
Using the 20µA buffer maximum output current, the
value of the integrating capacitor is calculated using the
following equation.
EQUATION 6-2:
(TINT) (20 x 10 -6)
CINT =
VS = IVDDI or IVSSI, whichever is less (TC500/A
VS = IVDDI (TC510, TC514)
It is critical that the integrating capacitor has a very low
dielectric absorption. Polypropylene capacitors are an
example of one such dielectic. Polyester and Polybicarbonate capacitors may also be used in less critical
applications. Table 6-2 summarizes recommended
capacitors for CINT.
20
RECOMMENDED CAPACITOR
FOR CINT
Value
VIN(MAX) = Maximum input voltage (full count voltage)
RINT = Integrating Resistor (in MΩ)
CREF and C AZ must be low leakage capacitors (such as
polypropylene). The slower the conversion rate, the
larger the value C REF must be. Recommended capacitors for CREF and CAZ are shown in Table 6-1. Larger
values for CAZ and C REF may also be used to limit
rollover errors.
 2002 Microchip Technology Inc.
µF
TINT = Integration Period
TABLE 6-2:
Select Reference (CREF) and Auto
Zero (C AZ) Capacitors
(VS - 0.9)
Where:
Where:
6.5
SMR5 104K50J01L4
Manufactured by Evox-Rifa, Inc.
VIN(MAX)
For loop stability, RINT should be ≥ 50kΩ.
Suggested* Part
Number
>7
Calculate Integrating Resistor
(RINT)
The desired full scale input voltage and amplifier output
current capability determine the value of RINT. The
buffer and integrator amplifiers each have a full-scale
current of 20µA.
Typical Value of
CREF, CAZ (µF)
2 to 7
Select Integration Time
Integration time must be picked as a multiple of the
period of the line frequency. For example, TINT times of
33msec, 66msec and 132msec maximize 60Hz line
rejection.
CREF AND C AZ SELECTION
Note:
6.7
Suggested Part Number*
0.1
SMR5 104K50J01L4
0.22
SMR5 224K50J02L4
0.33
SMR5 334K50J03L4
0.47
SMR5 474K50J04L4
Manufactured by Evox-Rifa, Inc.
Calculate VREF
The reference deintegration voltage is calculated using
the following equation:
EQUATION 6-3:
VREF =
(VS – 0.9) (CINT) (RINT)
2(RINT)
V
DS21428B-page 11
TC500/A/510/514
7.0
DESIGN CONSIDERATIONS
7.4
7.1
Noise
The length of this phase is constant from one conversion to the next and depends on system parameters
and component value selections. The calculation of
TINT is shown elsewhere in this data sheet. At some
point near the end of this phase, the microcontroller
should sample CMPTR to determine the input signal
polarity. This value is, in effect, the Sign Bit for the overall conversion result. Optimally, CMPTR should be
sampled just before this phase is terminated by changing AB from 10 to 11. The consideration here is that,
during the initial stage of input integration when the
integrator voltage is low, the comparator may be
affected by noise and its output unreliable. Once integration is well underway, the comparator will be in a
defined state.
The threshold noise (NTH) is the algebraic sum of the
integrator noise and the comparator noise. This value
is typically 30µV. Figure 7-1 shows how the value of the
reference voltage can affect the final count. Such errors
can be reduced by increased integration times, in the
same way that 50/60Hz noise is rejected. The signalto-noise ratio is related to the integration time (TINT)
and the integration time constant (RINT) (CINT) as follows:
EQUATION 7-1:
S/N (dB) = 20 Log
7.2
V
( 30 xIN10–
6
•
tINT
(RINT) • (CINT)
)
System Timing
To obtain maximum performance from the TC5XX, the
overshoot at the end of the De-integration phase must
be minimized. Also, the Integrator Output Zero phase
must be terminated as soon as the comparator output
returns high. (See Figure 4-1).
Figure 4-1 shows the overall timing for a typical system
in which a TC5XX is interfaced to a microcontroller. The
microcontroller drives the A, B inputs with I/O lines and
monitors the comparator output, CMPTR, using an I/O
line or dedicated timer capture control pin. It may be
necessary to monitor the state of the CMPTR output in
addition to having it control a timer directly for the Reference De-integration phase. (This is further explained
below.)
7.5
Input Signal Integrate Phase
Reference De-integration
The length of this phase must be precisely measured
from the transition of AB from 10 to 11 to the falling
edge of CMPTR. The comparator delay contributes
some error in timing this phase. The typical delay is
specified to be 2µsec. This should be considered in the
context of the length of a single count when
determining overall system performance and possible
single count errors. Additionally, Overshoot will result in
charge accumulating on the integrator after its output
crosses zero. This charge must be nulled during the
Integrator Output Zero phase.
The timing diagram in Figure 4-1 is not to scale, as the
timing in a real system depends on many system
parameters and component value selections. There
are four critical timing events (as shown in Figure 4-1):
sampling the input polarity; capturing the de-integration
time; minimizing overshoot and properly executing the
Integrator Output Zero phase.
7.3
Auto Zero Phase
The length of this phase is usually set to be equal to the
Input Signal Integration time. This decision is virtually
arbitrary since the magnitudes of the various system
errors are not known. Setting the Auto Zero time equal
to the Input Integrate time should be more than
adequate to null out system errors. The system may
remain in this phase indefinitely (i.e., Auto Zero is the
appropriate Idle state for a TC5XX device).
DS21428B-page 12
 2002 Microchip Technology Inc.
TC500/A/510/514
FIGURE 7-1:
NOISE THRESHOLD
S
S
S
30 µV
NTH
NTH
Slope (S) =
VREF
N = Noise Threshold
RINT CINT TH
Integrator Output Zero Phase
The comparator delay and the controller's response
latency may result in overshoot, causing charge
buildup on the integrator at the end of a conversion.
This charge must be removed or performance will
degrade. The Integrator Output Zero phase should be
activated (AB = 00) until CMPTR goes high. It is absolutely critical that this phase be terminated immediately
so that Overshoot is not allowed to occur in the opposite direction. At this point, it can be assured that the
integrator is near zero. Auto Zero should be entered
(AB = 01) and the TC5XX held in this state until the next
cycle is begun (see Figure 7-2).
FIGURE 7-2:
OVERSHOOT
Integrator
Output
Zero
Crossing
7.7
7.7.1
Overshoot
Comparator
Output Comp
Using the TC510/TC514
NEGATIVE SUPPLY VOLTAGE
CONVERTER (TC510, TC514)
A capacitive charge pump is employed to invert the voltage on VDD for negative bias within the TC510/TC514.
This voltage is also available on the VOUT- pin to provide
negative bias elsewhere in the system. Two external
capacitors are required to perform the conversion.
Timing is generated by an internal state machine driven
from an on-board oscillator. During the first phase,
capacitor CF is switched across the power supply and
charged to VS+. This charge is transferred to capacitor
COUT- during the second phase. The oscillator normally
runs at 100kHz to ensure minimum output ripple. This
frequency can be reduced by placing a capacitor from
OSC to VDD. The relationship between the capacitor
value is shown in Section 9.0.
7.7.2
Integrate
Phase
High VREF
Normal VREF
LowREF
7.6
NTH
ANALOG INPUT MULTIPLEXER
(TC514)
The TC514 is equipped with a four input differential
analog multiplexer. Input channels are selected using
select inputs (A1, A0). These are high-true control signals (i.e., channel 0 is selected when (A1, A0 = 00).
De-integrate Phase
Integrator
Zero Phase
 2002 Microchip Technology Inc.
DS21428B-page 13
TC500/A/510/514
8.0
DESIGN EXAMPLE
(SEE FIGURES 8-1 TO 8-4)
Given: Required Resolution: (16 Bits (65,536
counts).
Maximum V IN: ±2V
Power Supply Voltage: +5V
60Hz System
Step 1: Pick integration time (tINT) as a multiple of the
line frequency:
1/60Hz = 16.6msec. Use 4x line frequency
= 66msec
Step 2: Calculate RINT
RINT = VIN(MAX) /20µA 2 /20µA = 100kΩ
Step 3: Calculate CINT for maximum (4V) integrator
output swing:
C INT = (tINT) (20 x 10 –6) / (V S - 0.9)
= (.066) (20 x 10 –6) / (4.1)
= .32µF (use closest value: 0.33µF)
Note:
Microchip recommended capacitor:
Evox-Rifa p/n: 5MR5 334K50J03L4.
Step 4: Choose CREF and C AZ based on conversion
rate:
Conversions/sec:
= 1/(TAZ + TINT + 2 TINT + 2msec)
= 1/(66msec +66msec
+132msec +2msec)
= 3.7 conversions/sec
From which CAZ = CREF = 0.22µF
(see Table 6-1)
Note:
Microchip recommended capacitor:
Evox-Rifa p/n: 5MR5 224K50J02L4
Step 5: Calculate V REF
EQUATION 8-1:
VREF =
(V S - 0.9) (C INT) (RINT)
2(TINT)
= (4.1) (0.33 x 1 –6) (105) / 2(.066)
= 1.025V
DS21428B-page 14
 2002 Microchip Technology Inc.
TC500/A/510/514
FIGURE 8-1:
TC510 DESIGN SAMPLE
1
1µF
CINT
0.33µF
2
CAZ
0.22µF
3
4
+5V
RINT
100k
CREF
R2 0.22µF
10k
1µF
7
R3, 10k
C1
0.01µF
FIGURE 8-2:
DGND
CINT
TC510
CAZ
24
23
1µF
Pin 2
CAP+ 22
VDD 21
BUF
Typical Waveforms
+5V
VIN+
+5V
Pin 19
5 ACOM
6
MCP1525
CAP-
VOUT-
Microcontroller
CREF-
CMPTR
CREF+
A
19
Pin 2
18
VIN17
9 V
REF-
B
8 VREF+
VIN+ 16
INPUT+
VIN- 15
INPUT–
Pin 19
TC514 DESIGN EXAMPLE
1
CINT
1µF 0.33µF
CAZ
0.22µF
2
3
4
+5V
RINT
100k
VOUT-
CAPDGND
CINT
CAP+
CAZ
BUF
5 ACOM
TC514
VDD
A0
A1
MCP1525
10k
1µF
CREF
0.22µF
10k
C1, .01µF
6 C
REF-
CMPTR
28
27
25
19
B 21
CH1+
CH1–
Analog
Mux Logic
Microcontroller
23
9
VREF-
+5V
22
A 22
8
+5V
26
7 C
REF+
VREF+
1µF
18
13
INPUT 1+
INPUT 1–
Typical Waveforms
CH2+ 17
CH2– 12
CH3+ 16
CH3– 11
CH4+ 15
CH4– 10
INPUT 2+
PIN 2
INPUT 2–
VIN+
INPUT 3+
INPUT 3–
PIN 23
INPUT4+
INPUT4–
PIN 2
VIN
PIN 23
 2002 Microchip Technology Inc.
DS21428B-page 15
TC500/A/510/514
TC510 TO IBM® COMPATIBLE PRINTER PORT
FIGURE 8-3:
+5V
21
VDD
1
VOUT-
1µF
CAP-
24
1µF
CAP+
22
7
CREF+
0.22µF
CREF-
6
VREF+
9
MCP1525
0.01µF
VREF-
PORT
0378
HEX
BUF
2
18
3
17
10
19
1µF
10k
TC510
PC
Printer
Port
10k
8
4
A
CAZ
3
B
CINT
2
CMPTR
VIN+
16
VIN-
15
100kΩ
0.22µF
0.33µF
100kΩ
+
0.01µF
Input
–
DGND
ACOM
5
23
DS21428B-page 16
 2002 Microchip Technology Inc.
TC500/A/510/514
FIGURE 8-4:
TC514 TO IBM COMPATIBLE PRINTER PORT
+5V
25
+
18
CH1+ VDD
Input 1
–
13 CH1–
+
17
Input 2
–
+
Input 3
–
12
16
11
15
+
Input 4
–
1
CAP–
1µF
CH2+
CREF+
CH2–
IBM
Printer Port
Port
0378
Hex
19
2
22
3
21
10
23
7
MCP1525
0.22µF
CH3+
CREF-
6
10k
CH3–
VREF+ 9
CH4+
10k
TC514
0.01µF
VREF-
Analog
Mux Control Logic
10kΩ
26
CAP+
10 CH4–
20
1µF
28
–
VOUT
8
A0
A1
BUF
A
CAZ
B
CINT
4
100kΩ
3
2
0.22µF
0.33µF
CMPTR
ACOM
5
DGND
27
 2002 Microchip Technology Inc.
DS21428B-page 17
TC500/A/510/514
9.0
TYPICAL CHARACTERISTICS
The graphs and tables following this note are a statistical summary based on a limited number of samples and are
provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed.
In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified
power supply range), and therefore outside the warranted range.
Output Voltage vs. Output Current
Output Voltage vs Load Current
-0
TA = 25˚C
V+ = 5V
3
2
1
0
-1
-2
-3
-4
-5
TA = 25˚C
-1
Output Voltage (V)
Output Voltage (V)
5
4
Slope 60Ω
-2
-3
-4
-5
-6
-7
-8
0
10
20
30
40
60
50
Load Current (mA)
70
0
80
Output Source Resistance (W)
Output Ripple (mV PK-PK)
V+ = 5V, TA = 25˚C
Osc. Freq. = 100kHz
150
CAP = 1µF
125
100
75
CAP = 10µF
50
25
0
0
1
2
3
4
5
6
7
Load Current (mA)
8
9 10
6
8 10 12 14 16
Output Current (mA)
90
V+ = 5V
IOUT = 10mA
80
70
60
50
40
-50
0
25
50
Temperature (˚C)
-25
10
1
DS21428B-page 18
1000
Oscillator Frequency (kHz)
TA = +25˚C
V+ = 5V
10
100
Oscillator Capacitance (pF)
75
100
Oscillator Frequency vs. Temperature
150
1
18 20
100
Oscillator Frequency vs. Capacitance
100
Oscillator Frequency (kHz)
4
Output Source Resistance vs. Temperature
Output Ripple vs. Load Current
200
175
2
V+ = 5V
125
100
75
50
-50
-25
0
25
75
50
Temperature (˚C)
100
125
 2002 Microchip Technology Inc.
TC500/A/510/514
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
Package marking data not available at this time.
10.2
Taping Forms
Component Taping Orientation for 16-Pin SOIC (Wide) Devices
User Direction of Feed
PIN 1
W
P
Standard Reel Component Orientation
for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
16-Pin SOIC (W)
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
16 mm
12 mm
1000
13 in
Component Taping Orientation for 24-Pin SOIC (Wide) Devices
User Direction of Feed
PIN 1
W
P
Standard Reel Component Orientation
for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
24-Pin SOIC (W)
 2002 Microchip Technology Inc.
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
24 mm
12 mm
1000
13 in
DS21428B-page 19
TC500/A/510/514
10.2
Taping Forms (Continued)
Component Taping Orientation for 28-Pin SOIC (Wide) Devices
User Direction of Feed
PIN 1
W
P
Standard Reel Component Orientation
for TR Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
28-Pin SOIC (W)
DS21428B-page 20
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
24 mm
12 mm
1000
13 in
 2002 Microchip Technology Inc.
TC500/A/510/514
10.3
Package Dimensions
16-Pin PDIP (Narrow)
PIN 1
.270 (6.86)
.240 (6.10)
.045 (1.14)
.030 (0.76)
.770 (19.56)
.740 (18.80)
.310 (7.87)
.290 (7.37)
.200 (5.08)
.140 (3.56)
.040 (1.02)
.020 (0.51)
.150 (3.81)
.115 (2.92)
.014 (0.36)
.008 (0.20)
10° MAX.
.400 (10.16)
.310 (7.87)
.110 (2.79)
.090 (2.29)
.070 (1.78)
.045 (1.14)
.022 (0.56)
.015 (0.38)
Dimensions: inches (mm)
16-Pin SOIC (Narrow)
PIN 1
.157 (3.99)
.150 (3.81)
.244 (6.20)
.228 (5.79)
.050 (1.27) TYP
.394 (10.00)
.385 (9.78)
.069 (1.75)
.053 (1.35)
.018 (0.46)
.014 (0.36)
.010 (0.25)
.004 (0.10)
8°
MAX.
.010 (0.25)
.007 (0.18)
.050 (1.27)
.016 (0.40)
Dimensions: inches (mm)
 2002 Microchip Technology Inc.
DS21428B-page 21
TC500/A/510/514
10.3
Packaging Dimensions (Continued)
16-Pin SOIC (Wide)
PIN 1
.299 (7.59) .419 (10.65)
.291 (7.40) .398 (10.10)
.413 (10.49)
.398 (10.10)
.104 (2.64)
.097 (2.46)
.050 (1.27) TYP. .019 (0.48)
.014 (0.36)
8°
MAX.
.012 (0.30)
.004 (0.10)
.013 (0.33)
.009 (0.23)
.050 (1.27)
.016 (0.40)
Dimensions: inches (mm)
24-Pin PDIP (Narrow)
PIN 1
.280 (7.11)
.240 (6.10)
.045 (1.14)
.030 (0.76)
.310 (7.87)
.290 (7.37)
1.195 (30.35)
1.155 (29.34)
.200 (5.08)
.140 (3.56)
.040 (1.02)
.015 (0.38)
.150 (3.81)
.115 (2.92)
.110 (2.79)
.090 (2.29)
.070 (1.78)
.045 (1.14)
.023 (0.58)
.015 (0.38)
.015 (0.38)
.008 (0.20)
3˚ MIN.
.400 (10.16)
.310 (7.87)
Dimensions: inches (mm)
DS21428B-page 22
 2002 Microchip Technology Inc.
TC500/A/510/514
10.3
Packaging Dimensions (Continued)
24-Pin SOIC (Wide)
PIN 1
.299 (7.59) .419 (10.65)
.291 (7.40) .398 (10.10)
.615 (15.62)
.597 (15.16)
.104 (2.64)
.097 (2.46)
.050 (1.27) TYP. .019 (0.48)
.014 (0.36)
8°
MAX.
.012 (0.30)
.004 (0.10)
.013 (0.33)
.009 (0.23)
.050 (1.27)
.016 (0.40)
Dimensions: inches (mm)
28-Pin PDIP (Narrow)
PIN 1
.288 (7.32)
.240 (6.10)
.045 (1.14)
.030 (0.76)
.310 (7.87)
.290 (7.37)
1.400 (35.56)
1.345 (34.16)
.200 (5.08)
.140 (3.56)
.040 (1.02)
.015 (0.38)
.150 (3.81)
.115 (2.92)
.110 (2.79)
.090 (2.29)
.070 (1.78)
.045 (1.14)
.022 (0.56)
.015 (0.38)
.015 (0.38)
.008 (0.20)
3˚ MIN.
.400 (10.16)
.310 (7.87)
Dimensions: inches (mm)
 2002 Microchip Technology Inc.
DS21428B-page 23
TC500/A/510/514
10.3
Package Dimensions (Continued)
28-Pin SOIC (Wide)
PIN 1
.299 (7.59) .419 (10.65)
.291 (7.40) .398 (10.10)
.713 (18.11)
.697 (17.70)
.103 (2.62)
.097 (2.46)
.019 (0.48)
.014 (0.36)
.012 (0.30)
.004 (0.10)
.013 (0.33)
.009 (0.23)
8˚ MAX.
.050 (1.27)
.016 (0.40)
Dimensions: inches (mm)
DS21428B-page 24
 2002 Microchip Technology Inc.
TC500/A/510/514
SALES AND SUPPORT
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
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Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
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 2002 Microchip Technology Inc.
DS21428B-page 25
TC500/A/510/514
NOTES:
DS21428B-page 26
 2002 Microchip Technology Inc.
TC500/A/510/514
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro ® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
 2002 Microchip Technology Inc.
DS21428B-page 27
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
Japan
Corporate Office
Australia
2355 West Chandler Blvd.
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Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Microchip Technology Australia Pty Ltd
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Microchip Technology Japan K.K.
Benex S-1 6F
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Rocky Mountain
China - Beijing
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Tel: 480-792-7966 Fax: 480-792-7456
Microchip Technology Consulting (Shanghai)
Co., Ltd., Beijing Liaison Office
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
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Tel: 86-10-85282100 Fax: 86-10-85282104
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Chengdu 610016, China
Tel: 86-28-86766200 Fax: 86-28-86766599
China - Fuzhou
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Co., Ltd., Fuzhou Liaison Office
Unit 28F, World Trade Plaza
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Fuzhou 350001, China
Tel: 86-591-7503506 Fax: 86-591-7503521
China - Shanghai
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Room 701, Bldg. B
Far East International Plaza
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Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
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Co., Ltd., Shenzhen Liaison Office
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Renminnan Lu
Shenzhen 518001, China
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Microchip Technology Inc.
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San Jose, CA 95131
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New York
Toronto
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Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc.
India Liaison Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Microchip Technology Taiwan
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Denmark
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
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Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
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20041 Agrate Brianza
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Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Microchip Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
04/20/02
*DS21428B*
DS21428B-page 28
 2002 Microchip Technology Inc.