TC530/TC534 5V Precision Data Acquisition Subsystems Package Types Features 28-Pin SOIC 28-Pin PDIP • Precision (up to 17-Bits) A/D Converter • 3-Wire Serial Port • Flexible: User Can Trade Off Conversion Speed For Resolution • Single Supply Operation • -5V Output Pin • 4 Input, Differential Analog MUX (TC534) • Automatic Input Polarity and Overrange Detection • Low Operating Current: 5mA Max • Wide Analog Input Range: ±4.2V Max • Cost Effective VSS 1 28 CAP- CINT 2 27 AGND CAZ 3 26 CAP+ BUF 4 25 VDD ACOM 5 CREF- 6 24 NC VREF- 8 21 RESET VREF+ 9 VIN- 10 20 EOC 23 OSC TC530CPI CREF+ 7 TC530COI 22 VCCD 18 DIN DGND 12 17 DCLK N/C 13 16 DOUT 15 OSCIN OSCOUT 14 Applications 40-Pin PDIP • Precision Analog Signal Processor • Precision Sensor Interface • High Accuracy DC Measurements VSS 1 40 CAP- CINT 2 CAZ 3 39 AGND 38 CAP+ 37 VDD BUF 4 36 N/C ACOM 5 CREF- 6 CREF+ 7 Device Selection Table VREF- 35 N/C 34 OSC 33 N/C 8 VREF+ 9 Part Number 19 R/W VIN+ 11 Package Temperature Range 32 VCCD TC534CPL CH4- 10 31 N/C CH3- 11 30 RESET CH2- 12 29 N/C TC530COI 28-Pin SOIC 0°C to +70°C CH1- 13 28 N/C TC530CPJ 28-Pin PDIP (Narrow) 0°C to +70°C CH4+ 14 27 EOC 26 R/W TC534CKW 44-Pin PQFP 0°C to +70°C CH3+ 15 CH2+ 16 TC534CPL 40-Pin PDIP 0°C to +70°C CH1+ 17 24 DCLK DGND 18 23 DOUT 25 DIN A1 19 22 OSCIN A0 20 21 OSCOUT NC VDD AGND CAP+ CAP- NC VSS CINT CAZ BUF NC 44-Pin PQFP 44 43 42 41 40 39 38 37 36 35 34 NC 1 33 NC ACOM 2 32 OSC CREF- 3 31 NC CREF+ 4 30 VCDD VREF- 5 VREF+ 6 CH4- 7 27 NC CH3- 8 26 NC CH2- 9 25 NC 29 TC534CKW NC 28 RESET CH1- 10 24 EOC CH4+ 11 23 R/W 2002 Microchip Technology Inc. DIN DCLK DOUT OSCIN OSCOUT A0 A1 DGND CH1+ CH2+ CH3+ 12 13 14 15 16 17 18 19 20 21 22 DS21433B-page 1 TC530/TC534 new data is available. The converted data (plus Overrange and polarity bits) is held in the output shift register until read by the processor or until the next conversion is completed, allowing the user to access data at any time. General Description The TC530/TC534 are serial analog data acquisition subsystems ideal for high precision measurements (up to 17-bits plus sign). The TC530 consists of a dual slope integrating A/D converter, negative power supply generator and 3 wire serial interface port. The TC534 is identical to the TC530, but adds a four channel differential input multiplexer. Key A/D converter operating parameters (Auto Zero and Integration time) are programmable, allowing the user to trade conversion time for resolution. The TC530/TC534 timebase can be derived from an external crystal of 2MHz (max) or from an external frequency source. The TC530/TC534 requires a single 5V power supply and features a -5V, 10mA output which can be used to supply negative bias to other components in the system. Data conversion is initiated when the RESET input is brought low. After conversion, data is loaded into the output shift register and EOC is asserted, indicating Typical Application VDD CINT +5V RINT VDD (TC530 Only) VINVIN+ .01µF DIF. MUX CH3+ CH3- (TC534 Only) TC530 TC534 VREF- ACOM 0.01µF CMPTR A B EOC VDD R/W Serial Port DC-TO-DC Converter Oscillator (÷ 4) VSS OSC CAP+ CAP– Optional Power-On Reset Cap RESET State Machine CH4+ CH4- A0 A1 VREF+ INT CREF+ CREF- Dual Slope A/D Converter IN+ IN- CH2+ CH2- DS21433B-page 2 100k CREF VDD BUF CAZ CH1+ CH1- TC534 (Only) CAZ MCP1525 OSCIN DIN DOUT DCLK OSCOUT Negative Supply Output 2002 Microchip Technology Inc. TC530/TC534 1.0 ELECTRICAL CHARACTERISTICS *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* Supply Voltage ...................................................... +6V Analog Input Voltage (VIN+ or VIN-).............VDD to VSS Logic Input Voltage......... (V DD + 0.3V) to (GND - 0.3V) Ambient Operating Temperature Range: PDIP Package (C)................. 0°C to +70°C SOIC Package (C) ................ 0°C to +70°C PQFP Package (C) ............... 0°C to +70°C Storage Temperature Range .............. -65°C to +150°C TC530/TC530A/TC534 ELECTRICAL SPECIFICATIONS Electrical Characteristics: VDD = VCCD, C AZ = CREF = 0.47µF, unless otherwise specified. Symbol TA = +25°C Parameter Min Typ TA = 0°C to +70°C Max Min Typ Unit Test Conditions Max V DD Analog Power Supply Voltage 4.5 5.0 5.5 4.5 — 5.5 V VCCD Digital Power Supply Voltage 4.5 5.0 5.5 4.5 — 5.5 V PD TC530/TC534 Total Power Dissipation — — 25 — — — mΩ IS Supply Current (VS + PIN ) — 1.8 2.5 — — 3.0 mA ICCD Supply Current (VCCD PIN) — — 1.5 — — 1.7 mA FOSC = 1MHz Note 1 VDD = VCCD = 5V Analog Resolution — — ±17 — — ±17 Bits ZSE R Zero Scale Error with Auto Zero Phase — — 0.5 — 0.005 0.012 % F.S. ENL End Point Linearity — 0.015 0.030 — 0.015 0.045 % F.S. Note 1 and Note 2 NL Max. Deviation from Best Straight Line Fit — 0.008 0.015 — — — % F.S. Note 1 and Note 2 ZSTC Zero Scale Temperature Coefficient — — — — 1 2 µV/°C SYE Rollover Error — .012 — — .03 — % F.S. Note 3 FSTC Full Scale Temperature Coefficient — — — — 10 — ppm/ °C — 6 — — — — pA VCMR Common-Mode Voltage Range VSS + 1.5 — VDD - 1.5 VSS + 1.5 — VDD - 1.5 V VINT Integrator Output Swing VSS + 0.9 — VDD - 0.9 VSS + 0.9 — VDD - 0.9 V VIN Analog Input Signal Range VSS + 1.5 — VDD -1.5 VSS + 1.5 — VDD - 1.5 V VREF Voltage Reference Range VSS + 1 — VDD - 1 VDD + 1 — VDD - 1 V — 2.0 — 3.0 — µsec IIN TD Note 1: 2: 3: 4: Input Current Zero Crossing Comparator Delay — Ext. VREF T.C. = 0ppm/°C VIN = 0V Integrate time ≥ 66msec, Auto Zero time ≥ 66msec, VINT (pk) = 4V. End point linearity at ±1/4, ±1/2 ±3/4, F.S. after full scale adjustment. Rollover error is related to capacitor used for CINT. See Table 5-2, Recommended Capacitor for C INT. TC534 Only. 2002 Microchip Technology Inc. DS21433B-page 3 TC530/TC534 TC530/TC530A/TC534 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: VDD = VCCD, C AZ = CREF = 0.47µF, unless otherwise specified. Symbol TA = +25°C Parameter Min Typ TA = 0°C to +70°C Max Min Typ Unit Test Conditions Max Serial Port Interface VIH Input Logic HIGH Level 2.5 — — 2.5 — — VIL Input Logic LOW Level — — 0.8 — — 0.8 V IIN Input Current (DI, DO, DCLK) — — 10 — — — µA Logic LOW Output Voltage (EOC) — 0.2 0.3 — — 0.35 V IOUT = 250µA Rise and Fall Times (EOC, DI, DO) — — 250 — 250 nsec CL = 10pF VOL T R, T F V FXTL Crystal Frequency — — 2.0 — — 2.0 MHz FEXT External Frequency on OSCIN — — 4.0 — — 4.0 MHz — µsec TRS Read Setup Time 1 — — — 1 TRD Read Delay Time 250 — — — 250 nsec TDRS DCLK to D OUT Delay 450 — — — 450 nsec TPWL DCLK LOW Pulse Width 150 — — — 150 nsec TPWH DCLK HIGH Pulse Width 150 — — — 150 nsec TDR Data Ready Delay 200 — — — 200 nsec ROUT Output Resistance — 65 85 — — 100 Ω IOUT = 10mA FCLK Oscillator Frequency — 100 — — — — kHz COSC = 0 IOUT VSS Output Current — — 10 — — 10 mA -2.5 — 2.5 -2.5 — 2.5 V — 6 10 — — — kΩ Multiplexer VIMMAX Maximum Input Voltage RDSON Note 1: 2: 3: 4: Drain/Source ON Resistance Integrate time ≥ 66msec, Auto Zero time ≥ 66msec, VINT (pk) = 4V. End point linearity at ±1/4, ±1/2 ±3/4, F.S. after full scale adjustment. Rollover error is related to capacitor used for CINT. See Table 5-2, Recommended Capacitor for C INT. TC534 Only. DS21433B-page 4 2002 Microchip Technology Inc. TC530/TC534 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1 TABLE 2-1: PIN FUNCTION TABLE Pin Number Pin Number (TC530) (TC530) 28-Pin PDIP 28-Pin SOIC Pin Number (TC534) 40-Pin PDIP Pin Number (TC534) Symbol 44-Pin PQFP Description 1 1 1 40 VSS Analog output. Negative power supply converter output and reservoir capacitor connection. This output can be used to provide negative bias to other devices in the system. 2 2 2 41 CINT Analog output. Integrator capacitor connection and integrator output. 3 3 3 42 CAZ Analog input. Auto Zero capacitor connection. 4 4 4 43 BUF Analog output. Integrator capacitor connection and voltage buffer output. 5 5 5 2 ACOM 6 6 6 3 CREF- Analog Input. Reference cap negative connection. 7 7 7 4 CREF+ Analog Input. Reference cap positive connection. 8 8 8 5 VREF- Analog Input. External voltage reference negative connection. 9 9 9 6 VREF+ Analog Input. External voltage reference positive connection. Not Used Not Used 10 7 CH4- Analog Input. Multiplexer channel 4 negative differential Not Used Not Used 11 8 CH3- Analog Input. Multiplexer channel 3 negative differential Not Used Not Used 12 9 CH2- Analog Input. Multiplexer channel 2 negative differential Analog input. This pin is ground for all of the analog switches in the A/D converter. It is grounded for most applications. ACOM and the input common pin (VIN - or CHX-) should be within the common mode range, CMR. Not Used Not Used 13 10 CH1- Analog Input. Multiplexer channel 1 negative differential Not Used Not Used 14 11 CH4+ Analog Input. Multiplexer channel 4 positive differential Not Used Not Used 15 12 CH3+ Analog Input. Multiplexer channel 3 positive differential Not Used Not Used 16 13 CH2+ Analog Input. Multiplexer channel 2 positive differential Not Used Not Used 17 14 CH1+ Analog Input. Multiplexer channel 1 positive differential 10 10 Not Used Not Used VN- Analog Input. Negative differential analog voltage input. 11 11 Not Used Not Used VIN + Analog Input. Positive differential analog voltage input. 12 12 18 15 DGND Analog Input. Ground connection for serial port circuit. Not Used Not Used 19 16 A1 Logic Level Input. Multiplexer address MSB. Not Used Not Used 20 17 A0 Logic Level Input. Multiplexer address LSB. 14 14 21 18 15 15 22 19 2002 Microchip Technology Inc. OSCOUT Analog Input. Timebase for state machine. This pin connects to one side of an AT-cut crystal having an effective series resistance of 100Ω (typ) and a parallel capacitance of 20pF. If an external frequency source is used to clock the TC530/TC534 this pin must be left floating. OSCIN Analog Input. This pin connects to the other side of the crystal described in OSCOUT above. The TC530/TC534 may also be clocked from an external frequency source connected to this pin. The external frequency source must be a pulse wave form with a minimum 30% duty cycle and rise and fall times 15nsec (Max). If an external frequency source is used, OSCOUT must be left floating. A maximum operating frequency of 2MHz (crystal) or 4MHz (external clock source) is permitted. DS21433B-page 5 TC530/TC534 TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Number Pin Number (TC530) (TC530) 28-Pin PDIP 28-Pin SOIC Pin Number (TC534) 40-Pin PDIP Pin Number (TC534) Symbol 44-Pin PQFP Description 16 16 23 20 DOUT Logic Level Output. Serial port data output pin. This pin is enabled only when R/W is high. 17 17 24 21 DCLK Logic Input, Positive and Negative Edge Triggered. Serial port clock. When R/W is high, serial data is clocked out of the TC530/TC534A (on DOUT ) at each high-to-low transition of DCLK. A/D initialization data (LOAD VALUE) is clocked into the TC530/TC534 (on DIN ) at each low-to-high transition of DCLK. A maximum serial port DCLK frequency of 3MHz is permitted. 18 18 25 22 DIN Logic Level Input. Serial port input pin. The A/D converter integration time (TINT) and Auto Zero time (TAZ) values are determined by the LOAD VALUE byte clocked into this pin. This initialization must take place at power up, and can be rewritten (or modified and rewritten) at any time. The LOAD VALUE is clocked into DIN MSB first. 19 19 26 23 R/W Logic Level Input. This pin must be brought low to perform a write to the serial port (e.g. initialize the A/D converter). The DOUT pin of the serial port is enabled only when this pin is high. 20 20 27 24 EOC Open Drain Output. End-of-Conversion (EOC) is asserted any time the TC530/TC534 is in the AZ phase of conversion. This occurs when either the TC530/TC534 initiates a normal AZ phase or when RESET is pulled high. EOC is returned high when the TC530/TC534 exits AZ. Since EOC is driven low immediately following completion of a conversion cycle, it can be used as a DATA READY processor interrupt. 21 21 30 28 RESET Logic Level Input. It is necessary to force the TC530/TC534 into the Auto Zero phase when power is initially applied. This is accomplished by momentarily taking RESET high. Using an I/O port line from the microprocessor or by applying an external system reset signal or by connecting a 0.01µF capacitor from the RESET input to VDD. Conversions are performed continuously as long as RESET is low and conversion is halted when RESET is high. RESET may therefore be used in a complex system to momentarily suspend conversion (for example, while the address lines of an input multiplexer are changing state). In this case, RESET should be pulled high only when the EOC is LOW to avoid excessively long integrator discharge times which could result in erroneous conversion. (See Applications Section). 22 22 32 30 VCCD Analog Input. Power supply connection for digital logic and serial port. Proper power-up sequencing is critical, see the Applications section. 23 23 34 32 OSC Input. The negative power supply converter normally runs at a frequency of 100kHz. This frequency can be slowed down to reduce quiescent current by connecting an external capacitor between this pin and V+DD. See Section 6.0, Typical Characteristics. 25 25 37 35 VDD Analog Input. Power supply connection for the A/D analog section and DC-DC converter. Proper power-up sequencing is critical, (See the Applications section). DS21433B-page 6 2002 Microchip Technology Inc. TC530/TC534 TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Number Pin Number (TC530) (TC530) 28-Pin PDIP 28-Pin SOIC Pin Number (TC534) 40-Pin PDIP Pin Number (TC534) Symbol 44-Pin PQFP Description 26 26 38 36 CAP+ Analog Input. Storage capacitor positive connection for the DC/DC converter. 27 27 39 37 AGND Analog Input. Ground connection for DC/DC converter. 28 28 40 38 CAP- Analog Input. Storage capacitor negative connection for the DC/DC converter. 13, 24 13, 24 28, 29, 31, 33, 35, 36 1, 25, 26, 27, 29, 31, 33, 34, 39, 44 NC 2002 Microchip Technology Inc. No connect. Do not connect any signal to these pins. DS21433B-page 7 TC530/TC534 3.0 DETAILED DESCRIPTION 3.1 Dual Slope Integrating Converter The TC530/TC534 dual slope converter operates by integrating the input signal for a fixed time period, then applying an opposite polarity reference voltage while timing the period (counting clocks pulses) for the integrator output to cross 0V (deintegrating). The resulting count is read as conversion data. A simple mathematical expression that describes dual slope conversion is: In addition to the two phases required for dual slope measurement (Integrate and De-integrate), the TC530/ TC534 performs two additional adjustments to minimize measurement error due to system offset voltages. The resulting four internal operations (conversion phases) performed each measurement cycle are: Auto Zero (AZ), Integrator Output Zero (IZ), Input Integrate (INT) and Reference De-integrate (DINT). The AZ and IZ phases compensate for system offset errors and the INT and DINT phases perform the actual A/D conversion. FIGURE 3-1: EQUATION 3-1: EQUATION 3-2: TINT TDEINT 1 1 ∫ ∫ VREF VIN(T)DT = R INTCINT 0 RINTCINT 0 from which: EQUATION 3-3: (V IN) [ (T INT) (RINT)(CINT) ] = (VREF) [ (TDEINT) (RINT)(CINT) ] Normal Mode Rejection (dB) Integrate Voltage = De-integrate Voltage And therefore: 3.2 EQUATION 3-4: [ ] VIN = VREF TDEINT T INT where: VREF = Reference Voltage TINT = Integrate Time INTEGRATING CONVERTER NORMAL MODE REJECTION 30 T = Measurement Period 20 10 0 0.1/T 1/T Input Frequency 10/T Auto Zero Phase (AZ) This phase compensates for errors due to buffer, integrator and comparator offset voltages. During this phase, an internal feedback loop forces a compensating error voltage on auto zero capacitor (CAZ). The duration of the AZ phase is programmable via the serial port (see Section 4.1.1, AZ and INT Phase Duration). TDEINT = Reference Voltage De-integrate Time Inspection of Equation 3-4 shows dual slope converter accuracy is unrelated to integrating resistor and capacitor values, as long as they are stable throughout the measurement cycle. This measurement technique is inherently ratiometric (i.e., the ratio between the TINT and TDEINT times is equal to the ratio between VIN and VREF). Another inherent benefit is noise immunity. Input noise spikes are integrated, or averaged to zero, during the integration period. The integrating converter has a noise immunity with an attenuation rate of at least -20dB per decade. Interference signals with frequencies at integral multiples of the integration period are, for the most part, completely removed. For this reason, the integration period of the converter is often established to reject 50/ 60Hz line noise. The ability to reject such noise is shown by the plot of Figure 3-1. DS21433B-page 8 2002 Microchip Technology Inc. TC530/TC534 FIGURE 3-2: SERIAL PORT TIMING Read Timing Write Timing Write Default Timing TRS R/W R/W TRD R/W TLS EOC TLDL DIN DIN TDLS TPWL DOUT TDRS TPWL TLDS DCLK DCLK Read Format R/W EOC DOUT EOC OVR SGN MSB LSB DCLK Write Format R/W DOUT MSB LSB DCLK For Polled vs Interrupt Operation and Write Value Modified Cycle Use TC520A Data Sheet (DS21431). FIGURE 3-3: A/D CONVERTER TIMING Conversion Phase Data to Serial Port Transmit Register AZ INT Updated Data Ready DINT IZ AZ Updated Data Ready TDR EOC 3.3 Input Integrate Phase (INT) In this phase, a current directly proportional to differential input voltage is sourced into integrating capacitor CINT. The amount of voltage stored on CINT at the end of the INT phase is directly proportional to the applied differential input voltage. Input signal polarity (sign bit) is determined at the end of this phase. Converter resolution and speed is a function of the duration of the INT phase, which is programmable by the user via the serial port (see Section 4.1.1, AZ and INT Phase Duration). The shorter the integration time, the faster the 2002 Microchip Technology Inc. speed of conversion (but the lower the resolution). Conversely, the longer the integration time, the greater the resolution (but at slower the speed of conversion). DS21433B-page 9 TC530/TC534 3.4 Reference De-integrate Phase (DINT) This phase consists of measuring the time for the integrator output to return (at a rate determined by the external reference voltage) from its initial voltage to 0V. The resulting timer data is stored in the output shift register as converted analog data. 3.5 Integrator Output Zero Phase (IZ) This phase ensures the integrator output is at zero volts when the AZ phase is entered so that only true system offset voltages will be compensated for. All internal converter timing is derived from the frequency source at OSC IN and OSCOUT. This frequency source must be either an externally provided clock signal or an external crystal. If an external clock is used, it must be connected to the OSCIN pin and the OSC OUT pin must remain floating. If a crystal is used, it must be connected between OSCIN and OSCOUT and be physically located as close to the OSCIN and OSC OUT pins as possible. In either case, the incoming clock frequency is divided by four, with the resulting clock serving as the internal TC530/TC534 timebase. 4.0 TYPICAL APPLICATIONS 4.1 Programming the TC530/TC534 4.1.1 AZ AND INT PHASE DURATION These two phases have equal duration determined by the crystal (or external) frequency and the timer initialization byte (LOAD VALUE). Timing is selected as follows: 1. Select Integration Time Integration time must be picked as a multiple of the period of the line frequency. For example, TINT times of 33msec, 66msec and 132msec maximize 60Hz line rejection. 2. 3. EQUATION 4-2: [LOAD VALUE]10 = EQUATION 4-1: 2(R)/TINT where: R = Desired Converter Resolution (in counts) FIN = Input Frequency (in MHz) INT = Integration Time (in seconds) 256 - (TINT)(FIN) 1024 FIN can be adjusted to a standard value during this step. The resulting base, -10 LOAD VALUE, must be converted to a hexadecimal number and then loaded into the serial port prior to initiating A/D conversion. 4.2 DINT and IZ Phase Timing The duration of the DINT phase is a function of the amount of voltage stored on the integrator capacitor during INT and the value of VREF. The DINT phase is initiated immediately following INT and terminated when an integrator output zero crossing is detected. In general, the maximum number of counts chosen for DINT is twice that of INT (with VREF chosen at VIN(MAX)/2). 4.3 System RESET The TC530/TC534 must be forced into the AZ state when power is first applied. A .01µF capacitor connected from RESET to VDD (or external system reset logic signal) can be used to momentarily drive RESET high for a minimum of 100msec. 4.4 Design Example Figure 4-1 shows a typical TC534 interrupt-driven application. Timing and component values are calculated from equations and recommendations made in Section 3.1 and Section 4.1 of this document. The EOC connection to the processor INT input is for interrupt-driven applications only. (In polled systems, the EOC output is available on DOUT). Given: Required resolution:16-bits (65,536 counts.) Maximum: VIN ±2V Estimate Crystal Frequency Crystal frequencies as high as 2MHz are allowed. Crystal frequency is estimated using: Calculate LOAD VALUE Power supply voltage: +5V 60hz system 1. 2. Pick Integration time (TINT): 66msec Estimate crystal frequency. EXAMPLE 4-1: FIN = 2R/TINT = 2 x 65536/66 x 10-3 = 1.98MHz (use 2MHz) 3. Calculate LOAD VALUE EXAMPLE 4-2: LOAD VALUE = 256 – (T INT)(FIN)/1024 = 10  10 = 80 hex DS21433B-page 10 2002 Microchip Technology Inc. TC530/TC534 4. Calculate RINT 4.6 EXAMPLE 4-3: RINT = VINMAX/20 = 2/20 = 100kΩ 5. 1. Calculate CINT for maximum (4V) integrator output swing: EXAMPLE 4-4: CINT = (TINT)(20 x 10–6 )/ (VS – 0.9) = (.066)(20 x 10–6)/(4.1) 2. = .32µF (use closest value: 0.33µF) Note: 6. Microchip recommended capacitor: Evox-Rifa p/n: SMR5 334K50J03L Choose CREF and CAZ based on conversion rate: EXAMPLE 4-5: Conversions/sec = 1/(TAZ + TINT + 2TINT + 2msec) 3. = 1/(66msec + 66msec + 132msec + 2msec) = 3.7 conversions/sec from which CAZ = C REF = 0.22µF (Table 5-1) 4. Note: 7. Microchip recommended capacitor: Evox-Rifa p/n: SMR5 224K50J02L4 Calculate VREF. 5. EXAMPLE 4-6: VREF = (V S – 0.9) (C INT) (R INT) 2(TINT) = (4.1) (0.33 x 1 –6) (105) / 2(.066) 6. = 1.025V 4.5 Power Supply Sequencing Improper sequencing of the power supply inputs (VDD vs. VCCD) can potentially cause an improper power-up sequence to occur. See Section 4.6, Circuit Design/ Layout Considerations. Failing to insure a proper power-up sequence can cause spurious operation. 2002 Microchip Technology Inc. 7. Circuit Design/Layout Considerations Separate ground return paths should be used for the analog and digital circuitry. Use of ground planes and trace fill on analog circuit sections is highly recommended EXCEPT for in and around the integrator section and CREF, CAZ (C INT, CREF, C AZ, RINT). Stray capacitance between these nodes and ground appears in parallel with the components themselves and can affect measurement accuracy. Improper sequencing of the power supply inputs (VDD vs. VCCD) can potentially cause an improper power-up sequence to occur in the internal state machines. It is recommended that the digital supply, VCCD, be powered up first. One method of insuring the correct power-up sequence is to delay the analog supply using a series resistor and a capacitor. See Figure 4-1, TC530/TC534 Typical Application. Decoupling capacitors, preferably a higher value electrolytic or tantulum in parallel with a small ceramic or tantalum, should be used liberally. This includes bypassing the supply connections of all active components and the voltage reference. Critical components should be chosen for stability and low noise. The use of a metal-film resistor for RINT and Polypropylene or Polyphenelyne Sulfide (PPS) capacitors for CINT, CAZ and CREF is highly recommended. The inputs and integrator section are very high impedance nodes. Leakage to or from these critical nodes can contribute measurement error. A guard-ring should be used to protect the integrator section from stray leakage. Circuit assemblies should be exceptionally clean to prevent the presence of contamination from assembly, handling or the cleaning itself. Minute conductive trace contaminates, easily ignored in most applications, can adversely affect the performance of high impedance circuits. The input and integrator sections should be made as compact and close to the TC53X as possible. Digital and other dynamic signal conductors should be kept as far from the TC53X’s analog section as possible. The microcontroller or other host logic should be kept quiet during a measurement cycle. Background activities such as keypad scanning, display refreshing and power switching can introduce noise. DS21433B-page 11 TC530/TC534 TC530/TC534 TYPICAL APPLICATION FIGURE 4-1: +5V +5V C1 .01µF VDD .01µF IN1+ RESET IN1- VCCD 10µF 100Ω VDD IN2+ VCCD .01µF I/O IN3- DOUT I/O IN4+ DIN I/O IN4- DCLK I/O 1µF CAZ 0.22µF CINT CAZ BUF RINT 100k CREF 0.22µF MUX Channel Control INT R/W IN3+ CIN 0.33µF (Optional) EOC IN2Analog Inputs TC534 OSCIN X1: 2MHz OSCOUT –5V VSS 1µF DGND CREF+ CREFA0 A1 CAP+ 1µF Processor +5V R1 100k R2 100k VREF+ (1.03V) VREFACOM CAP- DS21433B-page 12 2002 Microchip Technology Inc. TC530/TC534 5.0 SELECTING COMPONENT VALUES FOR THE TC530/TC534 Calculate Integrating Resistor (RINT) 1. The desired full scale input voltage and amplifier output current capability determine the value of R INT. The buffer and integrator amplifiers each have a full scale current of 20µA. The value of RINT is therefore directly calculated as follows: It is critical that the integrating capacitor have a very low dielectric absorption. PPS capacitors are an example of one such dielectric. Table 5-2 summarizes various capacitors suitable for CINT. TABLE 5-2: Value (µF) Suggested Part Number* EQUATION 5-1: RINT = VINMAX mΩ 20 where: Note: 5.2 VIN(MAX) = Maximum Input Voltage (full count voltage) R INT = Integrating Resistor (in mΩ) RECOMMENDED CAPACITOR FOR CINT 0.1 SMR5 104K50J0IL 0.22 SMR5 224K50J2L 0.33 SMR5 334K50J03L4 0.47 SMR5 474K50J04L *Manufactured by Evox-Rifa, Inc. Calculate VREF The reference de-integration voltage is calculated using the following equaton: For loop stability, RINT should be ≥ 50kΩ. 2. Select Reference (CREF) and Auto Zero (CAZ) Capacitors C REF and CAZ must be low leakage capacitors (such as polypropylene). The slower the conversion rate, the larger the value CREF must be. Recommended capacitors for CREF and CAZ are shown in Table 5-1. Larger values for CAZ and C REF may also be used to limit rollover errors. TABLE 5-1: C REF AND CAZ SELECTION Conversion Per Second Typical Value of C REF, C AZ (µF) Suggested* Part Number >7 0.1 SMR5 104K50J0IL 2 to 7 0.22 SMR5 224K50J2L 2 or less 0.47 SMR5 474K50J04L Note: 5.1 *Manufactured by Evox-Rifa, Inc. Calculate Integrating Capacitor (CINT) The integrating capacitor must be selected to maximize integrator output voltage swing. The integrator output voltage swing is defined as the absolute value of VDD (or VSS) less 0.9V (i.e.,IVDD – 0.9VI or IVSS +0.9VI). Using the 20µA buffer maximum output current, the value of the integrating capacitor is calculated using the following equation. VREF = 5.3 (VS – 0.9) (CINT) (RINT) 2(RINT) V Serial Port Communication with the TC530/TC534 is accomplished over a 3 wire serial port. Data is clocked into DIN on the rising edge of DCLK and clocked out of DOUT on the falling edge of DCLK. R/W must be HIGH to read converted data from the serial port and LOW to write the LOAD VALUE to the TC530/TC534. 5.4 Data Read Cycle Data is shifted out of the serial port in the following order: End of Conversion (EOC), Overrange (OVR), Polarity (POL), conversion data (MSB first). When R/W is high, the state of the EOC bit can be polled by simply reading the state of DOUT. This allows the processor to determine if new data is available without connecting an additional wire to the EOC output pin (this is especially useful in a polled environment). See Figure 5-1. FIGURE 5-1: SERIAL PORT DATA READ CYCLE R/W DCLK EQUATION 5-2: (TINT) (20 x 10 CINT = (V S - 0.9) EQUATION 5-3: -6) µF DOUT EOC OVR POL MSB LSB where: TINT = Integration Period VS = IVDD I CINT = Integrated Capacitor Value (µF). 2002 Microchip Technology Inc. DS21433B-page 13 TC530/TC534 5.5 Load Value Write Cycle 5.6 Following the power-up reset pulse, the LOAD VALUE (which sets the duration of AZ and INT) must next be transmitted to the serial port. To accomplish this, the processor monitors the state of EOC (which is available as a hardware output or at DOUT). R/W is taken low to initiate the write cycle only when EOC is low (during the AZ phase). (Failure to observe EOC low may cause an offset voltage to be developed across CINT, resulting in erroneous readings). The 8-bit LOAD VALUE data on DIN is clocked in by DCLK. The processor then terminates the write cycle by taking R/W high. (Data is transferred from the serial input shift register to the time base counter on the rising edge of R/W and data conversion is initiated). See Figure 5-2. FIGURE 5-2: Timing Status A 4-input, differential multiplexer is included in the TC534. The states of channel address lines A0 and A1 determine which differential VIN pair is routed to the converter input. A0 is the least significant address bit (i.e., channel 1 is selected when A0 = 0 and A1 = 0). The multiplexer is designed to be operated in a differential mode. For single-ended inputs, the CHx- input for the channel under selection must be connected to the ground reference associated with the input signal. TC530/TC534 INITIALIZATION AND LOAD VALUE WRITE CYCLE Power-up RESET Conversion Phase R/W Input Multiplexer (TC534 Only) Undefined Write LOAD VALUE to Serial Port AZ INT AZ R/W brought LOW during AZ for serial port write cycle Converter held in AZ state due to RESET = 1 Converter in Normal Service DINT IZ AZ… Continuous Conversions R/W = HIGH strobes LOAD VALUE into timebase and starts conversion RESET DCLK DIN 1 1 MSB EOC 5.7 0 0 1 1 LOAD VALUE 1 1 LSB DC/DC Converter An on-board, TC7660H-type charge pump supplies negative bias to the converter circuitry, as well as to external devices. The charge pump develops a negative output voltage by moving charge from the power supply to the reservoir capacitor at VSS by way of the commutating capacitor connected to the CAP+ and CAP- inputs. The charge pump clock operates at a typical frequency of 100kHz. If lower quiescent current is desired, the charge pump clock can be slowed by connecting an external capacitor from the OSC pin to VDD. Reference typical characteristics curves. DS21433B-page 14 2002 Microchip Technology Inc. TC530/TC534 6.0 TYPICAL CHARACTERISTICS The graphs and tables following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range), and therefore outside the warranted range. Output Voltage vs. Output Current Output Voltage vs. Load Current 5 TA = 25˚C V+ = 5V 3 2 1 0 -1 -2 Slope 60Ω -3 -2 -3 -4 -5 -6 -4 -7 -5 -8 0 10 TA = 25˚C -1 OUTPUT VOLTAGE (V) 4 OUTPUT VOLTAGE (V) -0 20 30 40 50 60 70 0 80 2 4 Output Ripple vs. Load Current OUTPUT SOURCE RESISTANCE (Ω) OUTPUT RIPPLE (mV PK-PK) V+ = 5V, TA = 25˚C Osc. Freq. = 100kHz 150 CAP = 1µF 125 100 CAP = 10µF 75 50 25 0 0 1 2 3 4 5 6 7 8 9 10 100 90 10 12 14 60 50 40 0 25 50 TEMPERATURE (˚C) -25 10 1 OSCILLATOR CAPACITANCE (pF) 1000 OSCILLATOR FREQUENCY (kHz) TA = +25˚C V+ = 5V 100 75 100 Oscillator Frequency vs. Temperature 150 2002 Microchip Technology Inc. 20 70 Oscillator Frequency vs. Capacitance 10 18 80 -50 100 1 16 V+ = 5V IOUT = 10mA LOAD CURRENT (mA) OSCILLATOR FREQUENCY (kHz) 8 Output Source Resistance vs. Temperature 200 175 6 OUTPUT CURRENT (mA) LOAD CURRENT (mA) V+ = 5V 125 100 75 50 -50 -25 0 25 75 50 TEMPERATURE (˚C) 100 125 DS21433B-page 15 TC530/TC534 7.0 PACKAGING INFORMATION 7.1 Package Marking Information Package marking data not available at this time. 7.2 Taping Forms Component Taping Orientation for 28-Pin SOIC (Wide) Devices User Direction of Feed PIN 1 W P Standard Reel Component Orientation for TR Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package 28-Pin SOIC (W) Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 24 mm 12 mm 1000 13 in Component Taping Orientation for 44-Pin PQFP Devices User Direction of Feed PIN 1 W P Standard Reel Component Orientation for TR Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package 44-Pin PQFP Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 24 mm 16 mm 500 13 in NOTE: Drawing does not represent total number of pins. DS21433B-page 16 2002 Microchip Technology Inc. TC530/TC534 7.3 Package Dimensions 28-Pin PDIP (Narrow) PIN 1 .288 (7.32) .240 (6.10) .045 (1.14) .030 (0.76) .310 (7.87) .290 (7.37) 1.400 (35.56) 1.345 (34.16) .200 (5.08) .140 (3.56) .040 (1.02) .015 (0.38) .150 (3.81) .115 (2.92) .110 (2.79) .090 (2.29) .070 (1.78) .045 (1.14) .015 (0.38) .008 (0.20) 3˚ MIN. .400 (10.16) .310 (7.87) .022 (0.56) .015 (0.38) Dimensions: inches (mm) 40-Pin PDIP (Wide) PIN 1 .555 (14.10) .530 (13.46) 2.065 (52.45) 2.027 (51.49) .610 (15.49) .590 (14.99) .200 (5.08) .140 (3.56) .040 (1.02) .020 (0.51) .150 (3.81) .115 (2.92) .110 (2.79) .090 (2.29) .070 (1.78) .045 (1.14) .015 (0.38) .008 (0.20) 3˚ MIN. .700 (17.78) .610 (15.50) .022 (0.56) .015 (0.38) Dimensions: inches (mm) 2002 Microchip Technology Inc. DS21433B-page 17 TC530/TC534 7.3 Package Dimensions (Continued) 28-Pin SOIC (Wide) PIN 1 .299 (7.59) .419 (10.65) .291 (7.40) .398 (10.10) .713 (18.11) .697 (17.70) .103 (2.62) .097 (2.46) .019 (0.48) .014 (0.36) .013 (0.33) .009 (0.23) 8˚ MAX. .012 (0.30) .004 (0.10) .050 (1.27) .016 (0.40) Dimensions: inches (mm) 44-Pin PQFP 7 ˚MAX. .009 (0.23) .005 (0.13) PIN 1 .018 (0.45) .012 (0.30) .041 (1.03) .026 (0.65) .398 (10.10) .390 (9.90) .557 (14.15) .537 (13.65) .031 (0.80) TYP. .398 (10.10) .390 (9.90) .557 (14.15) .537 (13.65) .010 (0.25) TYP. .083 (2.10) .075 (1.90) .096 (2.45) MAX. Dimensions: inches (mm) DS21433B-page 18 2002 Microchip Technology Inc. TC530/534 SALES AND SUPPORT Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. DS21433B-page 19 TC530/534 NOTES: DS21433B-page 20 2002 Microchip Technology Inc. TC530/TC534 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro ® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. DS21433B-page 21 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Rocky Mountain China - Beijing 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-7456 Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Kokomo 2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 China - Chengdu Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599 China - Fuzhou Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521 China - Shanghai Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 China - Shenzhen 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086 San Jose China - Hong Kong SAR Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 New York Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O’Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 France Microchip Technology SARL Parc d’Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Italy Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 04/20/02 *DS21433B* DS21433B-page 22 2002 Microchip Technology Inc.