TI TPS7250QD

TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
D
D
D
D
D
D
D
D, P, OR PW PACKAGE
(TOP VIEW)
Available in 5-V, 4.85-V, 3.3-V, 3.0-V, and
2.5-V Fixed-Output and Adjustable Versions
Dropout Voltage <85 mV Max at
IO = 100 mA (TPS7250)
Low Quiescent Current, Independent of
Load, 180 µA Typ
8-Pin SOIC and 8-Pin TSSOP Package
Output Regulated to ± 2% Over Full
Operating Range for Fixed-Output Versions
Extremely Low Sleep-State Current,
0.5 µA Max
Power-Good (PG) Status Output
SENSE†/FB‡
RESET/PG
GND
EN
1
8
2
7
3
6
4
5
OUT
OUT
IN
IN
† SENSE – Fixed voltage options only
(TPS7225, TPS7230, TPS7233, TPS7248,
and TPS7250)
‡ FB – Adjustable version only (TPS7201)
600
TA = 25°C
description
The TPS72xx family of low-dropout (LDO) voltage
regulators offers the benefits of low-dropout
voltage, micropower operation, and miniaturized
packaging. These regulators feature extremely
low dropout voltages and quiescent currents
compared to conventional LDO regulators.
Offered in small-outline integrated-circuit (SOIC)
packages and 8-terminal thin shrink small-outline
(TSSOP), the TPS72xx series devices are ideal
for cost-sensitive designs and for designs where
board space is at a premium.
VDO – Dropout Voltage – mV
500
TPS7225
400
TPS7230
300
TPS7233
TPS7248
200
100
TPS7250
A combination of new circuit design and process
0
innovation has enabled the usual pnp pass
200
250
0
50
100
150
transistor to be replaced by a PMOS device.
IO – Output Current – mA
Because the PMOS pass element behaves as a
low-value resistor, the dropout voltage is very low
Figure 1. Typical Dropout Voltage Versus
– maximum of 85 mV at 100 mA of load current
Output Current
(TPS7250) – and is directly proportional to the
load current (see Figure 1). Since the PMOS pass
element is a voltage-driven device, the quiescent current is very low (300 µA maximum) and is stable over the
entire range of output load current (0 mA to 250 mA). Intended for use in portable systems such as laptops and
cellular phones, the low-dropout voltage and micropower operation result in a significant increase in system
battery operating life.
The TPS72xx also features a logic-enabled sleep mode to shut down the regulator, reducing quiescent current
to 0.5 µA maximum at TJ = 25°C. Other features include a power-good function that reports low output voltage
and may be used to implement a power-on reset or a low-battery indicator.
The TPS72xx is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for adjustable version).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
AVAILABLE OPTIONS
TJ
OUTPUT VOLTAGE
(V)
MIN
– 55°C to 150°C
TYP
PACKAGED DEVICES
MAX
SMALL OUTLINE
(D)
PDIP
(P)
TSSOP
(PW)
CHIP FORM
(Y)
4.9
5
5.1
TPS7250QD
TPS7250QP
TPS7250QPWR
TPS7250Y
4.75
4.85
4.95
TPS7248QD
TPS7248QP
TPS7248QPWR
TPS7248Y
3.23
3.3
3.37
TPS7233QD
TPS7233QP
TPS7233QPWR
TPS7233Y
2.94
3
3.06
TPS7230QD
TPS7230QP
TPS7230QPWR
TPS7230Y
2.45
2.5
2.55
TPS7225QD
TPS7225QP
TPS7225QPWR
TPS7225Y
TPS7201QD
TPS7201QP
TPS7201QPWR
TPS7201Y
Adjustable
1.2 V to 9.75 V
The D package is available taped and reeled. Add R suffix to device type (e.g., TPS7250QDR). The PW package is only available left-end
taped and reeled. The TPS7201Q is programmable using an external resistor divider (see application information). The chip form is tested
at 25°C.
TPS72xx‡
VI
5
IN
PG
6
PG
1
250 kΩ
SENSE
IN
OUT
0.1 µF
2
4
OUT
EN
7
VO
8
GND
3
+
CO
(see Note A)
10 µF
CSR = 1 Ω
‡ TPS7225Q, TPS7230Q, TPS7233Q, TPS7248Q, TPS7250Q (fixed-voltage
options)
NOTE A: Capacitor selection is nontrivial. See application information section
for details.
Figure 2. Typical Application Configuration
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS72xx chip information
These chips, when properly assembled, display characteristics similar to the TPS72xxQ. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
IN
(5)
7
(6) 6
(3)
(4)
4
(2)
EN
5
TPS72xx
(5)
SENSEĔ
(6)
FBĕ
(4)
OUT
(7)
PG
(1)
(7)
GND
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
57
TJmax = 150°C
TOLERANCES ARE ± 10%.
1
ALL DIMENSIONS ARE IN MILS.
(1) (2)
2
3
† Fixed-voltage options only (TPS7225,
TPS7233, TPS7248, and TPS7250)
‡ Adjustable version only (TPS7201)
(3)
TPS7230,
NOTE A. For most applications, OUT and SENSE should
be tied together as close as possible to the device;
for other implementations, refer to the SENSE-pin
connection discussion in the application
information section of this data sheet.
69
functional block diagram
IN
RESISTOR DIVIDER OPTIONS
§
EN
§
§
PG
_
+
OUT
1.12 V
SENSE¶/FB
+
_
DEVICE
R1
R2
UNIT
TPS7201
TPS7225
TPS7230
TPS7233
TPS7248
TPS7250
0
257
357
420
726
756
∞
233
233
233
233
233
Ω
kΩ
kΩ
kΩ
kΩ
kΩ
NOTE A: Resistors are nominal values only.
R1
Vref = 1.188 V
COMPONENT COUNT
R2
MOS transistors
Bilpolar transistors
Diodes
Capacitors
Resistors
108
41
4
15
75
GND
§ Switch positions are shown with EN low (active).
¶ For most applications, SENSE should be externally connected to OUT as close as possible to the device.
For other implementations, refer to the SENSE-pin connection discussion in application information section.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Ĕ
Input voltage rangeĕ, VI, PG, SENSE, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 11 V
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURE (see Note 1 and Figure 3)
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
P
PW
725 mW
1175 mW
525 mW
5.8 mW/°C
8.74
8
74 mW/°C
4.2 mW/°C
464 mW
782 mW
336 mW
377 mW
650 mW
273 mW
145 mW
301 mW
105 mW
DISSIPATION RATING TABLE 2 – CASE TEMPERATURE (see Note 1 and Figure 4)
PACKAGE
TC ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TC = 25°C
TC = 70°C
POWER RATING
TC = 85°C
POWER RATING
TC = 125°C
POWER RATING
D
P
PW
2063 mW
2738 mW
2900 mW
16.5 mW/°C
20.49
20
49 mW/°C
23.2 mW/°C
1320 mW
1816 mW
1856 mW
1073 mW
1508 mW
1508 mW
413 mW
689 mW
580 mW
NOTE 1: Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute
maximum of 150°C. For guidelines on maintaining junction temperature within the recommended operating range,
see application information section.
MAXIMUM CONTINUOUS DISSIPATION
vs
FREE-AIR TEMPERATURE
MAXIMUM CONTINUOUS DISSIPATION
vs
CASE TEMPERATURE
3000
PD – Maximum Continuous Dissipation – mW
PD – Maximum Continuous Dissipation – mW
1200
1100
P Package
RθJA = 114.4°C/W
1000
900
800
D Package
RθJA = 172°C/W
700
600
500
400
300
PW Package
RθJA = 238°C/W
200
100
0
25
50
75
100
125
150
P Package
RθJC = 48.8°C/W
2500
2000
PW Package
RθJC = 43.1°C/W
1500
1000
D Package
RθJC = 60.6°C/W
500
0
25
TA – Free-Air Temperature – °C
75
Figure 4
POST OFFICE BOX 655303
100
125
TC – Case Temperature – °C
Figure 3
4
50
• DALLAS, TEXAS 75265
150
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
recommended operating conditions
Input voltage,
voltage VI†
MIN
MAX
TPS7201Q
3
10
TPS7225Q
3.65
10
TPS7230Q
3.96
10
TPS7233Q
3.98
10
TPS7248Q
5.24
10
TPS7250Q
5.41
10
High-level input voltage at EN, VIH
2
Low-level input voltage at EN, VIL
Output current, IO
0
UNIT
V
V
0.5
V
250
mA
Operating virtual junction temperature, TJ
– 40
125
°C
† Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the
maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To
calculate the minimum input voltage for the maximum load current used in a given application, use the following equation:
V
V
V
I(min)
O(max)
DO(max load)
+
)
Because the TPS7201 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for
calculating VDO from rDS(on) is given in Note 3 under the TPS7201 electrical characteristics table. The minimum value of 3 V is the absolute
lower limit for the recommended input-voltage range for the TPS7201.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), SENSE/FB shorted to OUT
(unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Ground current (active mode)
EN ≤ 0.5 V,
0 mA ≤ IO ≤ 250 mA
VI = VO + 1 V,
Input current (standby mode)
EN = VI,
3 V ≤ VI ≤ 10 V
Output current limit threshold
VO = 0 V
VI = 10 V
Pass-element leakage
g current in
standby mode
EN = VI,
3 V ≤ VI ≤ 10 V
PG leakage current
VPG = 10 V,
V
Normal operation
Output voltage temperature coefficient
TJ
TPS72xxQ
MIN
25°C
EN logic low (active mode)
225
25°C
0.5
– 40°C to 125°C
1
25°C
0.6
1
– 40°C to 125°C
1.5
25°C
0.5
– 40°C to 125°C
1
25°C
0.5
– 40°C to 125°C
0.5
– 40°C to 125°C
31
75
3 V ≤ VI ≤ 6 V
6 V ≤ VI ≤ 10 V
3 V ≤ VI ≤ 10 V
– 40°C to 125°C
2
0 V ≤ VI ≤ 10 V
25°C
0.5
– 40°C to 125°C
0.5
50
– 0.5
0.5
– 40°C to 125°C
– 0.5
0.5
1.9
– 40°C to 125°C
IPG = 300 µA
25°C
– 40°C to 125°C
µA
A
µA
µA
ppm/°C
2.5
2.5
1.1
V
mV
25°C
25°C
µA
V
2.7
25°C
UNIT
°C
165
Minimum VI for active pass element
Minimum VI for valid PG
180
325
EN hysteresis voltage
EN input current
MAX
– 40°C to 125°C
Thermal shutdown junction temperature
EN logic high (standby mode)
TYP
1.5
1.9
µA
V
V
† CSR(compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any
series resistance added externally, and PWB trace resistance to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7201Q electrical characteristics, IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), FB
shorted to OUT at device leads (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Reference voltage
g ((measured
at FB with OUT connected to
FB)
VI = 3.5 V,
3 V ≤ VI ≤ 10 V,
See Note 2
TJ
IO = 10 mA
5 mA ≤ IO ≤ 250 mA,
Reference voltage
temperature coefficient
VI = 2.4 V,§
VI = 2.4 V,§
Pass-element series
resistance (see Note 3)
Input regulation
Output regulation
25°C
– 40°C to 125°C
TYP
1.152
50 µA ≤ IO ≤ 100 mA
25°C
2.1
100 mA ≤ IO ≤ 200 mA
25°C
2.9
25°C
1.6
VI = 2
2.9
9V
V,
50 µA ≤ IO ≤ 250 mA
VI = 3.9 V,
VI = 5.9 V,
50 µA ≤ IO ≤ 250 mA
25°C
1
50 µA ≤ IO ≤ 250 mA
25°C
0.8
VI = 3 V to 10 V,,
See Note 2
50 µ
µA ≤ IO ≤ 250 mA,,
IO = 5 mA to 250 mA,,
See Note 2
3 V ≤ VI ≤ 10 V,,
IO = 50 µA
µ to 250 mA,,
See Note 2
3 V ≤ VI ≤ 10 V,,
f = 120 Hz
Output noise voltage
10 Hz
H ≤ f ≤ 100 kHz,
kH
CSR† = 1 Ω
25°C
23
36
25°C
15
17
25°C
49
– 40°C to 125°C
32
25°C
45
– 40°C to 125°C
30
25°C
235
25°C
190
CO = 100 µF
25°C
125
IPG = 400 µA
µA,
VI = 2
2.13
13 V
FB input current
27
mV
mV
dB
50
CO = 10 µF
PG output low voltage¶
Ω
60
CO = 4.7 µF
Measured at VFB
ppm/°C
43
2
PG hysteresis voltage¶
V
25
36
25°C
25°C
VFB voltage decreasing from above VPG
2.7
– 40°C to 125°C
– 40°C to 125°C
PG trip-threshold voltage¶
75
4.5
– 40°C to 125°C
IO = 250 mA,,
See Note 2
Output noise spectral density
– 40°C to 125°C
UNIT
V
1.224
31
f = 120 Hz
MAX
1.188
– 40°C to 125°C
IO = 50 µA
Ripple rejection
TPS7201Q
MIN
µV/√Hz
µVrms
0.95 ×
VFB(nom)
– 40°C to 125°C
25°C
12
25°C
0.1
– 40°C to 125°C
V
mV
0.4
0.4
25°C
– 10
– 40°C to 125°C
– 20
0.1
10
20
V
nA
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§ This voltage is not recommended.
¶ Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 2. When VI < 2.9 V and IO > 100 mA simultaneously, pass element rDS(on) increases (see Figure 10) to a point such that the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
3. To calculate dropout voltage, use equation:
VDO = IO ⋅ rDS(on)
rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other
programmed values, refer to Figures 10 and 11.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7225Q electrical characteristics, IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
TJ
Output voltage
VI = 3.5 V,
3.5 V ≤ VI ≤ 10 V,
IO = 10 mA
5 mA ≤ IO ≤ 250 mA
Dropout voltage
IO = 250 mA,
mA
VI = 2
2.97
97 V
Pass element series resistance
Pass-element
(
(2.97
V – VO)/I
) O,
IO = 250 mA
VI = 2.97 V,,
Input regulation
3 5 V to 10 V,
V
VI = 3.5
50 µA ≤ IO ≤ 250 mA
IO = 5 mA to 250 mA,
mA
3 5 V ≤ VI ≤ 10 V
3.5
IO = 50 µA to 250 mA,
mA
3 5 V ≤ VI ≤ 10 V
3.5
IO = 50 µA
f = 120 Hz
IO = 250 mA
Output noise spectral density
f = 120 Hz
Output noise voltage
H ≤ f ≤ 100 kHz,
kH
10 Hz
CSR† = 1 Ω
PG trip-threshold voltage
IPG = 1.2
1 2 mA,
mA
25°C
2.55
560
– 40°C to 125°C
25°C
2.24
25°C
9
– 40°C to 125°C
25°C
28
24
– 40°C to 125°C
47
– 40°C to 125°C
45
25°C
40
– 40°C to 125°C
38
27
Ω
mV
36
41
mV
58
dB
46
25°C
248
CO = 10 µF
25°C
200
CO = 100 µF
25°C
130
– 40°C to 125°C
0.95 ×
VO(nom)
25°C
50
25°C
0.3
– 40°C to 125°C
V
3.4
73
25°C
CO = 4.7 µF
VI = 2
2.13
13 V
mV
60
25°C
V
1.1
33
– 40°C to 125°C
UNIT
850
3.84
2
VO voltage decreasing from above VPG
MAX
2.5
2.45
25°C
PG hysteresis voltage
PG output low voltage
25°C
– 40°C to 125°C
TYP
– 40°C to 125°C
Output regulation
Ripple rejection
TPS7225Q
MIN
µV/√Hz
µVrms
V
mV
0.44
0.5
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7230Q electrical characteristics, IO = 10 mA, VI = 4 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
TJ
VI = 4 V,
4 V ≤ VI ≤ 10 V,
IO = 10 mA
5 mA ≤ IO ≤ 250 mA
IO = 100 mA,
mA
VI = 2
2.97
97 V
Dropout voltage
IO = 250 mA,
mA
VI = 2
2.97
97 V
Pass element series resistance
Pass-element
((2.97 V – VO)/I
) O,
IO = 250 mA
VI = 2.97 V,,
Input regulation
VI = 4 V to 10 V,
V
50 µA ≤ IO ≤ 250 mA
IO = 5 mA to 250 mA,
mA
4 V ≤ VI ≤ 10 V
4 V ≤ VI ≤ 10 V
IO = 50 µA
Ripple rejection
f = 120 Hz
IO = 250 mA
Output noise spectral density
Output noise voltage
PG trip-threshold voltage
f = 120 Hz
10 Hz
H ≤ f ≤ 100 kHz,
kH
CSR† = 1 Ω
IPG = 1.2
1 2 mA,
mA
25°C
3.06
145
– 40°C to 125°C
390
502
1.56
2.01
– 40°C to 125°C
3.6
25°C
9
– 40°C to 125°C
25°C
34
– 40°C to 125°C
mV
42
– 40°C to 125°C
Ω
mV
45
74
25°C
60
mV
98
25°C
45
– 40°C to 125°C
44
25°C
40
– 40°C to 125°C
38
56
dB
45
2
256
CO = 10 µF
25°C
206
CO = 100 µF
25°C
132
µV/√Hz
µVrms
0.95 ×
VO(nom)
25°C
50
25°C
0.25
– 40°C to 125°C
27
33
25°C
VI = 2
2.55
55 V
V
900
25°C
– 40°C to 125°C
UNIT
185
270
25°C
25°C
VO voltage decreasing from above VPG
MAX
3
2.94
CO = 4.7 µF
PG hysteresis voltage
PG output low voltage
25°C
– 40°C to 125°C
TYP
– 40°C to 125°C
Output regulation
IO = 50 µA to 250 mA,
mA
TPS7230Q
MIN
V
mV
0.44
0.44
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7233Q electrical characteristics, IO = 10 mA, VI = 4.3 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
TJ
VI = 4.3 V,
4.3 V ≤ VI ≤ 10 V,
IO = 10 mA
5 mA ≤ IO ≤ 250 mA
IO = 10 mA,
mA
VI = 3
3.23
23 V
IO = 100 mA,
mA
VI = 3
3.23
23 V
mA
IO = 250 mA,
23 V
VI = 3
3.23
Pass element series resistance
Pass-element
(
(3.23
V – VO)/I
) O,
IO = 250 mA
VI = 3.23 V,,
Input regulation
VI = 4.3
4 3 V to 10 V,
V
50 µA ≤ IO ≤ 250 mA
IO = 5 mA to 250 mA,
mA
4 3 V ≤ VI ≤ 10 V
4.3
Dropout voltage
4 3 V ≤ VI ≤ 10 V
4.3
IO = 50 µA
Ripple rejection
f = 120 Hz
IO = 250 mA
Output noise spectral density
f = 120 Hz
Output noise voltage
10 Hz
H ≤ f ≤ 100 kHz,
kH
CSR† = 1 Ω
PG trip-threshold voltage
1 2 mA,
mA
IPG = 1.2
25°C
3.37
14
20
140
180
– 40°C to 125°C
– 40°C to 125°C
232
25°C
360
460
1.5
1.84
– 40°C to 125°C
2.5
25°C
8
– 40°C to 125°C
25
33
25°C
32
– 40°C to 125°C
mV
41
– 40°C to 125°C
Ω
mV
42
71
25°C
55
mV
98
25°C
40
– 40°C to 125°C
38
25°C
35
– 40°C to 125°C
33
52
dB
44
25°C
265
CO = 10 µF
25°C
212
CO = 100 µF
25°C
135
– 40°C to 125°C
0.95 ×
VO(nom)
25°C
32
25°C
0.22
– 40°C to 125°C
V
610
25°C
CO = 4.7 µF
8V
VI = 2
2.8
UNIT
30
25°C
2
VO voltage decreasing from above VPG
MAX
3.3
3.23
25°C
PG hysteresis voltage
PG output low voltage
25°C
– 40°C to 125°C
TYP
– 40°C to 125°C
Output regulation
IO = 50 µA to 250 mA,
mA
TPS7233Q
MIN
µV/√Hz
µVrms
V
mV
0.4
0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7248Q electrical characteristics, IO = 10 mA, VI = 5.85 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω),
SENSE shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
TJ
VI = 5.85 V,
5.85 V ≤ VI ≤ 10 V,
IO = 10 mA
5 mA ≤ IO ≤ 250 mA
IO = 10 mA
mA,
VI = 4
4.75
75 V
IO = 100 mA,
mA
VI = 4
4.75
75 V
mA
IO = 250 mA,
75 V
VI = 4
4.75
Pass element series resistance
Pass-element
(
(4.75
V – VO)/I
) O,
IO = 250 mA
VI = 4.75 V,,
Input regulation
VI = 5
5.85
85 V to 10 V
V,
50 µA ≤ IO ≤ 250 mA
IO = 5 mA to 250 mA,
mA
5 85 V ≤ VI ≤ 10 V
5.85
Dropout voltage
Output regulation
IO = 50 µA to 250 mA,
mA
5 85 V ≤ VI ≤ 10 V
5.85
IO = 50 µA
Ripple rejection
f = 120 Hz
IO = 250 mA
Output noise spectral density
f = 120 Hz
Output noise voltage
H ≤ f ≤ 100 kHz,
kH
10 Hz
CSR† = 1 Ω
PG trip-threshold voltage
25°C
4.95
10
19
90
100
– 40°C to 125°C
– 40°C to 125°C
150
25°C
216
– 40°C to 125°C
mV
250
0.8
1
– 40°C to 125°C
1.4
25°C
34
– 40°C to 125°C
50
25°C
43
– 40°C to 125°C
55
– 40°C to 125°C
Ω
mV
55
95
25°C
75
mV
135
25°C
42
– 40°C to 125°C
36
25°C
36
– 40°C to 125°C
34
53
dB
46
25°C
370
CO = 10 µF
25°C
290
CO = 100 µF
25°C
µV/√Hz
µVrms
168
0.95 ×
VO(nom)
25°C
50
25°C
0.2
– 40°C to 125°C
V
285
25°C
– 40°C to 125°C
UNIT
30
25°C
CO = 4.7 µF
VI = 4
4.12
12 V
MAX
4.85
4.75
2
VO voltage decreasing from above VPG
IPG = 1.2
1 2 mA,
mA
25°C
– 40°C to 125°C
TYP
25°C
PG hysteresis voltage
PG output low voltage
TPS7248Q
MIN
V
mV
0.4
0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7250Q electrical characteristics, IO = 10 mA, VI = 6 V, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), SENSE
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
VI = 6 V,
6 V ≤ VI ≤ 10 V,
IO = 10 mA
5 mA ≤ IO ≤ 250 mA
IO = 10 mA
mA,
VI = 4
4.88
88 V
IO = 100 mA,
mA
VI = 4
4.88
88 V
mA
IO = 250 mA,
88 V
VI = 4
4.88
Pass element series resistance
Pass-element
(
(4.88
V – VO))/IO,
IO = 250 mA
VI = 4.88 V,,
Input regulation
VI = 6 V to 10 V,
V
50 µA ≤ IO ≤ 250 mA
IO = 5 mA to 250 mA,
mA
6 V ≤ VI ≤ 10 V
Dropout voltage
6 V ≤ VI ≤ 10 V
IO = 50 µA
Ripple rejection
f = 120 Hz
IO = 250 mA
Output noise spectral density
f = 120 Hz
Output noise voltage
10 Hz
H ≤ f ≤ 100 kHz,
kH
CSR† = 1 Ω
PG trip-threshold voltage
25°C
– 40°C to 125°C
25°C
5.1
8
76
– 40°C to 125°C
V
12
85
136
25°C
190
206
0.76
0.825
– 40°C to 125°C
mV
312
25°C
1.25
25°C
28
– 40°C to 125°C
35
25°C
46
– 40°C to 125°C
59
– 40°C to 125°C
Ω
mV
61
100
25°C
79
mV
150
25°C
41
– 40°C to 125°C
37
25°C
36
– 40°C to 125°C
32
52
dB
46
CO = 4.7 µF
25°C
390
CO = 10 µF
25°C
300
CO = 100 µF
25°C
175
– 40°C to 125°C
0.95 ×
VO(nom)
25°C
50
25°C
0.19
– 40°C to 125°C
UNIT
30
25°C
2
25 V
VI = 4
4.25
MAX
5
4.9
25°C
VO voltage decreasing from above VPG
1 2 mA,
mA
IPG = 1.2
TYP
– 40°C to 125°C
PG hysteresis voltage
PG output low voltage
TPS7250Q
MIN
– 40°C to 125°C
Output regulation
IO = 50 µA to 250 mA
mA,
TJ
µV/√Hz
µVrms
V
mV
0.4
0.4
V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE/FB
shorted to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Ground current (active mode)
EN ≤ 0.5 V,
0 mA ≤ IO ≤ 250 mA
VI = VO + 1 V,
Output current limit threshold
VO = 0 V,
VI = 10 V
MIN
TPS72xxY
TYP
MAX
UNIT
µA
180
0.6
A
165
°C
EN hysteresis voltage
50
mV
Minimum VI for active pass element
1.9
V
1.1
V
Thermal shutdown junction temperature
Minimum VI for valid PG
IPG = 300 µA
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, FB shorted to
OUT at device leads (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Reference voltage (measured at FB with OUT
connected to FB)
TPS7201Y
MIN
TYP
VI = 3.5 V,
IO = 10 mA
VI = 2.4 V,§
VI = 2.4 V,§
50 µA ≤ IO ≤ 100 mA
2.1
100 mA ≤ IO ≤ 200 mA
2.9
VI = 2.9 V,
VI = 3.9 V,
50 µA ≤ IO ≤ 250 mA
1.6
50 µA ≤ IO ≤ 250 mA
1
VI = 5.9 V,
3 V ≤ VI ≤ 10 V,
See Note 2
50 µA ≤ IO ≤ 250 mA
0.8
IO = 5 mA to 250 mA,
15
3 V ≤ VI ≤ 10 V,
See Note 2
IO = 50 µA to 250 mA,
17
Ripple rejection
VI = 3
3.5
5V
V,
f = 120 Hz
IO = 50 µA
IO = 250 mA,
See Note 2
Output noise spectral density
VI = 3.5 V,
f = 120 Hz
Pass-element series resistance (see Note 3)
Output regulation
Output noise voltage
VI = 3.5 V,
10 Hz ≤ f ≤ 100 kHz,
CSR† = 1 Ω
1.188
MAX
UNIT
V
Ω
mV
60
50
2
CO = 4.7 µF
235
CO = 10 µF
190
CO = 100 µF
125
dB
µV/√Hz
µVrms
PG hysteresis voltage¶
VI = 3.5 V,
Measured at VFB
12
mV
PG output low voltage¶
VI = 2.13 V,
IPG = 400 µA
0.1
V
FB input current
0.1
nA
VI = 3.5 V
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
§ This voltage is not recommended.
¶ Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 2 When VI < 2.9 V and IO > 100 mA simultaneously, pass element rDS(on) increases (see Figure 10) to a point such that the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
3 To calculate dropout voltage, use equation:
VDO = IO ⋅ rDS(on)
rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other
programmed values, refer to Figures 10 and 11.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, FB shorted to
OUT at device leads (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
TPS7225Y
MIN
TYP
MAX
UNIT
Output voltage
VI = 3.5 V,
IO = 10 mA
2.5
V
Dropout voltage
VI = 2.97 V,
IO = 250 mA
560
mV
Pass-element series resistance
(2.97 V – VO)/IO,
IO = 250 mA
VI = 2.97 V,
2.24
Ω
VI = 3.5 V to 10 V,
3.5 V ≤ VI ≤ 10 V
50 µA ≤ IO ≤ 250 mA
9
28
3.5 V ≤ VI ≤ 10 V
IO = 5 mA to 250 mA
IO = 50 µA to 250 mA
Ripple rejection
VI = 3.5 V,,
f = 120 Hz
IO = 50 µA
IO = 250 mA
58
Output noise spectral density
VI = 3.5 V,
f = 120 Hz
Output noise voltage
VI = 3.5 V,
10 Hz ≤ f ≤ 100 kHz,
CSR† = 1 Ω
Input regulation
Output regulation
PG hysteresis voltage
24
46
2
CO = 4.7 µF
248
CO = 10 µF
200
CO = 100 µF
130
50
VI = 3.5 V
mV
mV
dB
µV/√Hz
µVrms
mV
VI = 2.13 V
IPG = 1.2 mA
0.3
V
PG output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE shorted
to OUT (unless otherwise noted)
TEST CONDITIONS‡
PARAMETER
Output voltage
TPS7230Y
MIN
TYP
VI = 4 V,
VI = 2.97 V,
IO = 10 mA
IO = 100 mA
VI = 2.97 V,
(2.97 V – VO)/IO,
IO = 250 mA
IO = 250 mA
VI = 2.97 V,
VI = 4 V to 10 V,
4 V ≤ VI ≤ 10 V
50 µA ≤ IO ≤ 250 mA
9
34
4 V ≤ VI ≤ 10 V
IO = 5 mA to 250 mA
IO = 50 µA to 250 mA
Ripple rejection
VI = 4 V,,
f = 120 Hz
IO = 50 µA
IO = 250 mA
56
Output noise spectral density
VI = 4 V,
f = 120 Hz
Output noise voltage
VI = 4 V,
10 Hz ≤ f ≤ 100 kHz,
CSR† = 1 Ω
Dropout voltage
Pass-element series resistance
Input regulation
Output regulation
PG hysteresis voltage
MAX
3
V
145
mV
390
Ω
1.56
mV
mV
41
dB
45
µV/√Hz
2
CO = 4.7 µF
256
CO = 10 µF
206
CO = 100 µF
132
µVrms
50
VI = 4 V
UNIT
mV
VI = 2.55 V
IPG = 1.2 mA
0.25
V
PG output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TEST CONDITIONS‡
PARAMETER
TPS7233Y
MIN
TYP
Output voltage
VI = 4.3 V,
VI = 3.23 V,
IO = 10 mA
IO = 10 mA
3.3
Dropout voltage
VI = 3.23 V,
VI = 3.23 V,
IO = 100 mA
IO = 250 mA
140
(3.23 V – VO)/IO,
IO = 250 mA
VI = 3.23 V,
VI = 4.3 V to 10 V,
4.3 V ≤ VI ≤ 10 V,
50 µA ≤ IO ≤ 250 mA
8
32
4.3 V ≤ VI ≤ 10 V,
IO = 5 mA to 250 mA
IO = 50 µA to 250 mA
Ripple rejection
VI = 4.3 V,,
f = 120 Hz
IO = 50 µA
IO = 250 mA
52
Output noise spectral density
VI = 4.3 V,
f = 120 Hz
Pass-element series resistance
Input regulation
Output regulation
Output noise voltage
PG hysteresis voltage
VI = 4.3 V,
10 Hz ≤ f ≤ 100 kHz,
CSR† = 1 Ω
UNIT
V
14
mV
360
1.5
41
44
2
CO = 4.7 µF
265
CO = 10 µF
212
CO = 100 µF
135
32
VI = 4.3 V
MAX
Ω
mV
mV
dB
µV/√Hz
µVrms
mV
VI = 2.8 V,
IPG = 1.2 mA
0.22
V
PG output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 µF (CSR† = 1 Ω), TJ = 25°C, SENSE shorted
to OUT (unless otherwise noted) (continued)
TEST CONDITIONS‡
PARAMETER
Output voltage
TPS7248Y
MIN
TYP
VI = 5.85 V,
VI = 4.75 V,
IO = 10 mA
IO = 10 mA
VI = 4.75 V,
VI = 4.75 V,
IO = 100 mA
IO = 250 mA
216
(4.75 V – VO)/IO,
IO = 250 mA
VI = 4.75 V,
0.8
5.85 V ≤ VI ≤ 10 V
IO = 5 mA to 250 mA
IO = 50 µA to 250 mA
43
5.85 V ≤ VI ≤ 10 V
Ripple rejection
VI = 5.85 V,,
f = 120 Hz
IO = 50 µA
IO = 250 mA
53
Output noise spectral density
VI = 5.85 V,
f = 120 Hz
Output noise voltage
VI = 5.85 V,
10 Hz ≤ f ≤ 100 kHz,
CSR† = 1 Ω
Dropout voltage
Pass-element series resistance
Output regulation
PG hysteresis voltage
MAX
4.85
UNIT
V
10
mV
90
Ω
mV
55
dB
46
µV/√Hz
2
CO = 4.7 µF
370
CO = 10 µF
290
CO = 100 µF
168
µVrms
50
VI = 5.85 V
mV
VI = 4.12 V
IPG = 1.2 mA
0.2
V
PG output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
TEST CONDITIONS‡
PARAMETER
TPS7250Y
MIN
TYP
Output voltage
VI = 6 V,
VI = 4.88 V
IO = 10 mA
IO = 10 mA
5
Dropout voltage
VI = 4.88 V
VI = 4.88 V,
IO = 100 mA
IO = 250 mA
76
190
(4.88 V – VO)/IO,
IO = 250 mA
VI = 4.88 V,
0.76
VI = 6 V to 10 V,
6 V ≤ VI ≤ 10 V,
50 µA ≤ IO ≤ 250 mA
Pass-element series resistance
Input regulation
6 V ≤ VI ≤ 10 V,
Ripple rejection
VI = 6 V,,
f = 120 Hz
IO = 50 µA
IO = 250 mA
52
Output noise spectral density
VI = 6 V,
f = 120 Hz
PG hysteresis voltage
VI = 6 V,
10 Hz ≤ f ≤ 100 kHz,
CSR† = 1 Ω
59
46
2
CO = 4.7 µF
390
CO = 10 µF
300
CO = 100 µF
175
50
VI = 6 V
V
mV
Ω
mV
46
Output noise voltage
UNIT
8
IO = 5 mA to 250 mA
IO = 50 µA to 250 mA
Output regulation
MAX
mV
dB
µV/√Hz
µVrms
mV
VI = 4.25 V,
IPG = 1.2 mA
0.19
V
PG output low voltage
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
‡ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output current
5
vs Input voltage
6
IQ
Quiescent current
∆IQ†
Change in quiescent current
vs Free-air temperature
7
VDO
∆VDO
Dropout voltage
vs Output current
8
Change in dropout voltage
vs Free-air temperature
9
VDO
rDS(on)
Dropout voltage (TPS7201 only)
vs Output current
10
Pass-element series resistance
vs Input voltage
11
∆VO
VO
Change in output voltage
vs Free-air temperature
12
Output voltage
vs Input voltage
13
Line regulation
(TPS7201, TPS7233, TPS7248, TPS7250)
14
Load regulation
(TPS7225, TPS7233, TPS7248, TPS7250)
15
VO(PG)
Power-good (PG) voltage
vs Output voltage
16
rDS(on)PG
Power-good (PG) on-resistance
vs Input voltage
17
VI
Minimum input voltage for valid PG
vs Free-air temperature
18
Output voltage response from enable (EN)
19
Load transient response (TPS7201/ TPS7233)
20
Load transient response (TPS7248/ TPS7250)
21
Line transient response (TPS7201)
22
Line transient response (TPS7233)
23
Line transient response (TPS7248/ TPS7250)
24
Ripple rejection
vs Frequency
25
Output Spectral Noise Density
vs Frequency
26
vs Output current (CO = 4.7 µF)
27
vs Added ceramic capacitance (CO = 4.7 µF)
28
vs Output current (CO = 10 µF)
29
vs Added ceramic capacitance (CO = 10 µF)
30
Compensation series resistance (CSR)
† This symbol is not currently listed within EIA or JEDEC standards for semiconductor symbology.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
vs
OUTPUT CURRENT
QUIESCENT CURRENT
vs
INPUT VOLTAGE
230
250
TA = 25°C
TPS7233
200
210
200
TPS7233 VI = 10 V
190
TPS7250 VI = 10 V
180
TPS7248 VI = 5.85 V
I Q – Quiescent Current – µ A
I Q – Quiescent Current – µ A
220
170
TPS7250 VI = 6.0 V
160
150
150
TPS7201 With
VO Programmed to 2.5 V
100
TPS7250
50
TPS7233 VI = 4.3 V
0
50
100
150
200
IO – Output Current – mA
0
250
0
1
2
Figure 5
9
10
600
IO = 10 mA
VI = VO + 1 V
TA = 25°C
500
30
VDO – Dropout Voltage – mV
∆I Q – Change in Quiescent Current – µ A
8
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
50
40
3
4
5
6
7
VI – Input Voltage – V
Figure 6
CHANGE IN QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
20
10
0
– 10
– 20
TPS7225
400
TPS7230
300
TPS7233
TPS7248
200
100
TPS7250
– 30
– 40
– 40 – 20
0
20
40 60
80 100 120 140
TA – Free-Air Temperature – °C
0
0
50
100
150
200
IO – Output Current – mA
Figure 8
Figure 7
18
TPS7248
TA 25°C
IO = 250 mA
TPS7248 VI = 10 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
250
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TPS7201
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
CHANGE IN DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
1.6
0.04
VI = 2.4 V†
1.4
TPS7230
0.03
VDO – Dropout Voltage – V
TPS7233
0.02
0.01
TPS7248/TPS7250
0
– 0.01
– 0.02
1.2
VI = 2.9 V
1
VI = 2.6 V†
VI = 3.2 V
VI = 3.9 V
0.8
VI = 5.9 V
0.6
VI = 9.65 V
0.4
0.2
– 0.03
– 0.04
– 40 – 20
0
0
20
40
60 80 100 120 140
TA – Free-Air Temperature – °C
0
50
100
150
200
IO – Output Current – mA
250
† This voltage is not recommended.
Figure 10
Figure 9
CHANGE IN OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
PASS ELEMENT SERIES RESISTANCE
vs
INPUT VOLTAGE
15
6
TA = 25°C
VFB = 1.12 V
∆VO – Change in Output Voltage – mV
r DS(on) – Pass Element Series Resistance – Ω
∆VDO – Change in Dropout Voltage – V
0.05
5
4
IO = 250 mA
3
2
1
IO = 100 mA
0
2
3
4
5
6
7
8
9
10
IO = 10 mA
VI = VO + 1 V
10
5
0
–5
– 10
– 15
– 20
– 25
– 40 – 20
VI – Input Voltage – V
0
20 40
60
80 100 120 140
TA – Free-Air Temperature – °C
Figure 12
Figure 11
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
LINE REGULATION
5.5
25
5
TPS7250
TPS7248
4.5
∆VO – Output Voltage – V
∆VO – Change in Output Voltage – mV
TA = 25°C
IO = 250 mA
4
3.5
TPS7233
3
2.5
2
TPS7201 With
VO Programmed to 2.5 V
1.5
1
15
TPS7201 With
VO Programmed to 2.5 V
10
5
TPS7233
0
–5
TPS7248
– 10
– 15
TPS7250
– 20
0.5
0
TA = 25°C
IO = 250 mA
20
0
1
2
3
4
5
6
7
8
9
– 25
10
4
4.5
VI – Input Voltage – V
6 6.5 7 7.5 8 8.5 9
VI – Input Voltage – V
Figure 13
Figure 14
6
TA = 25°C
PG Pulled Up to VI With 5 kΩ Resistor
TA = 25°C
VO(PG) – Power-Good (PG) Voltage – V
40
∆VO – Change in Output Voltage – mV
9.5 10
POWER-GOOD (PG) VOLTAGE
vs
OUTPUT VOLTAGE†
LOAD REGULATION
50
30
20
10
TPS7233
0
– 10
TPS7225
– 20
TPS7250
– 50
0
50
100
150
200
IO – Output Current – mA
VI
ÁÁ
ÁÁ
TPS7248
– 30
– 40
250
GND
0
92
93
94
95
Figure 16
POST OFFICE BOX 655303
96
VO – Output Voltage – %
† VO as a percent of VOnom.
Figure 15
20
5 5.5
• DALLAS, TEXAS 75265
97
98
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
MINIMUM INPUT VOLTAGE FOR VALID PG
vs
FREE-AIR TEMPERATURE
POWER-GOOD (PG) ON-RESISTANCE
vs
INPUT VOLTAGE
1.3
VI – Minimum Input Voltage for Valid PG
TA = 25°C
10
1
1.125
1.12
1.115
1.11
1.105
ÁÁ
1.095
– 40 – 20
0
1.5
2
2.5
3
3.5
4
4.5
5
0
20
40
60
80
100 120 140
TA – Free-Air Temperature – °C
VI – Input Voltage – V
Figure 18
Figure 17
OUTPUT VOLTAGE RESPONSE FROM
ENABLE (EN)
10
TA = 25°C
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
5
0
VO nom
V I(EN)– EN Voltage – V
1
1.1
VO – Output Voltage – V
(Values Vary With
Selection of Device)
rDS(on) – Power-Good (PG) On-Resistance – kΩ
100
0
50
100
150
t – Time – µs
Figure 19
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
LOAD TRANSIENT RESPONSE
200
100
0
TA = 25°C
VI = 6 V
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– 100
– 200
105
55
5
0
100
200
300
400
500
I O – Output Current – mA
∆VO – Change in Output Voltage – mV
TPS7201 (WITH VO PROGRAMMED TO 2.5 V), TPS7233
t – Time – µs
Figure 20
200
100
0
TA = 25°C
VI = 6 V
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– 100
– 200
105
55
5
0
100
200
300
400
t – Time – µs
Figure 21
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
500
I O – Output Current – mA
∆VO – Change in Output Voltage – mV
TPS7248/TPS7250
LOAD TRANSIENT RESPONSE
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TPS7201 WITH VO PROGRAMMED TO 2.5 V
LINE TRANSIENT RESPONSE
100
50
0
– 50
– 100
TA = 25°C
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
6.5
6.25
6
0
100
200
300
VI – Input Voltage – V
∆VO – Change in Output Voltage – mV
TYPICAL CHARACTERISTICS
400
t – Time – µs
Figure 22
200
100
0
– 50
TA = 25°C
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– 100
6.5
6.25
6
0
100
200
300
400
5.75
500
V I – Input Voltage – V
∆VO – Change in Output Voltage – mV
TPS7233
LINE TRANSIENT RESPONSE
t – Time – µs
Figure 23
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
100
50
0
– 50
TA = 25°C
CI = 0
CO = 4.7 µF (CSR = 1 Ω)
– 100
6.5
6.25
6
0
100
200
300
400
500
V I – Input Voltage – V
∆VO – Change in Output Voltage – mV
TPS7248/TPS7250
LINE TRANSIENT RESPONSE
t – Time – µs
Figure 24
RIPPLE REJECTION
vs
FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
60
TPS7233
TPS7248/
TPS7250
Output Spectral Noise Density – µV/ Hz
Ripple Rejection – dB
50
40
10
TA = 25°C
No Input
Capacitance Added
VI = VO + 1 V
IO = 100 mA
CO = 4.7 µF (CSR = 1 Ω)
TPS7201 With
VO Programmed
to 2.5 V
30
20
10
0
10
100
1K
10 K
100 K
1M
10 M
TA = 25°C
No Input Capacitance Added
VI = VO + 1 V
CO = 4.7 µF (CSR = 1 Ω)
1
CO = 10 µF (CSR = 1 Ω)
0.1
CO = 100 µF (CSR = 1 Ω)
0.01
10
f – Frequency – Hz
Figure 25
24
100
1k
10 k
f – Frequency – Hz
Figure 26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100 k
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)†
vs
OUTPUT CURRENT
COMPENSATION SERIES RESISTANCE (CSR)†
vs
ADDED CERAMIC CAPACITANCE
100
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
100
Region of Instability
10
1
TA = 25°C
VI = VO + 1 V
CO = 4.7 µF
No Added Ceramic Capacitance
No Input Capacitance Added
0.1
Region of Instability
0.01
0
50
100
TA = 25°C
VI = VO + 1 V
IO = 250 mA
CO = 4.7 µF
No Input Capacitor Added
Region of
Instability
10
1
0.1
Region of Instability
0.01
150
200
0
250
0.1
0.2 0.3 0.4 0.5
Figure 27
0.9
1
Figure 28
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)†
vs
OUTPUT CURRENT
COMPENSATION SERIES RESISTANCE (CSR)†
vs
ADDED CERAMIC CAPACITANCE
100
100
Region of Instability
CSR – Compensation Series Resistance – Ω
CSR – Compensation Series Resistance – Ω
0.6 0.7 0.8
Added Ceramic Capacitance – µF
IO – Output Current – mA
10
TA = 25°C
VI = VO + 1 V
CO = 10 µF
No Added Ceramic Capacitance
No Input Capacitor Added
1
0.1
Region of Instability
0.01
Region of
Instability
10
TA = 25°C
VI = VO + 1 V
IO = 250 mA
CO = 10 µF
No Input Capacitor Added
1
0.1
Region of Instability
0.01
0
50
100
150
200
250
IO – Output Current – mA
0
0.1
0.2 0.3 0.4 0.5
0.6 0.7 0.8
0.9
1
Added Ceramic Capacitance – µF
Figure 29
Figure 30
† CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
APPLICATION INFORMATION
The design of the TPS72xx family of low-dropout (LDO) regulators is based on the higher-current TPS71xx
family. These new families of regulators have been optimized for use in battery-operated equipment and feature
extremely low dropout voltages, low supply currents that remain constant over the full-output-current range of
the device, and an enable input to reduce supply currents to less than 0.5 µA when the regulator is turned off.
device operation
The TPS72xx uses a PMOS pass element to dramatically reduce both dropout voltage and supply current over
more conventional PNP-pass-element LDO designs. The PMOS transistor is a voltage-controlled device that,
unlike a PNP transistor, does not require increased drive current as output current increases. Supply current
in the TPS72xx is essentially constant from no-load to maximum.
Current limiting and thermal protection prevent damage by excessive output current and/or power dissipation.
The device switches into a constant-current mode at approximately 1 A; further load increases reduce the output
voltage instead of increasing the output current. The thermal protection shuts the regulator off if the junction
temperature rises above 165°C. Recovery is automatic when the junction temperature drops approximately 5°C
below the high temperature trip point. The PMOS pass element includes a back diode that safely conducts
reverse current when the input voltage level drops below the output voltage level.
A logic high on the enable input, EN, shuts off the output and reduces the supply current to less than 0.5 µA.
EN should be grounded in applications where the shutdown feature is not used.
Power good (PG) is an open-drain output signal used to indicate output-voltage status. A comparator circuit
continuously monitors the output voltage. When the output drops to approximately 95% of its nominal regulated
value, the comparator turns on and pulls PG low.
Transient loads or line pulses can also cause activation of PG if proper care is not taken in selecting the input
and output capacitors. Load transients that are faster than 5 µs can cause a signal on PG if high-ESR output
capacitors (greater than approximately 7 Ω) are used. A 1-µs transient causes a PG signal when using an output
capacitor with greater than 3.5 Ω of ESR. It is interesting to note that the output-voltage spike during the transient
can drop well below the reset threshold and still not trip if the transient duration is short. A 1-µs transient must
drop at least 500 mV below the threshold before tripping the PG circuit. A 2-µs transient trips PG at just 400 mV
below the threshold. Lower-ESR output capacitors help by reducing the drop in output voltage during a transient
and should be used when fast transients are expected.
A typical application circuit is shown in Figure 31.
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
APPLICATION INFORMATION
TPS72xx
(see Note A)
5
VI
IN
PG
6
PG
1
250 kΩ
SENSE
IN
OUT
C1
0.1 µF
2
4
OUT
EN
7
VO
8
+
GND
3
10 µF
CSR = 1 Ω
NOTE A: TPS7225, TPS7230, TPS7233, TPS7248, TPS7250
(fixed-voltage options).
Figure 31. Typical Application Circuit
external capacitor requirements
Although not required, a 0.047-µF to 0.1-µF ceramic bypass input capacitor, connected between IN and GND
and located close to the TPS72xx, is recommended to improve transient response and noise rejection. A
higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated
and the device is located several inches from the power source.
An output capacitor is required to stabilize the internal feedback loop. For most applications, a 10-µF to 15-µF
solid-tantalum capacitor with a 0.5-Ω resistor (see capacitor selection table) in series is sufficient. The maximum
capacitor ESR should be limited to 1.3 Ω to allow for ESR doubling at cold temperatures. Figure 32 shows the
transient response of a 5-mA to 85-mA load using a 10-µF output capacitor with a total ESR of 1.7 Ω.
A 4.7-µF solid-tantalum capacitor in series with a 1-Ω resistor may also be used (see Figures 27 and 28)
provided the ESR of the capacitor does not exceed 1 Ω at room temperature and 2 Ω over the full operating
temperature range.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
APPLICATION INFORMATION
VI = VO + 1 V
VO
1→
IO = 85 mA
IO = 5 mA
2→
Ch1
Ch 2
50 mV
50 mA
100 µs/div
Figure 32. Load Transient Response (CSR total = 1.7 Ω), TPS7248Q
A partial listing of surface-mount capacitors usable with the TPS72xx family is provided below. This information
(along with the stability graphs, Figures 27 through 30) is included to assist the designer in selecting suitable
capacitors.
CAPACITOR SELECTION
SIZE (H × L × W)†
MFR.
VALUE
MAX ESR†
592D156X0020R2T
Sprague
15 µF, 20 V
1.1
1.2 × 7.2 × 6
595D156X0025C2T
Sprague
15 µF, 25 V
1
2.5 × 7.1 × 3.2
595D106X0025C2T
Sprague
10 µF, 25 V
1.2
2.5 × 7.1 × 3.2
695D106X0035G2T
Sprague
10 µF, 35 V
1.3
2.5 × 7.6 × 2.5
PART NO.
† Size is in mm. ESR is maximum resistance in ohms at 100 kHz and TA = 25°C. Listings are sorted by height.
sense-pin connection
SENSE must be connected to OUT for proper operation of the regulator. Normally this connection should be
as short as possible; however, remote sense may be implemented in critical applications when proper care of
the circuit path is exercised. SENSE internally connects to a high-impedance wide-bandwidth amplifier through
a resistor-divider network, and any noise pickup on the PCB trace will feed through to the regulator output.
SENSE must be routed to minimize noise pickup. Filtering SENSE using an RC network is not recommended
because of the possibility of inducing regulator instability.
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
APPLICATION INFORMATION
output voltage programming
The output voltage of the TPS7201 adjustable regulator is programmed using an external resistor divider as
shown in Figure 33. The output voltage is calculated using:
V
O
ǒ Ǔ
+ Vref @ 1 ) R1
R2
(1)
Where:
Vref = 1.188 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 7-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 169 kΩ to set the divider current at 7 µA and then calculate R1 using:
R1
+
ǒ Ǔ
V
V
O
ref
* 1 @ R2
(2)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
OUTPUT
VOLTAGE
(V)
TPS7201
5
DIVIDER RESISTANCE
(kΩ)†
R1
R2
2.5
191
169
3.3
309
169
3.6
348
169
4
402
169
5
549
169
6.4
750
169
>2.7 V
VI
0.1 µF
6
IN
PG
IN
OUT
4
EN
OUT
2
8
Power-Good Indicator
250 kΩ
7
<0.4 V
VO
R1
FB
1
GND
3
+
10 µF
CSR = 1 Ω
R2
† 1% values shown.
Figure 33. TPS7201 Adjustable LDO Regulator Programming
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
APPLICATION INFORMATION
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
allowable to avoid damaging the device is 150°C. These restrictions limit the power dissipation that the regulator
can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate
the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal
to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
P
T max * T
J
A
+
D(max)
R
qJA
Where:
TJmax is the maximum allowable junction temperature, i.e.,150°C absolute maximum and 125°C
recommended operating temperature.
RθJA is the thermal resistance junction-to-ambient for the package, i.e., 172°C/W for the 8-terminal
SOIC and 238°C/W for the 8-terminal TSSOP.
TA is the ambient temperature.
ǒ
Ǔ
The regulator dissipation is calculated using:
P
D
+ VI * VO @ IO
Power dissipation resulting from quiescent current is negligible.
regulator protection
The TPS72xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the
input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be
appropriate.
The TPS72xx also features internal current limiting and thermal protection. During normal operation, the
TPS72xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator
operation resumes.
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
MECHANICAL DATA
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040082 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS7201Q, TPS7225Q, TPS7230Q
TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102G – MARCH 1995 – REVISED JUNE 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
0,75
0,50
A
Seating Plane
0,15
0,05
1,20 MAX
0,10
PINS **
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064 / E 08/96
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS7201QD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7201QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7201QDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7201QDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7201QP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7201QPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7201QPW
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7201QPWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7201QPWLE
OBSOLETE
TSSOP
PW
8
TPS7201QPWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7201QPWRG4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7225QD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7225QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7225QDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7225QDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7225QP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7225QPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7225QPWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7225QPWRG4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7230QD
ACTIVE
SOIC
D
8
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7230QDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7230QDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7230QP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7230QPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7230QPWR
ACTIVE
TSSOP
PW
8
CU NIPDAU
Level-1-260C-UNLIM
TBD
75
2000 Green (RoHS &
no Sb/Br)
Addendum-Page 1
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS7230QPWRG4
ACTIVE
TSSOP
PW
8
TPS7233QD
ACTIVE
SOIC
D
8
75
TPS7233QDG4
ACTIVE
SOIC
D
8
75
TPS7233QDR
ACTIVE
SOIC
D
TPS7233QDRG4
ACTIVE
SOIC
TPS7233QP
ACTIVE
TPS7233QPE4
2000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7233QPW
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7233QPWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7233QPWLE
OBSOLETE
TSSOP
PW
8
TPS7233QPWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7233QPWRG4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7248QD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7248QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7248QDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7248QDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7248QP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7248QPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7248QPW
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7248QPWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7248QPWLE
OBSOLETE
TSSOP
PW
8
TPS7248QPWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7248QPWRG4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7250QD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7250QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7250QDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7250QDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
TBD
TBD
Addendum-Page 2
Call TI
Call TI
Call TI
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS7250QP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7250QPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TPS7250QPWLE
OBSOLETE
TSSOP
PW
8
TBD
Call TI
TPS7250QPWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS7250QPWRG4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
IMPORTANT NOTICE
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