SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 D Recommended Amplifiers: FEATURES D 14-Bit Resolution D 125MSPS Sample Rate D High SNR: 70.5dBFS at 100MHz fIN D High SFDR: 82dBc at 100MHz fIN D 2.3VPP Differential Input Voltage D Internal Voltage Reference D 3.3V Single-Supply Voltage D Analog Power Dissipation: 578mW D D OPA695, OPA847, THS3201, THS3202, THS4503, THS9001 APPLICATIONS D Wireless Communication − Communication Receivers − Base Station Infrastructure Test and Measurement Instrumentation Single and Multichannel Digital Receivers D D D Communication Instrumentation − Total Power Dissipation: 780mW Serial Programming Interface TQFP-64 PowerPADE Package − Radar, Infrared D Video and Imaging D Medical Equipment DESCRIPTION The ADS5500 is a high-performance, 14-bit, 125MSPS analog-to-digital converter (ADC). To provide a complete converter solution, it includes a high-bandwidth linear sample-and-hold stage (S&H) and internal reference. Designed for applications demanding the highest speed and highest dynamic performance in very little space, the ADS5500 has excellent power consumption of 780mW at 3.3V single-supply voltage. This allows an even higher system integration density. The provided internal reference simplifies system design requirements. Parallel CMOScompatible output ensures seamless interfacing with common logic. The ADS5500 is available in a 64-pin TQFP PowerPAD package and is specified over the full temperature range of −40°C to +85°C. DRVDD AVDD CLK+ VIN+ S&H VIN− CM CLKOUT Timing Circuitry CLK− 14−Bit Pipeline ADC Core Output Control Serial Programming Register ADS5500 SCLK DRGND SEN SDATA D0 . . . D13 OVR DFS Control Logic Internal Reference AGND Digital Error Correction Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright 2003−2004, Texas Instruments Incorporated ! " #$ " %$&# '( '$#" #! "%##" % ) !" *" "$!" "'' +,( '$# %#"" '" #"", #$' " %!"( www.ti.com www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 PACKAGE/ORDERING INFORMATION(1) PRODUCT PACKAGE−LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS5500 HTQFP-64(2) PowerPAD PAP −40°C to +85°C ADS5500I ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS5500IPAP Tray, 160 ADS5500IPAPR Tape and Reel, 1000 (1) For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet. (2) Thermal pad size: 3.5mm x 3.5mm (min), 4mm x 4mm (max). ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ADS5500 UNIT −0.3 to +3.7 V ±0.1 V Analog input to AGND −0.15 to +2.5 V Logic input to DRGND −0.3 to DRVDD + 0.3 V Digital data output to DRGND −0.3 to DRVDD + 0.3 V 30 mA PARAMETER −40 to +85 °C Supplies +105 °C °C Supply Voltage AVDD to AGND, DRVDD to DRGND AGND to DRGND Input current (any input) Operating temperature range Junction temperature Storage temperature range −65 to +150 (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT Analog supply voltage, AVDD 3.0 3.3 3.6 V Output driver supply voltage, DRVDD 3.0 3.3 3.6 V 1.6 VPP V Analog Input Differential input range 2.3 Input common-mode voltage, VCM(1) Digital Output 1.5 Maximum output load 10 pF Clock Input ADCLK input sample rate (sine wave) 1/tC DLL ON 60 125 MSPS DLL OFF 10 80 MSPS Clock amplitude, sine wave, differential(2) 3 Clock duty cycle(3) 50 Open free-air temperature range −40 +85 (1) Input common-mode should be connected to CM. (2) See Figure 13 for more information. (3) See Figure 12 for more information. 2 VPP % °C www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 ELECTRICAL CHARACTERISTICS Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 125MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted. CONDITIONS PARAMETER MIN Resolution TYP MAX UNIT 14 Tested Bits 2.3 VPP kΩ Analog Inputs Differential input range Differential input impedance See Figure 4 Differential input capacitance See Figure 4 6.6 Total analog input common-mode current Analog input bandwidth Source impedance = 50Ω 4 pF 4(1) mA 750 MHz Conversion Characteristics Maximum sample rate Data latency see note (2) See timing diagram, Figure 1 125 MSPS 16.5 Clock Cycles Reference bottom voltage, VREFM 0.97 V Reference top voltage, VREFP 2.11 Internal Reference Voltages Reference error −4 ±0.9 V +4 1.55 ± 0.05 Common-mode voltage output, VCM % V Dynamic DC Characteristics and Accuracy No missing codes Differential linearity error, DNL Integral linearity error, INL Tested fIN = 10MHz fIN = 10MHz −0.9 ±0.75 +1.1 LSB −5 ±2.5 +5 LSB ±1.5 mV Offset temperature coefficient 0.0007 %/°C Gain error ±0.45 %FS Gain temperature coefficient 0.01 ∆%/°C 70.5 71.5 dBFS 69 71.5 dBFS 71.5 dBFS Offset error Dynamic AC Characteristics fIN = 10MHz Room temp Full temp range fIN = 30MHz fIN = 55MHz Signal-to-noise ratio, SNR RMS Output noise 71.5 dBFS 70 71.2 dBFS 68.5 71 dBFS fIN = 100MHz fIN = 150MHz 70.5 dBFS 70.1 dBFS fIN = 225MHz Input tied to common-mode 69.1 dBFS 1.1 LSB fIN = 70MHz fIN = 10MHz Room temp Full temp range Room temp 82 84 dBc Full temp range 78 84 dBc 84 dBc 79 dBc fIN = 30MHz fIN = 55MHz Spurious-free dynamic range, SFDR Room temp 80 83 dBc Full temp range 77 82 dBc fIN = 100MHz fIN = 150MHz 82 dBc 78 dBc fIN = 225MHz 74 dBc fIN = 70MHz (1) 2mA per input. (2) See Reccommended Operating Conditions on page 2. 3 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 ELECTRICAL CHARACTERISTICS (continued) Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 125MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER CONDITIONS fIN = 10MHz MIN TYP Room temp 82 91 dBc Full temp range 78 86 dBc 86 dBc 84 dBc fIN = 30MHz fIN = 55MHz Second-harmonic, HD2 80 87 dBc Full temp range 77 83 dBc fIN = 100MHz fIN = 150MHz 84 dBc 78 dBc fIN = 225MHz 74 dBc fIN = 70MHz Room temp 82 89 dBc Full temp range 78 88 dBc 90 dBc 79 dBc fIN = 30MHz fIN = 55MHz Worst-harmonic/spur (other than HD2 and HD3) fIN = 70MHz Room temp 80 85 dBc Full temp range 77 82 dBc fIN = 100MHz fIN = 150MHz 82 dBc 80 dBc fIN = 225MHz fIN = 10MHz Room temp 76 dBc 88 dBc fIN = 70MHz 86 dBc 69 70 dBc 67.5 70 dBc fIN = 10MHz Room temp Room temp Full temp range fIN = 30MHz fIN = 55MHz Signal-to-noise + distortion, SINAD 70 dBc 69.5 dBc 68.5 69 dBc 67 69.5 dBc fIN = 100MHz fIN = 150MHz 69 dBc 69 dBc fIN = 225MHz 66.4 dBc fIN = 70MHz Room temp Full temp range Room temp 80 85 dBc Full temp range 78 83 dBc 82 dBc 77 dBc 77.5 81 dBc 76 79.5 dBc fIN = 100MHz fIN = 150MHz 79 dBc 75 dBc fIN = 225MHz 71.8 dBc fIN = 10MHz fIN = 30MHz fIN = 55MHz Total harmonic distortion, THD 4 UNIT Room temp fIN = 10MHz Third-harmonic, HD3 MAX fIN = 70MHz Room temp Full temp range www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 ELECTRICAL CHARACTERISTICS (continued) Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 125MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER CONDITIONS Effective number of bits, ENOB MIN fIN = 70MHz f = 10.1MHz, 15.1MHz (−7dBFS each tone) Two-tone intermodulation distortion, IMD TYP MAX UNIT 11.3 Bits 85 dBc f = 30.1MHz, 35.1MHz (−7dBFS each tone) 85 dBc f = 50.1MHz, 55.1MHz (−7dBFS each tone) 88 dBc Power Supply VIN = full-scale, fIN = 55MHz AVDD = DRVDD = 3.3V VIN = full-scale, fIN = 55MHz AVDD = DRVDD = 3.3V Total supply current, ICC Analog supply current, IAVDD VIN = full-scale, fIN = 55MHz AVDD = DRVDD = 3.3V Analog only Output buffer supply current, IDRVDD 236 265 mA 175 190 mA 61 75 mA 578 627 mW Power dissipation Total power with 10pF load on digital output to ground 780 875 mW Standby power With clocks running 181 250 mW DIGITAL CHARACTERISTICS Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 125MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT Digital Inputs High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 10 µA 10 µA Low-level input current Input current for RESET Input capacitance Digital Outputs(1) Low-level output voltage High-level output voltage Output capacitance CLOAD = 10pF(2), fS = 125MSPS CLOAD = 10pF(2), fS = 125MSPS −20 µA 4 pF 0.3 V 3.0 V 3 pF (1) For optimal performance, all digital output lines (D0:D13), including the output clock, should see a similar load. (2) Equivalent capacitance to ground of (load + parasitics of transmission lines). 5 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 TIMING CHARACTERISTCS Analog Input Signal Sample N N + 1 N + 4 N + 3 N + 2 N + 15 N + 16 N + 17 tPDI tA Input Clock t SETUP Output Clock tHOLD N − 17 N − 16 Data Out (D0−D13) N − 15 N − 13 N−3 N−2 N−1 N Data Invalid 16.5 Clock Cycles NOTE: It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the above timing matches closely with the specified values. Figure 1. Timing Diagram TIMING CHARACTERISTICS Typ, min, and max values at TA = +25°C, full temperature range is TMIN = −40°C to tMAX = +85°C, sampling rate = 125MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3V, DLL On, −1dBFS differential input, and 3VPP differential clock, unless otherwise noted. PARAMETER DESCRIPTION MIN TYP MAX UNIT Switching Specification Aperture delay, tA Input CLK falling edge to data sampling point Aperture jitter (uncertainty) Uncertainty in sampling instant Data setup time, tSETUP Data valid to 50% of CLKOUT rising edge Data hold time, tHOLD 1 ns 300 fs 2 ns CLKOUT rising edge to data becoming invalid 1.7 ns Data latency, tD(Pipe) Input clock falling edge (on which sampling takes place) to input clock rising edge (on which the corresponding data is given out) 16.5 Clock Cycles Propagation delay, tPDI Input clock rising edge to data valid 7.5 ns Data rise time Data out 20% to 80% 2.5 ns Data fall time Data out 80% to 20% 2.5 ns 2 ms Output enable (OE) to output stable delay SERIAL PROGRAMMING INTERFACE CHARACTERISTICS The device has a three-wire serial interface. The device latches the serial data SDATA on the falling edge of serial clock SCLK when SEN is active. D Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at falling edge. D Minimum width of data stream for a valid loading is 16 clocks. 6 D Data is loaded at every 16th SCLK falling edge while SEN is low. D In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. D Data can be loaded in multiple of 16-bit words within a single active SEN pulse. www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 A3 SDATA A2 A1 A0 D11 D10 ADDRESS D9 D0 DATA MSB Figure 2. DATA Communication is 2-Byte, MSB First tSLOADS tSLOADH SEN tWSCLK tWSCLK tSCLK SCLK t OS SDATA t OH MSB LSB MSB LSB 16 x M Figure 3. Serial Programming Interface Timing Diagram Table 1. Serial Programming Interface Timing Characteristics SYMBOL PARAMETER MIN(1) tSCLK SCLK Period 50 TYP(1) MAX(1) UNIT ns tWSCLK SCLK Duty Cycle 25 tSLOADS SEN to SCLK setup time 8 50 75 ns % tSLOADH SCLK to SEN hold time 6 ns tDS Data Setup Time 8 ns tDH Data Hold Time 6 ns (1) Min, typ, and max values are characterized, but not production tested. Table 2. Serial Register Table A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 DLL OFF 0 DLL OFF = 0 : internal DLL is on, recommended for 60−125MSPS clock speed DLL OFF = 1 : internal DLL is off, recommended for 10−80MSPS clock speed DESCRIPTION 1 1 1 0 0 TP<1> TP<0> 0 0 0 0 0 0 0 0 0 TP<1:0> − Test modes for output data capture TP<1> = 0, TP<0> = 0 : Normal mode of operation, TP<1> = 0 TP<0> = 1 : All output lines are pulled to ’0’, TP<1> = 1 TP<0> = 0 : All output lines are pulled to ’1’, TP<1> = 1 TP<0> = 1 : A continuous stream of ’10’ comes out on all output lines 1 1 1 1 PDN 0 0 0 0 0 0 0 0 0 0 0 PDN = 0 : Normal mode of operation, PDN = 1 : Device is put in power down (low current) mode 7 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 Table 3. DATA FORMAT SELECT (DFS TABLE) DFS-PIN VOLTAGE (VDFS) DATA FORMAT CLOCK OUTPUT POLARITY 1 6 Straight Binary Data valid on rising edge V DFS t AV DD 5 12 1 AV DD u V DFS u 3 AV DD Two’s Complement Data valid on rising edge 2 3 7 AV DD u V DFS u 12 AV DD Straight Binary Data valid on falling edge Two’s Complement Data valid on falling edge V DFS u 5 6 AV DD PIN CONFIGURATION 8 55 54 53 52 51 50 DRVDD 56 DRGND D4 57 D5 58 D6 59 D7 60 D8 D10 61 D9 D11 62 DRGND D12 63 DRVDD D13 (MSB) 64 DRGND OVR PAP PACKAGE (TOP VIEW) 49 DRGND 1 48 DRGND SCLK 2 47 D3 SDATA 3 46 D2 SEN 4 45 D1 AVDD 5 44 D0 (LSB) AGND 6 43 CLKOUT AVDD 7 AGND 8 AVDD 9 42 DRGND ADS5500 PowerPAD 41 OE 40 DFS (Connected to Analog Ground) 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AGND 18 AGND 17 IREF 33 AVDD REFM AGND 16 REFP 34 AVDD AVDD AVDD 15 AGND 35 RESET AVDD AGND 14 AGND 36 AGND AVDD AGND 13 AGND 37 AVDD AVDD AGND 12 INM 38 AGND INP CLKM 11 AGND 39 AVDD CM CLKP 10 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 PIN ASSIGNMENTS TERMINAL NO. NAME NO. OF PINS I/O AVDD 5, 7, 9, 15, 22, 24, 26, 28, 33, 34, 37, 39 12 I Analog power supply AGND 6, 8, 12, 13, 14, 16, 18, 21, 23, 25, 27, 32, 36, 38 14 I Analog ground DRVDD 49, 58 2 I Output driver power supply DRGND 1, 42, 48, 50, 57, 59 6 I Output driver ground INP 19 1 I Differential analog input (positive) INM 20 1 I Differential analog input (negative) REFP 29 1 O Reference voltage (positive); 0.1µF capacitor in series with a 1Ω resistor to GND REFM 30 1 O Reference voltage (negative); 0.1µF capacitor in series with a 1Ω resistor to GND IREF 31 1 I Current set; 56kΩ resistor to GND; do not connect capacitors CM 17 1 O Common-mode output voltage RESET 35 1 I Reset (active high), 200kΩ resistor to AVDD OE 41 1 I Output enable (active high) DFS 40 1 I Data format and clock out polarity select(1) CLKP 10 1 I Data converter differential input clock (positive) CLKM 11 1 I Data converter differential input clock (negative) SEN 4 1 I Serial interface chip select SDATA 3 1 I Serial interface data SCLK 2 1 I Serial interface clock 44−47, 51−56, 60−63 14 O Parallel data output OVR 64 1 O Over-range indicator bit CLKOUT 43 1 O CMOS clock out in sync with data D0 (LSB)−D13 (MSB) DESCRIPTION NOTE: PowerPAD is connected to analog ground. (1) The DFS pin is programmable to four discrete voltage levels: 0, 3/8 AVDD, 5/8 AVDD, and AVDD. The thresholds are centered. More details are listed in Table 3 on page 8. 9 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 DEFINITION OF SPECIFICATIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3dB. Aperture Delay The delay in time between the falling edge of the input sampling clock and the actual time at which the sampling occurs. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse Width/Duty Cycle A perfect differential sine wave clock results in a 50% clock duty cycle on the internal coversion clock. Pulse width high is the minimum amount of time that the ENCODE pulse should be left in logic ‘1’ state to achieve rated performance. Pulse width low is the minimum time that the ENCODE pulse should be left in a low state (logic ‘0’). At a given clock rate, these specifications define an acceptable clock duty cycle. Integral Nonlinearity (INL) INL is the deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” or “best fit” determined by a least square curve fit. INL is independent from effects of offset, gain or quantization errors. Maximum Conversion Rate The encode rate at which parametric testing is performed. This is the maximum sampling rate where certified operation is given. Minimum Conversion Rate This is the minimum sampling rate where the ADC still works. Nyquist Sampling When the sampled frequencies of the analog input signal are below fCLOCK/2, it is called Nyquist sampling. The Nyquist frequency is fCLOCK/2, which can vary depending on the sample rate (fCLOCK). Offset Error Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation of any single LSB transition at the digital output from an ideal 1 LSB step at the analog input. If a device claims to have no missing codes, it means that all possible codes (for a 14-bit converter, 16384 codes) are present over the full operating range. Effective Number of Bits (ENOB) The effective number of bits for a sine wave input at a given input frequency can be calculated directly from its measured SINAD using the following formula: ENOB + SINAD * 1.76 6.02 If SINAD is not known, SNR can be used exceptionally to calculate ENOB (ENOBSNR). Effective Resolution Bandwidth The highest input frequency where the SNR (dB) is dropped by 3dB for a full-scale input amplitude. Gain Error The amount of deviation between the ideal transfer function and the measured transfer function (with the offset error removed) when a full-scale analog input voltage is applied to the ADC, resulting in all 1s in the digital code. Gain error is usually given in LSB or as a percent of full-scale range (%FSR). 10 Offset error is the deviation of output code from mid-code when both inputs are tied to common-mode. Propagation Delay This is the delay between the input clock rising edge and the time when all data bits are within valid logic levels. Signal-to-Noise and Distortion (SINAD) The RMS value of the sine wave fIN (input sine wave for an ADC) to the RMS value of the noise of the converter from DC to the Nyquist frequency, including harmonic content. It is typically expressed in decibels (dB). SINAD includes harmonics, but excludes DC. SINAD + 20Log (10) Input(VS ) Noise ) Harmonics Signal-to-Noise Ratio (without harmonics) SNR is a measure of signal strength relative to background noise. The ratio is usually measured in dB. If the incoming signal strength in µV is VS, and the noise level (also in µV) is VN, then the SNR in dB is given by the formula: SNR + 20Log (10) VS VN This is the ratio of the RMS signal amplitude, VS (set 1dB below full-scale), to the RMS value of the sum of all other spectral components, VN, excluding harmonics and DC. www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 Spurious-Free Dynamic Range (SFDR) The ratio of the RMS value of the analog input sine wave to the RMS value of the peak spur observed in the frequency domain. It may be reported in dBc (that is, it degrades as signal levels are lowered), or in dBFS (always related back to converter full-scale). The peak spurious component may or may not be a harmonic. Temperature Drift Temperature drift (for offset error and gain error) specifies the maximum change from the initial temperature value to the value at TMIN or TMAX. Total Harmonic Distortion (THD) THD is the ratio of the RMS signal amplitude of the input sine wave to the RMS value of distortion appearing at multiples (harmonics) of the input, typically given in dBc. Two-Tone Intermodulation Distortion Rejection The ratio of the RMS value of either input tone (f1, f2) to the RMS value of the worst third-order intermodulation product (2f1 − f2; 2f2 − f1). It is reported in dBc. 11 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V, differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted. 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 SPECTRAL PERFORMANCE (FFT for 15MHz Input Signal) SFDR = 84.0dBc SNR = 71.2dBFS THD = 84.0dBc SINAD = 71.0dBFS Amplitude (dB) Amplitude (dB) SPECTRAL PERFORMANCE (FFT for 2MHz Input Signal) 40 50 60 Frequency (MHz) 0 10 20 Amplitude (dB) Amplitude (dB) 30 40 50 60 Frequency (MHz) 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 62.5 10 20 0 10 40 Amplitude (dB) 12 20 30 40 50 60 50 60 Frequency (MHz) Amplitude (dB) 30 Frequency (MHz) 50 60 62.5 10 60 SPECTRAL PERFORMANCE (FFT for 100MHz Input Signal) SFDR = 84.4dBc SNR = 71.2dBFS THD = 81.3dBc SINAD = 70.9dBFS 0 50 SFDR = 85.1dBc SNR = 71.4dBFS THD = 83.6dBc SINAD = 71.1dBFS SPECTRAL PERFORMANCE (FFT for 80MHz Input Signal) 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 40 SPECTRAL PERFORMANCE (FFT for 70MHz Input Signal) SFDR = 81.0dBc SNR = 71.2dBFS THD = 80.2dBc SINAD = 70.7dBFS 0 30 Frequency (MHz) SPECTRAL PERFORMANCE (FFT for 60MHz Input Signal) 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 20 62.5 30 62.5 20 SFDR = 84.8dBc SNR = 71.5dBFS THD = 83.2dBc SINAD = 71.2dBFS 62.5 10 62.5 0 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 SFDR = 84.3dBc SNR = 71.1dBFS THD = 81.6dBc SINAD = 70.7dBFS 0 10 20 30 40 Frequency (MHz) www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V, differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted. 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 SPECTRAL PERFORMANCE (FFT for 225MHz Input Signal) SFDR = 77.8dBc SNR = 70.0dBFS THD = 75.3dBc SINAD = 69.0dBFS 20 30 40 50 60 Frequency (MHz) SFDR = 73.0dBc SNR = 69.1dBFS THD = 70.0dBc SINAD = 66.5dBFS 0 10 40 50 60 TWO−TONE INTERMODULATION 0 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 SFDR = 67.4dBc SNR = 68.0dBFS THD = 64.7dBc SINAD = 63.0dBFS f1 = 10.1MHz, −7dBFS f2 = 15.1MHz, −7dBFS 2−tone IMD = 88.0dBc −20 −40 Power (dBFS) Amplitude (dB) 30 Frequency (MHz) SPECTRAL PERFORMANCE (FFT for 300MHz Input Signal) −60 −80 −100 −120 −140 30 40 50 60 Frequency (MHz) 0 10 20 30 40 50 60 60 62.5 20 62.5 10 62.5 0 Frequency (MHz) TWO−TONE INTERMODULATION TWO−TONE INTERMODULATION 0 0 f1 = 30.1MHz, −7dBFS f2 = 35.1MHz, −7dBFS 2−tone IMD = 87.0dBc − 20 f 1 = 50.1MHz, −7dBFS f 2 = 55.1MHz, −7dBFS 2−tone IMD = 89.0dBc −20 −40 Power (dBFS) − 40 Power (dBFS) 20 62.5 10 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 62.5 0 Amplitude (dB) Amplitude (dB) SPECTRAL PERFORMANCE (FFT for 150MHz Input Signal) − 60 − 80 −60 −80 −100 −100 −120 −120 −140 −140 10 20 30 40 Frequency (MHz) 50 60 62.5 0 0 10 20 30 40 Frequency (MHz) 50 13 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V, differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted. DIFFERENTIAL NONLINEARITY (DNL) INTEGRAL NONLINEARITY (INL) f S = 125MSPS f IN = 10MHz AIN = −0.5dBFS Code Code SIGNAL−TO−NOISE RATIO vs INPUT FREQUENCY 90 76 85 74 80 72 SNR (dBFS) SFDR (dBc) SPURIOUS−FREE DYNAMIC RANGE vs INPUT FREQUENCY 75 70 65 70 68 66 64 60 f S = 125MSPS DLL On 55 f S = 125MSPS DLL On 62 60 50 0 50 100 150 200 250 0 300 50 85 85 SNR (dBFS) SFDR (dBc) SNR (dBFS) SFDR (dBc) 90 SFDR 75 SNR 70 fS = 125MSPS fIN = 150MHz DRVDD = 3.3V 65 150 200 250 300 AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE AC PERFORMANCE vs ANALOG SUPPLY VOLTAGE 90 80 100 Input Frequency (MHz) Input Frequency (MHz) SFDR 80 75 SNR 70 fS = 125MSPS fIN = 70MHz DRVDD = 3.3V 65 60 60 3.0 3.1 3.2 3.3 AVDD (V) 14 16384 16384 10240 8192 6144 4096 2048 0 −1.50 14336 −1.25 12288 f S = 125MSPS f IN = 10MHz AIN = −0.5dBFS −1.00 14336 −0.75 12288 −0.50 10240 0 −0.25 0 LSB LSB 0.50 0.25 8192 0.75 6144 1.00 4096 1.25 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 −0.5 −1.0 −1.5 −2.0 −2.5 −3.0 −3.5 −4.0 2048 1.50 3.4 3.5 3.6 3.0 3.1 3.2 3.3 AVDD (V) 3.4 3.5 3.6 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V, differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted. AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE AC PERFORMANCE vs DIGITAL SUPPLY VOLTAGE 79 84 78 SFDR 82 SFDR 77 80 SNR (dBFS) SFDR (dBc) SNR (dBFS) SFDR (dBc) 76 fS = 125MSPS fIN = 150MHz AVDD = 3.3V 75 74 73 72 fS = 125MSPS fIN = 70MHz AVDD = 3.3V 78 76 74 71 SNR 72 70 SNR 70 69 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.0 3.1 3.2 DRVDD (V) POWER DISSIPATION vs SAMPLE RATE 3.5 3.6 POWER DISSIPATION vs SAMPLING FREQUENCY AVDD = DRVDD = 3.3V fIN = 150MHz f IN = 70MHz 750 Power Dissipation (mW) 800 Power Dissipation (mW) 3.4 800 850 750 700 650 600 DLL On 700 650 DLL Off 600 550 550 500 10 30 50 70 90 110 130 10 150 20 30 40 50 60 70 80 90 100 110 120 125 500 Sampling Frequency (MSPS) Sample Rate (MSPS) SIGNAL−TO−NOISE RATIO AND SPURIOUS−FREE DYNAMIC RANGE vs TEMPERATURE AC PERFORMANCE vs INPUT AMPLITUDE 90 90 SNR (dBFS) 80 70 AC Performance (dB) 85 SFDR SNR (dBFS) SFDR (dBc) 3.3 DRVDD (V) 80 75 SNR 70 fS = 125MSPS fIN = 70MHz DLL On 65 0 50 40 SFDR (dBc) 30 20 SNR (dBc) 10 0 fS = 125MSPS fIN = 70MHz DLL On −10 −20 60 −40 60 25 Temperature (_C) 40 85 −30 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 Input Amplitude (dBFS) 15 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V, differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted. AC PERFORMANCE vs INPUT AMPLITUDE AC PERFORMANCE vs INPUT AMPLITUDE 90 90 SNR (dBFS) 80 70 60 AC Performance (dB) AC Performance (dB) SNR (dBFS) 80 70 SFDR (dBc) 50 40 30 SNR (dBc) 20 10 0 fS = 125MSPS fIN = 150MHz DLL On −10 −20 −30 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 60 SFDR (dBc) 50 40 SNR (dBc) 30 20 10 0 f S = 125MSPS f IN = 220MHz DLL On −10 −20 −30 0 −90 −80 −70 Input Amplitude (dBFS) 35 85 30 80 SNR (dBFS) SFDR (dBc) 90 25 20 15 fS = 125MSPS fIN = 70MHz 0 0.5 1.0 WCDMA TONE fS = 150MSPS fIN = 125MHz −40 −60 −80 −100 −120 −140 10 20 1.5 2.0 Differential Clock Amplitude (V) 0 Amplitude (dB) 0 SNR 8222 8221 8220 8219 8218 8217 8216 8215 8214 50 8213 0 8212 55 8211 5 8210 −10 65 60 8209 −20 70 Output Code 30 40 Frequency (MHz) 16 −30 SFDR 75 10 0 −40 AC PERFORMANCE vs CLOCK AMPLITUDE 40 −20 −50 Input Amplitude (dBFS) OUTPUT NOISE HISTOGRAM Occurrence (%) −60 50 60 2.5 3.0 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V, differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted. SIGNAL−TO−NOISE RATIO (SNR) WITH DLL ON 73 150 71 140 71 72 69 130 71 71 110 69 72 70 70 100 90 69 72 80 73 70 69 68 71 68 69 73 68 70 60 70 72 67 69 50 SNR (dB) Sample Frequency (MSPS) 120 71 72 40 0 69 50 100 150 67 68 200 250 66 300 Input Frequency (MHz) SIGNAL−TO−NOISE RATIO (SNR) WITH DLL OFF 80 71 69 70 72 73 70 72 73 70 69 50 70 71 68 68 67 66 40 72 SNR (dB) Sample Frequency (MSPS) 60 73 30 64 68 69 73 67 66 70 20 65 71 71 69 72 64 67 63 68 62 10 0 50 100 62 66 150 200 250 60 300 Input Frequency (MHz) 17 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V, differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted. SPURIOUS−FREE DYNAMIC RANGE (SFDR) WITH DLL ON 150 83 77 140 71 80 80 68 85 130 83 83 110 74 77 77 86 80 83 86 100 71 80 68 90 86 75 80 77 83 SFDR (dBc) Sample Frequency (MSPS) 120 74 89 70 60 83 86 89 70 80 71 86 68 83 50 77 74 65 40 0 50 100 150 Input Frequency (MHz) 200 250 300 SPURIOUS−FREE DYNAMIC RANGE (SFDR) WITH DLL OFF 88 80 78 88 86 80 70 84 84 88 86 86 82 84 76 88 60 74 82 86 72 50 78 80 80 70 68 78 76 86 40 86 76 82 74 74 30 72 72 84 88 20 80 86 70 78 84 76 74 82 70 68 68 72 70 66 10 0 50 100 150 Input Frequency (MHz) 18 200 250 300 SFDR (dBc) Sample Frequency (MSPS) 70 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V, differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted. SECOND HARMONIC (HD2) WITH DLL ON 150 83 86 140 98 89 130 92 89 100 92 89 80 77 80 83 83 68 95 98 70 74 86 92 89 85 71 89 80 90 83 86 95 86 98 90 77 80 89 86 92 95 74 92 120 Sample Frequency (MSPS) 92 86 86 110 68 80 71 89 89 77 83 86 77 86 89 HD2 (dBc) 86 95 74 71 75 60 92 98 95 92 50 92 70 83 68 98 95 89 95 86 80 77 74 71 40 65 0 50 100 150 200 250 300 Input Frequency (MHz) SECOND HARMONIC (HD2) WITH DLL OFF 90 87 84 93 70 95 93 96 99 96 78 60 Sample Frequency (MSPS) 68 81 90 75 99 87 50 93 99 40 85 68 81 99 99 80 90 96 78 75 99 30 84 72 HD2 (dBc) 80 72 87 75 84 81 93 20 68 78 84 70 72 87 75 10 0 50 100 150 200 250 300 Input Frequency (MHz) 19 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 TYPICAL CHARACTERISTICS (continued) Typical values are at TA = 25°C, AVDD = DRVDD = 3.3V, differential input amplitude = −1dBFS, sampling rate = 125MSPS, and DLL On, unless otherwise noted. THIRD HARMONIC (HD3) WITH DLL ON 150 83 77 80 89 140 71 74 68 90 86 86 130 86 83 85 86 89 83 110 80 77 86 71 77 74 80 77 100 80 86 90 83 83 86 89 80 75 92 89 70 86 86 92 60 HD3 (dBc) 120 70 86 50 83 83 89 86 89 40 65 0 50 100 150 200 250 300 Input Frequency (MHz) THIRD HARMONIC (HD3) WITH DLL OFF 80 87 90 87 84 90 90 70 81 78 84 78 87 72 75 50 40 80 78 84 81 87 75 30 75 87 84 90 20 72 84 81 78 70 81 84 10 0 50 100 72 75 87 150 Input Frequency (MHz) 200 72 250 300 HD3 (dBc) Sample Frequency (MSPS) 60 20 85 84 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 APPLICATION INFORMATION in a data latency of 16.5 clock cycles, after which the output data is available as a 14-bit parallel word, coded in either straight offset binary or binary two’s complement format. INPUT CONFIGURATION The analog input for the ADS5500 consists of a differential sample-and-hold architecture implemented using a switched capacitor technique, shown in Figure 4. SAMPLE W 3a PHASE SAMPLE PHASE SWITCH THEORY OF OPERATION The ADS5500 is a low-power, 14-bit, 125MSPS, CMOS, switched capacitor, pipeline ADC that operates from a single 3.3V supply. The conversion process is initiated by a falling edge of the external input clock. Once the signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results W1a L1 R1a C1a INP CP1 CP3 L2 SWITCH SAMPLE W2 PHASE R1b R3 SWITCH CACROSS C1b VINCM 1V INM W1b SAMPLE PHASE CP4 SAMPLE W 3a PHASE SWITCH CP2 L1, L2 : 6nh to 10nh effective R1a, R1b : 25Ω to 35Ω C1a, C1b : 2.2pF to 2.6pF CP1, CP2 : 2.5pF to 3.5pF CP3, CP4, : 1.2pF to 1.8pF CACROSS : 0.8pF to 1.2pF R3 : 80Ω to 120Ω Switches: W1a, W1b : On Resistance: 25Ωto 35Ω W2 : On Resistance: 7.5Ω to 15Ω W3a, W3b : On Resistance: 40Ωto 60Ω W1a, W1b, W2, W3a, W3b : Off Resistance: 1e10 All switches are on in sample phase. Approximately half of every clock period is a sample phase. Figure 4. Analog Input Stage 21 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 This differential input topology produces a high level of AC performance for high sampling rates. It also results in a very high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersampling applications. The ADS5500 requires each of the analog inputs (INP, INM) to be externally biased around the common-mode level of the internal circuitry (CM, pin 17). For a full-scale differential input, each of the differential lines of the input signal (pins 19 and 20) swings symmetrically between CM + 0.575V and CM – 0.575V. This means that each input is driven with a signal of up to CM ± 0.575V, so that each input has a maximum differential signal of 1.15VPP for a total differential input signal swing of 2.3VPP. The maximum swing is determined by the two reference voltages, the top reference (REFP, pin 29), and the bottom reference (REFM, pin 30). The ADS5500 obtains optimum performance when the analog inputs are driven differentially. The circuit shown in Figure 5 shows one possible configuration using an RF transformer. R0 50Ω Z0 50Ω INP 1:1 R 50Ω AC Signal Source ADS5500 INM ADT1−1WT CM 10Ω 1nF 0.1µF Figure 5. Transformer Input to Convert Single-Ended Signal to Differential Signal The single-ended signal is fed to the primary winding of an RF transformer. Since the input signal must be biased around the common-mode voltage of the internal circuitry, the common-mode voltage (VCM) from the ADS5500 is connected to the center-tap of the secondary winding. To ensure a steady low-noise VCM reference, best performance is obtained when the CM (pin 17) output is filtered to ground with 0.1µF and 0.01µF low-inductance capacitors. Output VCM (pin 17) is designed to directly drive the ADC input. When providing a custom CM level, be aware that the input structure of the ADC sinks a common-mode current in the order of 4mA (2mA per input). Equation (1) describes the dependency of the common-mode current and the sampling frequency: 22 4mA f s 125MSPS (1) Where: fS > 60MSPS. This equation helps to design the output capability and impedance of the driving circuit accordingly. When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combine single-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier without a transformer, to drive the input of the ADS5500. TI offers a wide selection of single-ended operational amplifiers (including the THS3201, THS3202, OPA847, and OPA695) that can be selected depending on the application. An RF gain block amplifier, such as TI’s THS9001, can also be used with an RF transformer for very high input frequency applications. The THS4503 is a recommended differential input/output amplifier. Table 4 lists the recommended amplifiers. When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA847, or OPA695) to provide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RF transformer and one amplifier in each of the legs of the secondary driving the two differential inputs of the ADS5500. These three amplifier circuits minimize even-order harmonics. For very high frequency inputs, an RF gain block amplifier can be used to drive a transformer primary; in this case, the transformer secondary connections can drive the input of the ADS5500 directly, as shown in Figure 5, or with the addition of the filter circuit shown in Figure 6. Figure 6 illustrates how RIN and CIN can be placed to isolate the signal source from the switching inputs of the ADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended that these components be included in the ADS5500 circuit layout when any of the amplifier circuits discussed previously are used. The components allow fine-tuning of the circuit performance. Any mismatch between the differential lines of the ADS5500 input produces a degradation in performance at high input frequencies, mainly characterized by an increase in the even-order harmonics. In this case, special care should be taken to keep as much electrical symmetry as possible between both inputs. Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers that can simplify the driver circuit for applications requiring DC coupling of the input. Flexible in their configurations (see Figure 7), such amplifiers can be used for singleended-to-differential conversion, signal amplification. www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 Table 4. Recommended Amplifiers to Drive the Input of the ADS5500 INPUT SIGNAL FREQUENCY RECOMMENDED AMPLIFIER TYPE OF AMPLIFIER DC to 20MHz THS4503 Differential In/Out Amp No DC to 50MHz OPA847 Operational Amp Yes OPA695 Operational Amp Yes 10MHz to 120MHz THS3201 Operational Amp Yes THS3202 Operational Amp Yes THS9001 RF Gain Block Yes Over 100MHz USE WITH TRANSFORMER? +5V −5V RS 100Ω VIN 0.1µF RIN 1:1 OPA695 INP RT 100Ω 1000pF R1 400Ω RIN CIN ADS5500 INM CM R2 57.5Ω AV = 8V/V (18dB) 10Ω 0.1µF Figure 6. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer RS RG RF +5V RT +3.3V 10µF 0.1µF R IN INP VOCM R IN ADS5500 14−Bit/125MSPS INM 1µF THS4503 10µF CM 0.1µF 10Ω RG −5V RF 0.1µF Figure 7. Using the THS4503 with the ADS5500 23 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 POWER SUPPLY SEQUENCE CLOCK INPUT The ADS5500 requires a power-up sequence where the DRVDD supply must be at least 0.4V by the time the AVDD supply reaches 3.0V. Powering up both supplies at the same time will work without any problem. If this sequence is not followed, the device may stay in power-down mode. The ADS5500 clock input can be driven with either a differential clock signal or a single-ended clock input, with little or no difference in performance between both configurations. The common-mode voltage of the clock inputs is set internally to CM (pin 17) using internal 5kΩ resistors that connect CLKP (pin 10) and CLKM (pin 11) to CM (pin 17), as shown in Figure 9. POWER DOWN The device will enter power-down in one of two ways: either by reducing the clock speed to between DC and 1MHz, or by setting a bit through the serial programming interface. Using the reduced clock speed, the power-down may be initiated for clock frequencies below 10MHz. For clock frequencies between 1MHz and 10Mhz, this can vary from device to device, but will power-down for clock speeds below 1MHz. The device can be powered down by programming the internal register (see Serial Programming Interface section). The outputs become tri-stated and only the internal reference is powered up to shorten the power-up time. The Power-Down mode reduces power dissipation to a minimum of 180mW. CM CM 5kΩ 5kΩ CLKP CLKM 6pF 3pF 3pF REFERENCE CIRCUIT The ADS5500 has built-in internal reference generation, requiring no external circuitry on the printed circuit board (PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1µF decoupling capacitor in series with a 1Ω resistor, as shown in Figure 8. In addition, an external 56.2kΩ resistor should be connected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, as shown in Figure 8. No capacitor should be connected between pin 31 and ground; only the 56.2kΩ resistor should be used. Figure 9. Clock Inputs When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a 0.01µF capacitor, while CLKP is AC-coupled with a 0.01µF capacitor to the clock source, as shown in Figure 10. Square Wave or Sine Wave (3VPP) 0.01µF CLKP ADS5500 CLKM 0.01µF 1Ω 29 REFP 30 REFM 1µF 1Ω 1µF 31 IREF 56kΩ Figure 8. REFP, REFM, and IREF Connections for Optimum Performance 24 Figure 10. AC-Coupled, Single-Ended Clock Input The ADS5500 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In this case, it is best to connect both clock inputs to the differential input clock signal with 0.01µF capacitors, as shown in Figure 11. www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 amplitudes without exceeding the supply rails and absolute maximum ratings of the ADC clock input. Figure 13 shows the performance variation of the device versus input clock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, refer to the ADS5500EVM User’s Guide (SLWU010), available for download from www.ti.com. 0.01µF CLKP Differential Square Wave or Sine Wave (3VPP) ADS5500 0.01µF CLKM Figure 11. AC-Coupled, Differential Clock Input AC PERFORMANCE vs CLOCK AMPLITUDE 90 SFDR 85 80 SNR (dBFS) SFDR (dBc) For high input frequency sampling, it is recommended to use a clock source with very low jitter. Additionally, the internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% duty cycle should be provided. Figure 12 shows the performance variation of the ADC versus clock duty cycle. 75 SNR 70 65 60 fS = 125MSPS fIN = 70MHz 55 90 fS = 125MSPS fIN = 20MHz SNR (dBFS) SFDR (dBc) 85 50 0 SFDR 0.5 1.0 1.5 2.0 2.5 3.0 Differential Clock Amplitude (V) 80 Figure 13. AC Performance vs Clock Amplitude 75 SNR INTERNAL DLL 70 65 60 30 35 40 45 50 55 60 65 70 Clock Duty Cycle (%) Figure 12. AC Performance vs Clock Duty Cycle Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. When using a sinusoidal clock, the clock jitter will further improve as the amplitude is increased. In that sense, using a differential clock allows for the use of larger In order to obtain the fastest sampling rates achievable with the ADS5500, the device uses an internal digital phase lock loop (DLL). Nevertheless, the limited frequency range of operation of DLL degrades the performance at clock frequencies below 60MSPS. In order to operate the device below 60MSPS, the internal DLL must be shut off using the DLL OFF mode described in the Serial Interface Programming section. The Typical Performance Curves show the performance obtained in both modes of operation: DLL ON (default), and DLL OFF. In either of the two modes, the device will enter power down mode if no clock or slow clock is provided. The limit of the clock frequency where the device will function properly is ensured to be over 10MHz. 25 www.ti.com SBAS303C − DECEMBER 2003 − REVISED MARCH 2004 OUTPUT INFORMATION SERIAL PROGRAMMING INTERFACE The ADC provides 14 data outputs (D13 to D0, with D13 being the MSB and D0 the LSB), a data-ready signal (CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals 1 when the output reaches the full-scale limits. The ADS5500 has internal registers for the programming of some of the modes described in the previous sections. The registers should be reset after power-up by applying a 2µs (minimum) high pulse on RESET (pin 35); this also resets the entire ADC and sets the data outputs to low. This pin has a 200kΩ internal pull-up resistor to AVDD. The programming is done through a three-wire interface. The timing diagram and serial register setting in the Serial Programing Interface section describe the programming of this register. Two different output formats (straight offset binary or two’s complement) and two different output clock polarities (latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to one of four different voltages. Table 3 details the four modes. In addition, output enable control (OE, pin 41, active high) is provided to tri-state the outputs. The output circuitry of the ADS5500 has being designed to minimize the noise produced by the transients of the data switching, and in particular its coupling to the ADC analog circuitry. Output D4 (pin 51) senses the load capacitance and adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in the timing diagram of Figure 1, as long as all outputs (including CLKOUT) have a similar load as the one at D4 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply voltage or temperature. External series resistors with the output are not necessary. 26 Table 2 shows the different modes and the bit values to be written on the register to enable them. Note that some of these modes may modify the standard operation of the device and possibly vary the performance with respect to the typical data shown in this data sheet. PACKAGE OPTION ADDENDUM www.ti.com 29-Oct-2004 PACKAGING INFORMATION ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY ADS5500IPAP ACTIVE HTQFP PAP 64 160 ADS5500IPAPR ACTIVE HTQFP PAP 64 1000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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