Revised May 2005
74ABT16245
16-Bit Transceiver with 3-STATE Outputs
General Description
Features
The ABT16245 contains sixteen non-inverting bidirectional
buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each
byte has separate control inputs which can be shorted
together for full 16-bit operation. The T/R inputs determine
the direction of data flow through the device. The OE inputs
disable both the A and B ports by placing them in a high
impedance state.
■ Bidirectional non-inverting buffers
■ Separate control logic for each byte
■ 16-bit version of the ABT245
■ A and B output sink capability of 64 mA, source
capability of 32 mA
■ Guaranteed output skew
■ Guaranteed multiple output switching specifications
■ Output switching specified for both 50 pF and
250 pF loads
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Non-destructive hot insertion capability
Ordering Code:
Order Number
Package Number
74ABT16245CSSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Description
74ABT16245CMTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
T/Rn
Transmit/Receive Input
A0–A15
Side A Inputs/Outputs
B0–B15
Side B Inputs/Outputs
© 2005 Fairchild Semiconductor Corporation
DS010986
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74ABT16245 16-Bit Transceiver with 3-STATE Outputs
April 1992
74ABT16245
Truth Tables
Inputs
OE1
Logic Diagrams
Outputs
T/R1
L
L
Bus B0–B7 Data to Bus A0–A7
L
H
Bus A0–A7 Data to Bus B0–B7
H
X
HIGH-Z State on A0–A7, B0–B 7
Inputs
OE2
Outputs
T/R2
L
L
Bus B8–B15 Data to Bus A8–A 15
L
H
Bus A8–A15 Data to Bus B8–B 15
H
X
HIGH-Z State on A8–A15, B8–B 15
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Functional Description
The ABT16245 contains sixteen non-inverting bidirectional
buffers with 3-STATE outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. The control pins can be shorted together to
obtain full 16-bit operation.
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2
Recommended Operating
Conditions
65qC to 150qC
55qC to 125qC
55qC to 150qC
0.5V to 7.0V
0.5V to 7.0V
30 mA to 5.0 mA
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
40qC to 85qC
4.5V to 5.5V
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate ('V/'t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Voltage Applied to Any Output
in the Disabled or
0.5V to 5.5V
0.5V to VCC
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
twice the rated IOL (mA)
500 mA
DC Latchup Source Current
Over Voltage Latchup (I/O)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
10V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VCC
Conditions
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
1.2
V
Min
IIN
VOH
Output HIGH Voltage
2.5
V
Min
IOH
2.0
V
Min
IOH
32 mA (An, Bn)
0.55
V
Min
IOL
64 mA (An, Bn)
1
PA
Max
VOL
Output LOW Voltage
IIH
Input HIGH Current
2.0
V
Recognized HIGH Signal
Recognized LOW Signal
1
3 mA (An, Bn)
VIN
2.7V (OEn, T/Rn) (Note 3)
VIN
VCC (OE n, T/Rn)
7
PA
Max
VIN
7.0V (OEn, T/Rn)
Input HIGH Current Breakdown Test (I/O)
100
PA
Max
VIN
5.5V (An, Bn)
Input LOW Current
1
PA
Max
VIN
0.5V (OEn, T/Rn) (Note 3)
IBVI
Input HIGH Current Breakdown Test
IBVIT
IIL
1
VID
18 mA (OEn, T/Rn)
Input Leakage Test
4.75
V
0.0
VIN
0.0V (OEn, T/Rn)
IID
1.9 PA (OEn, T/Rn)
All Other Pins Grounded
IIH I OZH Output Leakage Current
10
PA
0 5.5V VOUT
2.7V (An, Bn); OE
2.0V
IIL I OZL Output Leakage Current
10
PA
0 5.5V VOUT
0.5V (An, Bn); OE
2.0V
275
mA
Max
VOUT
0.0V (An, Bn)
100
IOS
Output Short-Circuit Current
ICEX
Output HIGH Leakage Current
50
PA
Max
VOUT
VCC (An, Bn)
IZZ
Bus Drainage Test
100
PA
0.0
VOUT
5.50V (An, Bn);
All Others GND
ICCH
Power Supply Current
100
PA
Max
All Outputs HIGH
ICCL
Power Supply Current
60
mA
Max
All Outputs LOW
ICCZ
Power Supply Current
100
PA
Max
OE n
VCC, T/Rn
GND or VCC
All others at V CC or GND
ICCT
Additional ICC/Input
Outputs Enabled
2.5
mA
Outputs 3-STATE
2.5
mA
Outputs 3-STATE
50
PA
VI
Max
VCC 2.1V
OE n, T/ Rn VI
VCC 2.1V
Data Input V I
VCC 2.1V
All others at V CC or GND
ICCD
Dynamic ICC
No Load
mA/
(Note 3)
0.1
MHz
Max
Outputs OPEN
OE n
GND, T/Rn
GND or VCC
One Bit Toggling, 50% Duty Cycle
Note 3: Guaranteed, but not tested.
3
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74ABT16245
Absolute Maximum Ratings(Note 1)
74ABT16245
DC Extended Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
VCC
0.5
0.9
V
Conditions
500:
CL
50 pF; RL
5.0
TA
25qC (Note 4)
VOLP
Quiet Output Maximum Dynamic VOL
VOLV
Quiet Output Minimum Dynamic VOL
1.4
1.0
V
5.0
TA
25qC (Note 4)
VOHV
Minimum HIGH Level Dynamic Output Voltage
2.5
3.0
V
5.0
TA
25qC (Note 5)
VIHD
Minimum HIGH Level Dynamic Input Voltage
2.0
1.4
V
5.0
TA
25qC (Note 5)
VILD
Maximum LOW Level Dynamic Input Voltage
V
5.0
TA
25qC (Note 6)
1.2
0.8
Note 4: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 5: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 6: Max number of data inputs (n) switching. n 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ).
Guaranteed, but not tested.
AC Electrical Characteristics
25qC
TA
Symbol
VCC
Parameter
CL
55qC to 125qC
TA
5V
VCC
50 pF
4.5V – 5.5V
CL
TA
40qC to 85qC
VCC
50 pF
4.5V – 5.5V
CL
50 pF
Min
Typ
Max
Min
Max
Min
tPLH
Propagation
1.0
2.4
3.9
0.5
4.5
1.0
3.9
tPHL
Delay Data to Outputs
1.0
2.8
3.9
0.5
5.2
1.0
3.9
tPZH
Output Enable
1.5
3.6
6.3
0.8
6.4
1.5
6.3
tPZL
Time
1.5
3.7
6.3
0.9
6.9
1.5
6.3
tPHZ
Output Disable
1.3
4.6
6.9
1.3
6.9
1.3
6.9
tPLZ
Time
1.3
3.7
6.9
1.0
6.9
1.3
6.9
Units
Max
ns
ns
ns
Extended AC Electrical Characteristics
TA 40qC to 85qC
VCC
Symbol
CL
Parameter
TA
4.5V–5.5V
40qC to 85qC
VCC
50 pF
CL
16 Outputs Switching
250 pF
1 Output Switching
(Note 7)
Min
4.5V–5.5V
TA
40qC to 85qC
VCC
CL
250 pF
(Note 9)
Max
Min
Max
Min
Max
fTOGGLE
Maximum Toggle Frequency
tPLH
Propagation Delay
1.5
5.0
1.5
6.0
2.5
8.0
tPHL
Data to Outputs
1.5
5.3
1.5
6.0
2.5
8.0
tPZH
Output Enable
1.5
6.5
2.5
8.2
2.5
10.0
1.5
6.5
2.5
8.2
2.5
9.0
Time
tPZL
Units
16 Outputs Switching
(Note 8)
Typ
4.5V–5.5V
100
MHz
tPHZ
Output Disable
1.0
6.9
tPLZ
Time
1.0
6.9
(Note 10)
(Note 10)
ns
ns
ns
Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only.
Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 10: 3-STATE delay are dominated by the RC network (500:, 250 pF) on the output and have been excluded from the datasheet.
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TA
40qC to 85qC
VCC
Symbol
Parameter
tOSHL
Pin to Pin Skew
(Note 13)
HL Transitions
tOSLH
Pin to Pin Skew
(Note 13)
LH Transitions
tPS
Duty Cycle
(Note 14)
LH–HL Skew
tOST
Pin to Pin Skew
(Note 13)
LH/HL Transitions
tPV
Device to Device Skew
(Note 15)
LH/HL Transitions
TA
4.5V–5.5V
50 pF
CL
40qC to 85qC
VCC
CL
4.5V–5.5V
250 pF
Units
16 Outputs Switching
16 Outputs Switching
(Note 11)
(Note 12)
Max
Max
1.3
1.5
ns
1.3
1.5
ns
1.5
2.0
ns
1.7
2.5
ns
2.0
3.0
ns
Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 12: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (tOSHL), LOW to HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGH-toLOW (tOST ). The specification is guaranteed but not tested.
Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not
tested.
Capacitance
Symbol
Parameter
CIN
Input Capacitance
CI/O (Note 16)
Output Capacitance
Note 16: CI/O is measured at frequency f
Conditions
Typ
Units
5
pF
V CC
0.0V (OEn, T/Rn)
11
pF
V CC
5.0V (An, Bn)
TA
25qC
1 MHz, per MIL-STD-883, Method 3012.
5
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74ABT16245
Skew
74ABT16245
AC Loading
*Includes jig and probe capacitance
FIGURE 2. Input Pulse Requirements
FIGURE 1. Standard AC Test Load
Amplitude
Rep. Rate
tW
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 6. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
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74ABT16245
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
7
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74ABT16245 16-Bit Transceiver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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