Revised November 1999 74ABT2541 Octal Buffer/Line Driver with 25Ω Series Resistors in the Outputs General Description Features The ABT2541 is an octal buffer and line driver designed to drive the capacitive inputs of MOS memory drivers, address drivers, clock drivers, and bus-oriented transmitters/receivers. Functionally identical to the ABT541. ■ Guaranteed output skew The 25Ω series resistors in the outputs reduce ringing and eliminate the need for external resistors. ■ Guaranteed simultaneously switching noise level and dynamic threshold performance ■ Guaranteed multiple output switching specifications ■ Output switching specified for both 50 pF and 250 pF loads ■ Guaranteed latchup protection ■ High impedance glitch free bus loading during entire power up and power down cycle ■ Nondestructive hot insertion capability ■ Disable time less than enable time to avoid bus contention Ordering Code: Order Number 74ABT2541CSC 74ABT2541CSJ Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT2541CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74ABT2541CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description OE1, OE2 Output Enable Input (Active LOW) I0–I7 Inputs O0–O7 Outputs Truth Table Schematic of Each Output Inputs OE1 OE2 I Outputs L L H H H X X Z X H X Z L L L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance © 1999 Fairchild Semiconductor Corporation DS011502 www.fairchildsemi.com 74ABT2541 Octal Buffer/Line Driver with 25Ω Series Resistors in the Outputs September 1992 74ABT2541 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA −40°C to +85°C +4.5V to +5.5V Minimum Input Edge Rate (∆V/∆t) Data Input 50 mV/ns Enable Input 20 mV/ns Voltage Applied to Any Output in the Disabled or Power-Off State −0.5V to 5.5V in the HIGH State −0.5V to VCC Current Applied to Output in LOW State (Max) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. twice the rated IOL (mA) −500 mA DC Latchup Source Current Over Voltage Latchup (I/O) Note 2: Either voltage limit or current limit is sufficient to protect inputs. 10V DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VCC V Conditions VIH Input HIGH Voltage Recognized HIGH Signal VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA VOH Output HIGH Voltage 2.5 V Min IOH = −3 mA 2.0 V Min IOH = −32 mA IOL = 15 mA Recognized LOW Signal VOL Output LOW Voltage 0.8 V Min IIH Input HIGH Current 1 µA Max IBVI Input HIGH Current 7 Breakdown Test IIL −1 Input LOW Current −1 4.75 VIN = 2.7V (Note 3) VIN = VCC 1 µA Max µA Max V 0.0 VIN = 7.0V VIN = 0.5V (Note 3) VIN = 0.0V IID = 1.9 µA VID Input Leakage Test IOZH Output Leakage Current 10 µA 0 − 5.5V IOZL Output Leakage Current −10 µA 0 − 5.5V IOS Output Short-Circuit Current −275 mA Max ICEX Output High Leakage Current 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.5V; All Others GND ICCH Power Supply Current 50 µA Max All Outputs HIGH ICCL Power Supply Current 30 mA Max All Outputs LOW ICCZ Power Supply Current 50 µA Max All Other Pins Grounded −100 VOUT = 2.7V; OEn = 2.0V VOUT = 0.5V; OEn = 2.0V VOUT = 0.0V OEn = VCC; All Others at VCC or GND ICCT Additional ICC/Input Outputs Enabled 2.5 mA Outputs 3-STATE 2.5 mA Outputs 3-STATE 50 µA VI = VCC − 2.1V Max Enable Input VI = VCC − 2.1V Data Input VI = VCC − 2.1V All Others at VCC or GND ICCD Dynamic ICC No Load mA/ (Note 4) 0.1 MHz Max Outputs OPEN OEn = GND (Note 3) One Bit Toggling, 50% Duty Cycle Note 3: Guaranteed, but not tested. Note 4: For 8 bit toggling, ICCD < 0.8 mA/MHz. www.fairchildsemi.com 2 (SOIC Package) Symbol Parameter Min Typ Max Units VCC 0.6 0.8 Conditions CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL V 5.0 TA = 25°C (Note 5) VOLV Quiet Output Minimum Dynamic VOL −0.5 −0.4 V 5.0 TA = 25°C (Note 5) VOHV Minimum HIGH Level Dynamic Output Voltage 2.7 3.1 V 5.0 TA = 25°C (Note 6) VIHD Minimum HIGH Level Dynamic Input Voltage 2.0 1.4 V 5.0 TA = 25°C (Note 7) VILD Maximum LOW Level Dynamic Input Voltage V 5.0 TA = 25°C (Note 7) 1.2 0.8 Note 5: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 6: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Note 7: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. AC Electrical Characteristics Symbol tPLH Parameter Propagation Delay Data to Outputs tPHL tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ TA = +25°C TA = −40°C to +85°C VCC = +5V VCC = 4.5V–5.5V CL = 50 pF CL = 50 pF Min Typ Max Min Max 1.0 2.3 3.6 1.0 3.6 1.0 3.3 4.1 1.0 4.1 1.5 3.7 6.0 1.5 6.0 1.5 4.3 6.5 1.5 6.5 1.0 3.5 6.0 1.0 6.0 1.0 3.7 5.6 1.0 5.6 Units ns ns ns Extended AC Electrical Characteristics (SOIC Package) Symbol −40°C to +85°C TA = −40°C to +85°C TA = −40°C to +85°C V CC = 4.5V–5.5V VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF CL = 250 pF 8 Outputs Switching 1 Output Switching 8 Outputs Switching Parameter (Note 8) Min (Note 9) Typ (Note 10) Max Min Max Min Max fTOGGLE Maximum Toggle Frequency tPLH Propagation Delay 1.5 5.0 1.5 6.0 2.5 8.5 tPHL Data to Outputs 1.5 5.5 1.5 10.0 2.5 11.0 tPZH Output Enable Time 1.5 6.5 2.5 7.5 2.5 9.5 1.5 7.0 2.5 11.0 2.5 12.5 1.0 6.0 1.0 6.0 tPZL tPHZ tPLZ Output Disable Time Units 100 MHz (Note 11) (Note 11) ns ns ns Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.). Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 11: The 3-STATE delays are dominated by the RC network (500Ω, 250 pF) on the output and have been excluded from the datasheet. 3 www.fairchildsemi.com 74ABT2541 DC Electrical Characteristics 74ABT2541 Skew (SOIC Package) Symbol TA = −40°C to +85°C TA = −40°C to +85°C VCC = 4.5V–5.5V VCC = 4.5V–5.5V CL = 50 pF CL = 250 pF 8 Outputs Switching 8 Outputs Switching (Note 12) (Note 13) Max Max 1.3 2.3 ns 1.0 1.8 ns 2.0 5.0 ns 2.0 5.0 ns 2.0 5.0 ns Parameter tOSHL Pin to Pin Skew (Note 14) HL Transitions tOSLH Pin to Pin Skew (Note 14) LH Transitions tPS Duty Cycle (Note 15) LH–HL Skew tOST Pin to Pin Skew (Note 14) LH/HL Transitions tPV Device to Device Skew (Note 16) LH/HL Transitions Units Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) Note 13: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW (tOSHL), LOW-to-HIGH (tOSLH), or any combination switching LOW-to-HIGH and/or HIGHto-LOW (tOST). The specification is guaranteed but not tested. Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested. Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and VCC) from device to device. This specification is guaranteed but not tested. Capacitance Symbol Parameter Typ Units Conditions TA = 25°C CIN Input Capacitance 5.0 pF VCC = 0V COUT (Note 17) Output Capacitance 9.0 pF VCC = 5.0V Note 17: COUT is measured at frequency f = 1 MHz; per MIL-STD-883, Method 3012. www.fairchildsemi.com 4 74ABT2541 AC Loading *Includes jig and probe capacitance. FIGURE 2. Test Input Signal Levels FIGURE 1. Standard AC Test Load Amplitude Rep. Rate tW tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times FIGURE 5. Propagation Delay, Pulse Width Waveforms FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms 5 www.fairchildsemi.com 74ABT2541 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Body Package Number M20B www.fairchildsemi.com 6 74ABT2541 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D 7 www.fairchildsemi.com 74ABT2541 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 www.fairchildsemi.com 8 74ABT2541 Octal Buffer/Line Driver with 25Ω Series Resistors in the Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com