TI THS4509RGTT

THS4509
www.ti.com
SLOS454 – JANUARY 2005
WIDEBAND, LOW NOISE, LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIER
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Fully Differential Architecture
Centered Input Common-mode Range
Minimum Gain of 2V/V (6 dB)
Bandwidth: 1900 MHz (100 mVpp, G = 10 dB,
RL = 200 Ω)
Slew Rate: 6600 V/µs (2V step, G = 10 dB)
1% Settling Time: 2 ns (2 V step, G = 10 dB)
HD2: –75 dBc at 100 MHz (2 Vpp, G = 10 dB,
RL = 1 kΩ)
HD3: –80 dBc at 100 MHz (2 Vpp, G = 10 dB,
RL = 1 kΩ)
OIP2: 79 dBm at 70 MHz (2 Vpp envelope,
G = 10 dB)
OIP3: 43 dBm at 70 MHz (2 Vpp envelope,
G = 10 dB)
Input Voltage Noise: 1.9 nV/√Hz (f >10 MHz)
Noise Figure: 17.1 dB (50 Ω System, G = 10
dB)
Output Common-Mode Control
Power Supply:
– Voltage: 3 V (±1.5 V) to 5 V (±2.5 V)
– Current: 37.7 mA
Power-Down Capability: 0.65 mA
APPLICATIONS
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5 V Data Acquisition Systems High
Linearity ADC Amplifier
Wireless Communication
Medical Imaging
Test and Measurement
DESCRIPTION
The THS4509 is a wideband, fully differential op amp
designed for 5 V data acquisition systems. It has very
low noise at 1.9 nV/√Hz, and extremely low harmonic
distortion of –75 dBc HD2 and –80 dBc HD3 at 100
MHz with 2 Vpp, G = 10 dB, and 1 kΩ load. Slew rate
is very high at 6600 Vµs and with settling time of 2 ns
to 1% (2 V step) it is ideal for pulsed applications. It is
designed for minimum gain of 6 dB, but is optimized
for gain of 10 dB.
To allow for dc coupling to ADCs, its unique output
common-mode control circuit maintains the output
common-mode voltage within 3 mV offset (typ) from
the set voltage, when set within 0.5 V of mid-supply,
with less than 4 mV differential offset voltage. The
common-mode set point is set to mid-supply by
internal circuitry, which may be over-driven from an
external source.
The input and output are optimized for best performance with their common-mode voltages set to
mid-supply. Along with high performance at low
power supply voltage, this makes for extremely high
performance single supply 5 V data acquisition systems. The combined performance of the THS4509 in
a gain of 10 dB driving the ADS5500 ADC, sampling
at 125 MSPS, is 81 dBc SFDR and 69.1 dBc SNR
with a –1 dBFS signal at 70 MHz.
The THS4509 is offered in a Quad 16-pin leadless
QFN package (RGT), and is characterized for operation over the full industrial temperature range from
–40°C to 85°C.
From
50 Ω
Source
VIN
100 Ω
348 Ω
2.5 V
69.8 Ω
100 Ω
0.22 µF
487 Ω
THS 4509
69.8 Ω
487 Ω
CM
1:1
56.3 Ω
VOUT
To 50 Ω
Test
Equipment
Open
−2.5 V
49.9 Ω
348 Ω
-75
G = 10 dB,
VO = 2 V PP,
RL = 1 kW
-80
Harmonic Distortion - dBc
FEATURES
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•
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-85
-90
-95
HD3
-100
-105
HD2
-1 10
1
10
100
f - Frequency - MHz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
THS4509
www.ti.com
SLOS454 – JANUARY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION
PACKAGED DEVICES
TEMPERATURE
QUAD QFN (1) (2)
(RGT-16)
THS4509RGTT
–40°C to 85°C
(1)
(2)
SYMBOL
–
THS4509RGTR
This package is available taped and reeled. The R suffix standard quantity is 3000. The T suffix standard quantity is 250.
The exposed thermal pad is electrically isolated from all other pins.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
UNIT
VS– to VS+
Supply voltage
6V
VI
Input voltage
±VS
VID
Differential input voltage
IO
Output current (1)
4V
200 mA
Continuous power dissipation
See Dissipation Rating Table
TJ
Maximum junction temperature
TA
Operating free-air temperature range
–40°C to 85°C
150°C
Tstg
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
ESD ratings
(1)
300°C
HBM
2000
CDM
1500
MM
100
The THS4509 incorporates a (QFN) exposed thermal pad on the underside of the chip. This acts as a heatsink and must be connected
to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the
QFN thermally enhanced package.
DISSIPATION RATINGS TABLE PER PACKAGE
2
PACKAGE
θJC
θJA
RGT (16)
2.4°C/W
39.5°C/W
POWER RATING
TA≤ 25°C
TA = 85°C
2.3 W
225 mW
THS4509
www.ti.com
SLOS454 – JANUARY 2005
SPECIFICATIONS; VS+– VS– = 5 V:
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5 V, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, G = 10 dB, Single-Ended Input, Differential Output, Input and Output Referenced to Mid-supply
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
–40°C to
85°C
UNITS
MIN/
MAX
GHz
Typ
TEST
LEVEL (1)
AC PERFORMANCE
G = 6 dB, VO = 100 mVpp
Small-Signal Bandwidth
2.0
G = 10 dB, VO = 100 mVpp
1.9
GHz
Typ
G = 14 dB, VO = 100 mVpp
600
MHz
Typ
G = 20 dB, VO = 100 mVpp
275
MHz
Typ
3
GHz
Typ
Gain-Bandwidth Product
G = 20 dB
Bandwidth for 0.1dB flatness
G = 10 dB, VO = 2 Vpp
300
MHz
Typ
Large-Signal Bandwidth
G = 10 dB, VO = 2 Vpp
1.5
GHz
Typ
Slew Rate (Differential)
2V Step
6600
V/µs
Typ
Rise Time
2V Step
0.5
ns
Typ
Fall Time
2V Step
0.5
ns
Typ
Settling Time to 1%
VO = 2 V Step
2
ns
Typ
Settling Time to 0.1%
VO = 2 V Step
10
ns
Typ
f = 10 MHz
–104
dBc
Typ
f = 50 MHz
–80
dBc
Typ
f = 100 MHz
–68
dBc
Typ
f = 10 MHz
–108
dBc
Typ
f = 50 MHz
–92
dBc
Typ
2nd Order Harmonic Distortion
(Single-ended input)
3rd Order Harmonic Distortion
(Single-ended input)
f = 100 MHz
2nd
Order Intermodulation Distortion
(Single-ended input)
3rd Order Intermodulation Distortion
(Single-ended input)
VO = 2 Vpp envelope,
200 kHz Tone Spacing,
RL = 499 Ω
2nd Order Output Intercept Point
(Single-ended input)
200 kHz Tone Spacing
3rd Order Output Intercept Point
(Single-ended input)
–81
dBc
Typ
fC = 70 MHz
–78
dBc
Typ
fC = 140 MHz
–64
dBc
Typ
fC = 70 MHz
–95
dBc
Typ
fC = 140 MHz
–78
dBc
Typ
fC = 70 MHz
78
dBm
Typ
fC = 140 MHz
58
dBm
Typ
fC = 70 MHz
43
dBm
Typ
fC = 140 MHz
38
dBm
Typ
dBm
Typ
fC = 70 MHz
12.2
fC = 140 MHz
10.8
Noise Figure
50 Ω System, 10 MHz
17.1
dB
Typ
Input Voltage Noise
f > 10 MHz
1.9
nV/√Hz
Typ
Input Current Noise
f > 10 MHz
2.2
pA/√Hz
Typ
1-dB Compression Point (2)
C
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
68
Input Offset Voltage
0.5
0.8
Average Offset Voltage Drift
Input Bias Current
6
8
Average Bias Current Drift
Input Offset Current
1.6
Average Offset Current Drift
3.6
dB
Typ
1
mV
Max
C
2.6
µV/°C
Typ
13
µA
Max
A
20
nA/°C
Typ
B
4.5
µA
Max
A
4
nA/°C
Typ
B
B
INPUT
Common-Mode Input Range High
1.75
V
Max
Common-Mode Input Range Low
–1.75
V
Min
90
dB
Min
Common-Mode Rejection Ratio
(1)
(2)
A
B
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
The 1-dB compression point is measured at the load with 50-Ω double termination. Add 3 dB to refer to amplifier output.
3
THS4509
www.ti.com
SLOS454 – JANUARY 2005
SPECIFICATIONS; VS+– VS– = 5 V: (continued)
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5 V, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, G = 10 dB, Single-Ended Input, Differential Output, Input and Output Referenced to Mid-supply
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
–40°C to
85°C
UNITS
MIN/
MAX
TEST
LEVEL (1)
OUTPUT
Maximum Output Voltage High
Minimum Output Voltage Low
Each output with 100 Ω to mid-supply
Differential Output Voltage Swing
1.4
1.35
1.13
V
Min
–1.4
–1.35
–1.13
V
Max
5.6
5.4
4.5
V
Min
Differential Output Current Drive
RL = 10 Ω
96
mA
Typ
Output Balance Error
VO = 100 mV, f = 1 MHz
–49
dB
Typ
Closed-Loop Output Impedance
f = 1 MHz
0.3
Ω
Typ
Small-Signal Bandwidth
700
MHz
Typ
Slew Rate
110
V/µs
Typ
1
V/V
Typ
A
C
OUTPUT COMMON-MODE VOLTAGE CONTROL
Gain
Output Common-Mode Offset from CM input
–1 V < CM < 1 V
5
mV
Typ
CM Input Bias Current
–1 V < CM < 1 V
±40
µA
Typ
CM Input Voltage Range
–1.5 to
1.5
V
Typ
CM Input Impedance
23
CM Default Voltage
1
kΩ
0
pF
C
Typ
V
Typ
POWER SUPPLY
Specified Operating Voltage
5
5.5
5.5
V
Max
Maximum Quiescent Current
37.7
38.6
38.7
mA
Max
Minimum Quiescent Current
37.7
36.4
36
mA
Min
90
dB
Min
Power Supply Rejection (±PSRR)
C
A
C
POWERDOWN
Enable Voltage Threshold
Referenced to Vs–,
Device Assured on above 2.1 V
1.6
V
Min
Disable Voltage Threshold
Referenced to Vs–,
Device Assured off below 0.7 V
1.6
V
Max
mA
Max
µA
Typ
Powerdown Quiescent Current
Input Bias Current
C
0.65
PD = VS–
Input Impedance
100
50
2
0.76
0.89
kΩ
pF
Typ
Turn-on Time Delay
Measured to output on
55
ns
Typ
Turn-off Time Delay
Measured to output off
10
µs
Typ
4
A
C
THS4509
www.ti.com
SLOS454 – JANUARY 2005
SPECIFICATIONS; VS+– VS– = 3 V:
Test conditions unless otherwise noted: VS+ = +1.5 V, VS– = –1.5 V, CM = open, VO = 1 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, G = 10 dB, Single-Ended Input, Differential Output, Input and Output Referenced to Mid-supply
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
–40°C to
85°C
UNITS
MIN/
MAX
GHz
Typ
TEST
LEVEL (1)
AC PERFORMANCE
G = 6 dB, VO = 100 mVpp
Small-Signal Bandwidth
1.9
G = 10 dB, VO = 100 mVpp
1.6
GHz
Typ
G = 14 dB, VO = 100 mVpp
625
MHz
Typ
G = 20 dB, VO = 100 mVpp
260
MHz
Typ
3
GHz
Typ
Gain-Bandwidth Product
G = 20 dB
Bandwidth for 0.1dB flatness
G = 10 dB, VO = 1 Vpp
400
MHz
Typ
Large-Signal Bandwidth
G = 10 dB, VO = 1 Vpp
1.5
GHz
Typ
Slew Rate (Differential)
1V Step
3500
V/µs
Typ
Rise Time
1V Step
0.25
ns
Typ
Fall Time
1V Step
0.25
ns
Typ
Settling Time to 1%
VO = 1 V Step
1
ns
Typ
f = 10 MHz
–107
dBc
Typ
f = 50 MHz
–83
dBc
Typ
f = 100 MHz
–60
dBc
Typ
f = 10 MHz
–87
dBc
Typ
f = 50 MHz
–65
dBc
Typ
2nd Order Harmonic Distortion
(Single-ended input)
3rd Order Harmonic Distortion
(Single-ended input)
f = 100 MHz
2nd
Order Intermodulation Distortion
(Single-ended input)
3rd
Order Intermodulation Distortion
(Single-ended input)
VO = 1 Vpp envelope,
200 kHz Tone Spacing,
RL = 200 Ω
2nd Order Output Intercept Point
(Single-ended input)
200 kHz Tone Spacing
3rd Order Output Intercept Point
(Single-ended input)
–54
dBc
Typ
fC = 70 MHz
–77
dBc
Typ
fC = 140 MHz
–54
dBc
Typ
fC = 70 MHz
–77
dBc
Typ
fC = 140 MHz
–62
dBc
Typ
fC = 70 MHz
72
dBm
Typ
fC = 140 MHz
52
dBm
Typ
fC = 70 MHz
38.5
dBm
Typ
fC = 140 MHz
30
dBm
Typ
dBm
Typ
fc = 70 MHz
2.2
fc = 140 MHz
0.25
Noise Figure
50 Ω System, 10 MHz
17.1
dB
Typ
Input Voltage Noise
f > 10 MHz
1.9
nV/√Hz
Typ
Input Current Noise
f > 10 MHz
2.2
pA/√Hz
Typ
1-dB Compression Point (2)
C
DC PERFORMANCE
Open-Loop Voltage Gain (AOL)
68
Input Offset Voltage
0.5
0.8
Average Offset Voltage Drift
Input Bias Current
6
8
Average Bias Current Drift
Input Offset Current
1.6
Average Offset Current Drift
3.6
dB
Typ
1
mV
Max
C
2.6
µV/°C
Typ
13
µA
Max
A
20
nA/°C
Typ
B
4.5
µA
Max
A
4
nA/°C
Typ
B
B
INPUT
Common-Mode Input Range High
0.75
V
Max
Common-Mode Input Range Low
–0.75
V
Min
80
dB
Min
Common-Mode Rejection Ratio
(1)
(2)
A
B
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
The 1-dB compression point is measured at the load with 50-Ω double termination. Add 3 dB to refer to amplifier output.
5
THS4509
www.ti.com
SLOS454 – JANUARY 2005
SPECIFICATIONS; VS+– VS– = 3 V: (continued)
Test conditions unless otherwise noted: VS+ = +1.5 V, VS– = –1.5 V, CM = open, VO = 1 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, G = 10 dB, Single-Ended Input, Differential Output, Input and Output Referenced to Mid-supply
TYP
PARAMETER
TEST CONDITIONS
25°C
OVER TEMPERATURE
25°C
–40°C to
85°C
UNITS
MIN/
MAX
TEST
LEVEL (1)
OUTPUT
Maximum Output Voltage High
Minimum Output Voltage Low
Each output with 100Ω to mid-supply
Differential Output Voltage Swing
0.45
0.43
0.2
V
Min
–0.45
–0.43
–0.2
V
Max
1.8
1.65
0.8
V
Min
18
18
Differential Output Current Drive
RL = 20 Ω
20
mA
Min
Output Balance Error
VO = 100 mV, f = 1 MHz
–49
dB
Typ
Closed-Loop Output Impedance
f = 1 MHz
0.3
Ω
Typ
Small-Signal Bandwidth
570
MHz
Typ
Slew Rate
60
V/µs
Typ
Gain
1
V/V
Typ
A
C
OUTPUT COMMON-MODE VOLTAGE CONTROL
Output Common-Mode Offset from CM input
–0.5 V < CM < 0.5 V
4
mV
Typ
CM Input Bias Current
–0.5 V < CM < 0.5 V
±40
µA
Typ
CM Input Voltage Range
–1.5 to
1.5
V
Typ
CM Input Impedance
20
kΩ pF
Typ
V
Typ
CM Default Voltage
1
0
C
POWER SUPPLY
Specified Operating Voltage
3
5.5
5.5
V
Max
Maximum Quiescent Current
34.8
35.8
36
mA
Max
Minimum Quiescent Current
34.8
33.8
33
mA
Min
dB
Min
Power Supply Rejection (±PSRR)
78
A
C
POWERDOWN
Enable Voltage Threshold
Referenced to Vs–
Device Assured on above 2.1 V
V
Min
Disable Voltage Threshold
Referenced to Vs–
Device Assured off below 0.7 V
V
Max
mA
Max
µA
Typ
Powerdown Quiescent Current
Input Bias Current
C
0.46
PD = VS–
Input Impedance
65
2
0.67
kΩ pF
Typ
Turn-on Time Delay
Measured to output on
100
ns
Typ
Turn-off Time Delay
Measured to output off
10
µs
Typ
6
50
0.53
A
C
THS4509
www.ti.com
SLOS454 – JANUARY 2005
DEVICE INFORMATION
TOP VIEW
RGT Package
THS4509
VS−
16
15
14
13
NC
1
12
PD
VIN−
2
11
VIN+
VOUT+
3
10
VOUT−
CM
4
9
5
6
7
CM
8
VS+
TERMINAL FUNCTIONS
TERMINAL
(RGT PACKAGE)
NO.
DESCRIPTION
NAME
1
NC
No internal connection
2
VIN–
Inverting amplifier input
3
VOUT+
Non-inverted amplifier output
4,9
CM
Common-mode voltage input
5,6,7,8
VS+
Positive amplifier power supply input
10
VOUT–
Inverted amplifier output
11
VIN+
Non-inverting amplifier input
12
PD
Powerdown, PD = logic low puts part into low power mode, PD = logic high or open for normal operation
13,14,15,16
VS–
Negative amplifier power supply input
7
THS4509
www.ti.com
SLOS454 – JANUARY 2005
TYPICAL CHARACTERISTICS
TYPICAL AC PERFORMANCE: VS+– VS– = 5 V
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, G = 10 dB, Single-Ended Input, Input and Output Referenced to Midrail
Small-Signal Frequnecy Response
Figure 1
Large Signal Frequnecy Response
Figure 2
0.1 dB Flatness
Figure 3
HD2, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 4
HD3, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 5
HD2, G = 10 dB, VOD = 2 VPP
vs Frequency
Figure 6
HD3, G = 10 dB, VOD = 2 VPP
vs Frequency
Figure 7
HD2, G = 14 dB, VOD = 2 VPP
vs Frequency
Figure 8
HD3, G = 14 dB, VOD = 2 VPP
vs Frequency
Figure 9
HD2, G = 10 dB
vs Output voltage
Figure 10
HD3, G = 10 dB
vs Output voltage
Figure 11
IMD2, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 12
IMD3, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 13
IMD2, G = 10 dB, VOD = 2 VPP
vs Frequency
Figure 14
IMD3, G = 10 dB, VOD = 2 VPP
vs Frequency
Figure 15
IMD2, G = 14 dB, VOD = 2 VPP
vs Frequency
Figure 16
IMD3, G = 14 dB, VOD = 2 VPP
vs Frequency
Figure 17
OIP2
vs Frequency
Figure 18
OIP3
vs Frequency
Figure 19
S-Parameters
vs Frequency
Figure 20
Slew Rate
vs Output Voltage
Figure 21
Harmonic
Distortion
Intermodulation
Distortion
Output Intercept Point
Transient Response
Figure 22
Settling Time
Figure 23
Rejection Ratio
vs Frequency
Figure 24
Output Impedance
vs Frequency
Figure 25
Overdrive Recovery
Output Voltage Swing
Figure 26
vs Load Resistance
Turn-Off Time
Figure 27
Figure 28
Turn-On Time
Figure 29
Input Offset Voltage
vs Input Common-Mode Voltage
Figure 30
Open Loop Gain
vs Frequency
Figure 31
Input Referred Noise
vs Frequency
Figure 32
Noise Figure
vs Frequency
Figure 33
Quiescent Current
vs Supply Voltage
Figure 34
Power Supply Current
vs Supply Voltage in Powerdown Mode
Figure 35
Output Balance Error
vs Frequency
Figure 36
CM Input Impedence
vs Frequency
Figure 37
CM Small-Signal Frequency Response
Figure 38
CM Input Bias Current
vs CM Input Voltage
Figure 39
Differential Output Offset Voltage
vs CM Input Voltage
Figure 40
Output Common-Mode Offset
vs CM Input Voltage
Figure 41
8
THS4509
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SLOS454 – JANUARY 2005
SMALL-SIGNAL
FREQUNECY RESPONSE
LARGE-SIGNAL
FREQUNECY RESPONSE
22
VOD = 100 mVPP
20
12
G = 10 dB
8
G = 6 dB
6
VOD = 2 VPP
10.1
16
G = 14 dB
14
12
G = 10 dB
10
8
G = 6 dB
6
4
4
2
2
0
1
10
100
f - Frequency - MHz
1000
10000
9.8
0.1
1
10
100
1000
10000
0.1
Figure 3.
HD2
vs
FREQUENCY
HD3
vs
FREQUENCY
HD2
vs
FREQUENCY
−80
RL = 200 Ω
−100
RL = 1 kΩ
−110
RL = 500 Ω
−120
−70
−80
RL = 100 Ω
−90
RL = 1 kΩ
−100
RL = 500 Ω
−110
RL = 200 Ω
1000
1
−70
−80
RL = 200 Ω
RL = 100 Ω
−90
−100
RL = 1 kΩ
−110
RL = 500 Ω
10
100
1000
1
f − Frequency − MHz
10
100
f − Frequency − MHz
Figure 4.
Figure 5.
Figure 6.
HD3
vs
FREQUENCY
HD2
vs
FREQUENCY
HD3
vs
FREQUENCY
−60
−60
−60
−70
−80
RL = 500 Ω
RL = 1 kΩ
−100
RL = 100 Ω
−110
RL = 200 Ω
−120
G = 14 dB,
VOD = 2 VPP
−70
3rd Order Harmonic Distortion − dBc
2nd Order Harmonic Distortion − dBc
G = 10 dB,
VOD = 2 VPP
RL = 100 Ω
−80
RL = 200 Ω
RL = 500 Ω
−90
−100
−110
RL = 1 kΩ
10
100
f − Frequency − MHz
Figure 7.
1000
1000
G = 14 dB,
VOD = 2 VPP
−70
−80
RL = 100 Ω
−90
RL = 1 kΩ
RL = 200 Ω
−100
RL = 500 Ω
−110
−120
−120
1
G = 10 dB,
VOD = 2 VPP
−120
−120
10
100
f − Frequency − MHz
1000
−60
G = 6 dB,
VOD = 2 VPP
2nd Order Harmonic Distortion − dBc
3rd Order Harmonic Distortion − dBc
RL = 100 Ω
−90
100
Figure 2.
−60
1
10
Figure 1.
G = 6 dB,
VOD = 2 VPP
−90
1
f − Frequency − MHz
f − Frequency − MHz
−60
−70
10
9.9
0
0.1
2nd Order Harmonic Distortion − dBc
VOD = 2 VPP
Signal Gain − dB
Large Signal Gain − dB
Small Signal Gain - dB
G = 14 dB
10
G = 20 dB
18
16
14
10.2
20
G = 20 dB
18
3rd Order Harmonic Distortion − dBc
0.1-dB FLATNESS
22
1
10
100
f − Frequency − MHz
Figure 8.
1000
1
10
100
1000
f − Frequency − MHz
Figure 9.
9
THS4509
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SLOS454 – JANUARY 2005
HD2
vs
OUTPUT VOLTAGE
HD3
vs
OUTPUT VOLTAGE
-60
-60
f = 64 MHz
-80
f = 32 MHz
-90
f = 16 MHz
-100
-110
f = 8 MHz
f = 32 MHz
-80
1
3
2
VOD - VPP
-100
-110
f = 16 MHz
4
1
2
3
−90
0
4
50
100
150
−95
RL = 500 Ω
−40
100
150
200
RL = 200 Ω
RL = 100 Ω
−50
−60
−70
RL = 500 Ω
−80
RL = 1 kΩ
−90
−100
−100
−60
Gain = 10 dB,
VOD = 2 VPP Envelope
0
50
100
150
200
RL = 100 Ω
Gain = 10 dB,
VOD = 2 VPP Envelope
−65
RL = 200 Ω
−70
−75
−80
−85
RL = 1 kΩ
−90
RL = 500 Ω
−95
−100
0
f − Frequency − MHz
f − Frequency − MHz
50
100
Figure 14.
Figure 15.
IMD2
vs
FREQUENCY
IMD3
vs
FREQUENCY
OIP2
vs
FREQUENCY
−60
IMD 3 − Intermodulation Distortion − dBc
Gain = 14 dB,
VOD = 2 VPP Envelope
RL = 200 Ω
RL = 100 Ω
−60
−70
RL = 500 Ω
−80
RL = 1 kΩ
−100
50
100
150
f − Frequency − MHz
Figure 16.
200
−65
−70
90
RL = 100 Ω
Gain = 14 dB,
VOD = 2 VPP Envelope
RL = 200 Ω
−75
−80
−85
−90
RL = 1 kΩ
−95
−100
0
RL = 500 Ω
50
100
150
150
200
f − Frequency − MHz
Figure 13.
−30
200
f − Frequency − MHz
IMD 3 − Intermodulation Distortion − dBc
IMD 2 − Intermodulation Distortion − dBc
RL = 100 Ω
−90
0
RL = 1 kΩ
IMD3
vs
FREQUENCY
−85
−90
RL = 500 Ω
−80
IMD2
vs
FREQUENCY
−80
−50
−70
IMD3
vs
FREQUENCY
RL = 1 kΩ
−40
−60
Figure 12.
RL = 200 Ω
50
−50
VOD - VPP
−70
0
RL = 200 Ω
RL = 100 Ω
−100
0
−30
−75
Gain = 6 dB,
VOD = 2 VPP Envelope
−40
Figure 11.
Gain = 6 dB,
VOD = 2 VPP Envelope
−65
−30
Figure 10.
−60
IMD 2 − Intermodulation Distortion − dBc
f = 8 MHz
-90
-120
0
IMD − Intermodulation Distortion − dBc
3
-70
OIP 3 − Output Intercept Point − dBm
2nd-Order Harmonic Distortion - dBc
-70
IMD2 − Intermodulation Distortion − dBc
3nd Order Harmonic Distortion - dBc
f = 64 MHz
-120
10
IMD2
vs
FREQUENCY
200
Gain = 6 dB
85
Gain = 14 dB
80
75
70
Gain = 10 dB
65
60
55
50
45
40
0
50
100
150
f − Frequency − MHz
f − Frequency − MHz
Figure 17.
Figure 18.
200
THS4509
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SLOS454 – JANUARY 2005
OIP3
vs
FREQUENCY
S-PARAMETERS
vs
FREQUENCY
8000
0
S21
Gain = 6 dB
48
7000
-10
42
40
Gain = 14 dB
38
36
Gain = 10 dB
SR − Slew Rate − V/µ s
44
-20
S11
-30
-40
S22
-50
-60
32
Fall
5000
4000
3000
2000
1000
S12
-70
0
50
100
150
0
200
10
1
f − Frequency − MHz
TRANSIENT RESPONSE
1.5
−0.5
1
1.5
2
2.5
0
−1
−2
3
40
30
−3
20
−4
10
0
0.5 1
1.5 2
2.5 3
3.5 4
CMRR
50
0
0.01
4.5 5
0.1
1
10
100
1000
f − Frequency − MHz
Figure 22.
Figure 23.
Figure 24.
OVERDRIVE RECOVERY
OUTPUT VOLTAGE SWING
vs
LOAD RESISTANCE
V OD − Differential Output Voltage − V
5
10
1
0.8
3
0.6
2
0.4
Output
0.2
0
0
−1
−0.2
−2
−0.4
−3
−0.6
−4
−0.8
−5
0.1
10
100
f − Frequency− MHz
Figure 25.
1000
7
1
Input
4
1
−1
0
4
PSRR+
60
t − Time − ns
100
1
70
t − Time − ns
OUTPUT IMPEDANCE
vs
FREQUENCY
0.1
3.5
PSRR−
80
0.2
0.4
0.6
0.8
t − Time − µs
Figure 26.
1
VOD - Differential Output Voltage - V
0.5
3
90
Input Voltage − V
0
2.5
100
VOD = 2 V step
1
−5
2
SETTLING TIME
2
−1
1.5
REJECTION RATIO
vs
FREQUENCY
Rejection Ratio −dB
VOD = 2 V step
0
1
Figure 21.
3
Percent of Final Value − %
0.5
0.5
VOD − Differential Output Voltage − VSTEP
5
1
0
Figure 20.
4
−1.5
−0.5
1000
100
f = Frequency - MHz
Figure 19.
V OD − Differential Output Voltage − V
6000
34
30
Z o − Output Impedance − Ω
Rise
46
S-Parameters - dB
OIP3 − Output Intercept Point − dBm
50
SLEW RATE
vs
OUTPUT VOLTAGE
6
5
4
3
2
1
0
0
500
1000
1500
2000
RL - Load Resistance - W
Figure 27.
11
THS4509
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SLOS454 – JANUARY 2005
4
Output
3
1.2
PD
0.8
2
0.4
1
0
0
−2
0
2
4
6
8
10
t − Time − µs
12
1.6
4
PD
1.2
3
Output
0.8
2
0.4
1
0
50
100
150
200
0
250
25
20
15
10
5
−5
−2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2
Input Common-Mode Voltage − V
t − Time − ns
Figure 28.
Figure 29.
Figure 30.
OPEN LOOP GAIN AND PHASE
vs
FREQUENCY
INPUT REFERRED NOISE
vs
FREQUENCY
NOISE FIGURE
vs
FREQUENCY
1000
50
−100
30
−150
20
10
−200
Hz
Hz
−50
40
19
100
In
10
Vn
0
Gain = 6 dB
17
Gain = 10 dB
16
15
Gain = 14 dB
14
13
12
Gain = 20 dB
11
−10
1
100
10 k
1M
100 M
−250
10 G
1
10
f − Frequency − Hz
100
1k
10 k
100 k
1M
10
10 M
0
100
150
Figure 32.
Figure 33.
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
POWER SUPPLY CURRENT
vs
SUPPLY VOLTAGE IN
POWERDOWN MODE
OUTPUT BALANCE ERROR
vs
FREQUENCY
800
10
TA = 85°C
700
±1.35 V
TA = 85°C
30
0
TA = 25°C
600
Output Balance Error − dB
Power Supply Current − µ A
TA = −40°C
500
400
TA = −40°C
300
200
0
1.5
2
VS − Supply Voltage − V
Figure 34.
2.5
−10
−20
−30
−40
−50
100
25
200
f − Frequency − MHz
Figure 31.
TA = 25°C
1
50
f − Frequency − Hz
40
35
50−Ω System
18
NF − Noise Figure − dB
Gain
50
2.5
20
I n − Current Noise − pA/
60
V n − Voltage Noise − nV/
Phase
Open Loop Phase − degrees
0
70
12
30
0
0
−50
80
I Q− Quiescent Current − mA
40
35
14
90
Open Loop Gain − dB
5
V IO − Input Offset Voltage − mV
1.6
2
Power Down Input − V
5
V OD− Differential Output Voltage − V
TURN-ON TIME
2
Power Down Input − V
V OD− Differential Ouput Voltage − V
TURN-OFF TIME
INPUT OFFSET VOLTAGE
vs
INPUT COMMON-MODE VOLTAGE
−60
0
0.5
1
1.5
2
VS − Supply Voltage − V
Figure 35.
2.5
0.1
1
10
100
f − Frequency − MHz
Figure 36.
1000
THS4509
www.ti.com
SLOS454 – JANUARY 2005
CM INPUT IMPEDANCE
vs
FREQUENCY
1
0.1
0.01
1
10
100
f − Frequency − MHz
1000
9
8
7
6
5
4
3
2
1
0
−1
−2
−3
−4
−5
−6
0.1
300
CM Input Bias Current − µ A
CM Gain − dB
10
100 mVPP
200
100
0
−100
−200
1
10
100
1000
−300
−2.5 −2 −1.5 −1 −0.5 0
f − Frequency − MHz
Figure 37.
0.5 1
1.5 2
2.5
CM Input Voltage − V
Figure 38.
DIFFERENTIAL OUTPUT
OFFSET VOLTAGE
vs
CM INPUT VOLTAGE
Figure 39.
OUTPUT COMMON-MODE OFFSET
vs
CM INPUT VOLTAGE
5
50
Output Common−Mode Offset − mV
Differential Output Offset Voltage − mV
CM Input Impedance − kΩ
100
0.1
CM INPUT BIAS CURRENT
vs
CM INPUT VOLTAGE
CM SMALL SIGNAL
FREQUENCY RESPONSE
4
3
2
1
0
−1
−2.5 −2 −1.5 −1 −0.5 0
0.5
1
CM Input Voltage − V
Figure 40.
1.5
2
2.5
40
30
20
10
0
−10
−20
−30
−40
−50
−2.5 −2 −1.5 −1 −0.5 0
0.5 1
1.5 2
2.5
CM Input Voltage − V
Figure 41.
13
THS4509
www.ti.com
SLOS454 – JANUARY 2005
TYPICAL AC PERFORMANCE: VS+– VS– = 3 V
Test conditions unless otherwise noted: VS+ = +1.5 V, VS– = –1.5V, CM = open, VOD = 1 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, G = 10 dB, Single-Ended Input, Input and Output Referenced to Midrail
Small-Signal Frequnecy Response
Figure 42
Large Signal Frequnecy Response
Figure 43
0.1 dB Flatness
Figure 44
Harmonic
Distortion
Intermodulation
Distortion
Ouput Intercept Point
HD2, G = 6 dB, VOD = 1 VPP
vs Frequency
Figure 45
HD3, G = 6 dB, VOD = 1 VPP
vs Frequency
Figure 46
HD2, G = 10 dB, VOD = 1 VPP
vs Frequency
Figure 47
HD3, G = 10 dB, VOD = 1 VPP
vs Frequency
Figure 48
HD2, G = 14 dB, VOD = 1 VPP
vs Frequency
Figure 49
HD3, G = 14 dB, VOD = 1 VPP
vs Frequency
Figure 50
IMD2, G = 6 dB, VOD = 1 VPP
vs Frequency
Figure 51
IMD3, G = 6 dB, VOD = 1 VPP
vs Frequency
Figure 52
IMD2, G = 10 dB, VOD = 1 VPP
vs Frequency
Figure 53
IMD3, G = 10 dB, VOD = 1 VPP
vs Frequency
Figure 54
IMD2, G = 14 dB, VOD = 1 VPP
vs Frequency
Figure 55
IMD3, G = 14 dB, VOD = 1 VPP
vs Frequency
Figure 56
OIP2
vs Frequency
Figure 57
OIP3
vs Frequency
Figure 58
S-Parameters
vs Frequency
Figure 59
Slew Rate
vs Output Voltage
Figure 60
Transient Response
Figure 61
Settling Time
Figure 62
Output Voltage Swing
vs Load Resistance
Figure 63
Rejection Ratio
vs Frequency
Figure 64
Overdrive Recovery
Output Impedance
Figure 65
vs Frequency
Turn-Off Time
Figure 66
Figure 67
Turn-On Time
Figure 68
Ouput Balance Error
vs Frequency
Figure 69
Noise Figure
vs Frequency
Figure 70
CM Small-Signal Frequency Response
Figure 71
CM Input Impedance
vs Frequency
Figure 72
Differential Output Offset Voltage
vs CM Input Voltage
Figure 73
Output Common-Mode Offset
vs CM Input Voltage
Figure 74
14
THS4509
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SLOS454 – JANUARY 2005
SMALL-SIGNAL
FREQUNECY RESPONSE
LARGE-SIGNAL
FREQUNECY RESPONSE
22
22
VOD = 100 mVPP
20
G = 14 dB
14
12
G = 10 dB
10
8
G = 6 dB
6
10.1
16
G = 14 dB
14
12
G = 10 dB
10
8
G = 6 dB
6
4
4
2
2
9.8
0
0.1
1
10
100
1000
10000
0.1
f − Frequency − MHz
1000
10000
0.1
HD3
vs
FREQUENCY
HD2
vs
FREQUENCY
−80
RL = 100 Ω
−90
RL = 200 Ω
RL = 1 kΩ
−110
RL = 500 Ω
10
100
G = 6 dB,
VOD = 1 VPP
−50
−60
−70
RL = 100 Ω
−80
RL = 200 Ω
−90
RL = 1 kΩ
RL = 500 Ω
−100
1000
2nd Order Harmonic Distortion − dBc
−70
1
10
RL = 200 Ω
−90
−100
RL = 1 kΩ
−110
RL = 500 Ω
10
1
1000
100
HD3
vs
FREQUENCY
HD2
vs
FREQUENCY
HD3
vs
FREQUENCY
2nd Order Harmonic Distortion − dBc
RL = 1 kΩ
RL = 500 Ω
RL = 200 Ω
−100
−40
G = 14 dB,
VOD = 1 VPP
−50
−60
RL = 100 Ω
−70
−80
RL = 200 Ω
−90
−100
RL = 500 Ω
−110
RL = 1 kΩ
−120
10
100
f − Frequency − MHz
Figure 48.
1000
1000
f − Frequency − MHz
Figure 47.
−70
1
−80
Figure 46.
−60
−90
−70
−120
100
−40
−80
−60
Figure 45.
G = 10 dB,
VOD = 1 VPP
−50
G = 10 dB,
VOD = 1 VPP
−50
f − Frequency − MHz
−40
10000
−40
−40
1
10
100
1000
f − Frequency − MHz
HD2
vs
FREQUENCY
G = 6 dB,
VOD = 1 VPP
−100
1
Figure 44.
3rd Order Harmonic Distortion − dBc
2nd Order Harmonic Distortion − dBc
100
Figure 43.
f − Frequency − MHz
3rd Order Harmonic Distortion − dBc
10
Figure 42.
−60
−120
1
f− Frequency − MHz
−40
−50
10
9.9
3rd Order Harmonic Distortion − dBc
0
VOD = 1 VPP
Signal Gain − dB
16
VOD = 1 VPP
18
Large Signal Gain − dB
Small Signal Gain − dB
18
G = 20 dB
20
G = 20 dB
0.1 dB FLATNESS
10.2
1
10
100
f − Frequency − MHz
Figure 49.
1000
G = 14 dB,
VOD = 1 VPP
−50
−60
RL = 100 Ω
−70
RL = 200 Ω
−80
RL = 500 Ω
−90
RL = 1 kΩ
−100
1
10
100
f − Frequency − MHz
1000
Figure 50.
15
THS4509
www.ti.com
SLOS454 – JANUARY 2005
−30
RL = 500 Ω
Gain = 6 dB,
VOD = 1 VPP Envelope
RL = 1 kΩ
−50
−60
−70
RL = 100 Ω
RL = 200 Ω
−80
−90
−100
0
50
100
150
−30
Gain = 6 dB,
VOD = 1 VPP Envelope
−40
RL = 100 Ω
−50
−60
RL = 1 kΩ
−70
RL = 500 Ω
−80
−90
RL = 200 Ω
−100
200
0
f − Frequency − MHz
−30
Gain = 10 dB,
VOD = 1 VPP Envelope
RL = 100 Ω
RL = 500 Ω
RL = 1 kΩ
RL = 200 Ω
50
100
150
150
−40
−50
−60
RL = 1 kΩ
RL = 100 Ω
−70
RL = 200 Ω
−80
−90
50
100
150
f − Frequency − MHz
Gain = 14 dB,
VOD = 1 VPP Envelope
−40
RL = 100 Ω
−50
−60
RL = 500 Ω
−70
RL = 1 kΩ
RL = 200 Ω
−80
−90
−100
200
0
50
100
150
f − Frequency − MHz
Figure 54.
Figure 55.
Figure 56.
OIP2, dBm
vs
FREQUENCY
OIP3, dBm
vs
FREQUENCY
S-PARAMETERS
vs
FREQUENCY
75
70
Gain = 10 dB
Gain = 14 dB
55
50
45
40
Gain = 6 dB
S21
48
-10
46
Gain = 10 dB
-20
44
S-Parameters - dB
80
42
40
38
36
34
Gain = 14 dB
S22
-50
-60
S12
f − Frequency − MHz
Figure 57.
Figure 58.
150
-40
-70
50
100
f − Frequency − MHz
100
S11
-30
32
30
50
200
0
50
Gain = 6 dB
200
−30
RL = 500 Ω
Gain = 14 dB,
VOD = 1 VPP Envelope
0
OIP3 − Output Intercept Point − dBm
OIP2 − Output Intercept Point − dBm
100
f − Frequency − MHz
−100
200
90
16
50
IMD3
vs
FREQUENCY
f − Frequency − MHz
0
0
IMD2
vs
FREQUENCY
−90
60
−90
IMD3
vs
FREQUENCY
−80
65
RL = 200 Ω
−80
−100
200
RL = 1 kΩ
RL = 100 Ω
−70
Figure 53.
−60
85
150
−60
Figure 52.
−50
−100
0
100
−50
Figure 51.
−40
−70
50
RL = 500 Ω
Gain = 10 dB,
VOD = 1 VPP Envelope
−40
f − Frequency − MHz
IMD 2 − Intermodulation Distortion − dBc
IMD 3 − Intermodulation Distortion − dBc
−30
IMD 2 − Intermodulation Distortion − dBc
−40
IMD2
vs
FREQUENCY
IMD 3 − Intermodulation Distortion − dBc
−30
IMD3
vs
FREQUENCY
IMD 3 − Intermodulation Distortion − dBc
IMD 2 − Intermodulation Distortion − dBc
IMD2
vs
FREQUENCY
0
150
1
10
100
f = Frequency - MHz
Figure 59.
1000
THS4509
www.ti.com
SLOS454 – JANUARY 2005
SLEW RATE
vs
OUTPUT VOLTAGE
TRANSIENT RESPONSE
2500
Falling
2000
1500
1000
500
0
0
0.2
0.4
0.6
0.8
1
1.2
4
0.4
0.2
0.1
0
−0.1
−0.2
−0.3
−2
−3
−0.5
0
0.5
1
1.5
2
2.5
−5
3
0
0.5 1
1.5 2
2.5 3
3.5 4
t − Time − ns
t − Time − ns
Figure 60.
Figure 61.
Figure 62.
OUTPUT VOLTAGE SWING
vs
LOAD RESISTANCE
REJECTION RATIO
vs
FREQUENCY
CMRR
70
1.5
1
60
PSRR+
50
40
30
0
1500
0
0.01
2000
1
10
100
f − Frequency − MHz
Figure 63.
Figure 64.
OUTPUT IMPEDANCE
vs
FREQUENCY
V OD − Differential Ouput Voltage − V
1
Figure 66.
−1
−0.2
−2
−0.4
−0.6
0
0.2
1000
2.5
Output
2
0.6
1.5
PD
1
0.2
0.5
0
0
2
4
6
8
t − Time − µs
10
Figure 67.
1
TURN-ON TIME
0.8
−2
0.8
1.2
3
0.4
0.4
0.6
t − Time − µs
Figure 65.
0
f − Frequency− MHz
0
TURN-OFF TIME
10
100
0
1000
1
100
10
Output
−3
0.1
R L - Load Resistance - W
1
0.2
1
0.5
−2.5
12
14
Power Down Input − V
1000
0.4
2
1.5
−1.5
10
500
0.6
Input
2.5
−0.5
20
0.5
5
OVERDRIVE RECOVERY
V OD − Differential Output Voltage − V
2
4.5
3
80
Rejection Ratio −dB
V OD - Differential Output Voltage - V
0
−1
−4
PSRR−
Z o − Output Impedance − Ω
1
−0.5
90
0.1
0.1
2
VOD − Differential Output Voltage −VSTEP
2.5
0
3
−0.4
−0.6
1.4
VOD = 1 V step
0.3
VOD = 1 V step
Input Voltage − V
Rising
0.5
3
2.5
1
PD
0.8
2
0.6
1.5
Output
0.4
1
0.2
0.5
0
0
50
100
150
200
Power Down Input − V
3000
5
V OD − Differential Ouput Voltage − V
SR − Slew Rate − V/µ s
3500
SETTLING TIME
0.6
Percent of Final Value − %
V OD − Differential Output Voltage − V
4000
0
250
t − Time − ns
Figure 68.
17
THS4509
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SLOS454 – JANUARY 2005
OUTPUT BALANCE ERROR
vs
FREQUENCY
NOISE FIGURE
vs
FREQUENCY
10
5
20
4
19
Gain = 6 dB
−20
−30
−40
17
Gain = 10 dB
16
15
Gain = 14 dB
14
13
10
100
50
100
150
200
0.1
1
10
100
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
1000
Figure 69.
Figure 70.
Figure 71.
CM INPUT IMPEDANCE
vs
FREQUENCY
DIFFERENTIAL OUTPUT OFFSET
VOLTAGE
vs
CM INPUT VOLTAGE
OUTPUT COMMON-MODE OFFSET
vs
CM INPUT VOLTAGE
100
50
10
1
0.1
0.01
1
10
100
f − Frequency − MHz
Figure 72.
1000
Output Common−Mode Offset − mV
Differential Output Offset Voltage − mV
5
0.1
−2
−6
0
1000
0
−1
−5
10
1
1
−4
Gain = 20 dB
11
0.1
2
−3
12
−60
100 mVPP
3
CM Gain − dB
−10
−50
CM Input Impedance − kΩ
50−Ω System
18
NF − Noise Figure − dB
Output Balance Error − dB
0
18
CM SMALL SIGNAL
FREQUENCY RESPONSE
4
3
2
1
0
−1
−1.5
−1
−0.5
0
0.5
CM Input Voltage − V
Figure 73.
1
1.5
40
30
20
10
0
−10
−20
−30
−40
−50
−1.5
−1
−0.5
0
0.5
CM Input Voltage − V
Figure 74.
1
1.5
THS4509
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SLOS454 – JANUARY 2005
TEST CIRCUITS
The THS4509 is tested with the following test circuits
built on the EVM. For simplicity, power supply decoupling is not shown – see layout in the applications
section for recommendations. Depending on the test
conditions, component values are changed per the
following tables, or as otherwise noted. The signal
generators used are ac coupled 50-Ω sources and a
0.22-µF capacitor and a 49.9-Ω resistor to ground are
inserted across RIT on the alternate input to balance
the circuit. A split power supply is used to ease the
interface to common test equipment, but the amplifier
can be operated single-supply as described in the
applications section with no impact on performance.
The output is probed using a high-impedance differential probe across the 100-Ω resistor. The gain is
referred to the amplifier output by adding back the
6-dB loss due to the voltage divider on the output.
From
50 Ω
Source
VIN
RG
R IT
RF
VS+
49.9 Ω
RG
0.22 µF
THS4509
CM
R IT
Output Measured
Here With High
Impedance
Differential Probe
Open
0.22 µF
VS−
49.9 Ω
100 Ω
49.9 Ω
RF
Figure 75. Frequency Response Test Circuit
Table 1. Gain Component Values
GAIN
RF
RG
RIT
6 dB
348 Ω
165 Ω
61.9 Ω
10 dB
348 Ω
100 Ω
69.8 Ω
14 dB
348 Ω
56.2 Ω
88.7 Ω
20 dB
348 Ω
16.5 Ω
287 Ω
Note the gain setting includes 50-Ω source impedance. Components are chosen to achieve gain
and 50-Ω input termination.
Table 2. Load Component Values
RL
RO
ROT
Atten.
100 Ω
25 Ω
open
6 dB
200 Ω
86.6 Ω
69.8 Ω
16.8 dB
499 Ω
237 Ω
56.2 Ω
25.5 dB
1k Ω
487 Ω
52.3 Ω
31.8 dB
Note the total load includes 50-Ω termination by
the test equipment. Components are chosen to
achieve load and 50-Ω line termination through a
1:1 transformer.
Due to the voltage divider on the output formed by
the load component values, the amplifier's output is
attenuated. The column Atten in Table 2 shows the
attenuation expected from the resistor divider. When
using a transformer at the output as shown in
Figure 76, the signal will see slightly more loss, and
these numbers will be approximate.
Frequency Response
The circuit shown in Figure 75 is used to measure the
frequency response of the circuit.
A network analyzer is used as the signal source and
as the measurement device. The output impedance
of the network analyzer is 50 Ω. RIT and RG are
chosen to impedance match to 50 Ω, and to maintain
the proper gain. To balance the amplifier, a 0.22-µF
capacitor and 49.9-Ω resistor to ground are inserted
across RIT on the alternate input.
Distortion and 1dB Compression
The circuit shown in Figure 76 is used to measure
harmonic distortion, intermodulation distortion, and
1-db compression point of the amplifier.
A signal generator is used as the signal source and
the output is measured with a spectrum analyzer. The
output impedance of the signal generator is 50 Ω. RIT
and RG are chosen to impedance-match to 50 Ω, and
to maintain the proper gain. To balance the amplifier,
a 0.22-µF capacitor and 49.9-Ω resistor to ground are
inserted across RIT on the alternate input.
A low-pass filter is inserted in series with the input to
reduce harmonics generated at the signal source.
The level of the fundamental is measured, then a
high-pass filter is inserted at the output to reduce the
fundamental so that it does not generate distortion in
the input of the spectrum analyzer.
The transformer used in the output to convert the
signal from differential to single ended is an
ADT1-1WT. It limits the frequency response of the
circuit so that measurements cannot be made below
approximately 1MHz.
From
50 Ω
Source
VIN
RF
RG
RIT
VS+
RO
RG
0.22 µF
49.9 Ω
THS 4509
CM
RIT
VS−
RO
1:1
VOUT
ROT
To 50 Ω
Test
Equipment
Open
0.22 µF
RF
Figure 76. Distortion Test Circuit
The 1-dB compression point is measured with a
spectrum analyzer with 50-Ω double termination or
19
THS4509
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SLOS454 – JANUARY 2005
100-Ω termination as shown in Table 2. The input
power is increased until the output is 1 dB lower than
expected. The number reported in the table data is
the power delivered to the spectrum analyzer input.
Add 3 dB to refer to the amplifier output.
S-Parameter, Slew Rate, Transient Response, Settling Time, Output Impedance, Overdrive, Output
Voltage, and Turn-On/Off Time
The circuit shown in Figure 77 is used to measure
s-parameters, slew rate, transient response, settling
time, output impedance, overdrive recovery, output
voltage swing, and turn-on/turn-off times of the amplifier. For output impedance, the signal is injected at
VOUT with VIN left open and the drop across the 49.9
Ω resistor is used to calculate the impedance seen
looking into the amplifier’s output.
Because S21 is measured single-ended at the load
with 50-Ω double termination, add 12 dB to refer to
the amplifier’s output as a differential signal.
From V IN
50 Ω
Source
RG
R IT
RF
VS+
at VOUT+ or VOUT– with the input injected at VIN, RCM =
0 Ω and RCMT = 49.9 Ω. The input impedance is
measured with RCM = 49.9 Ω with RCMT = open, and
calculated by measuring the voltage drop across RCM
to determine the input current.
RF
RG
0.22 mF
RIT
VS+
49.9 W
49.9 W
VOUT–
RG
0.22 mF
THS4509
VOUT+
CM
RIT
VOUT+
0.22 µF
49.9 Ω
THS 4509
49.9 Ω
VOUT−
CM
R IT
VS−
To 50 Ω
Test
Equipment
Open
0.22 µF
RF
Figure 77. S-Parameter, SR, Transient Response,
Settling Time, ZO, Overdrive Recovery, VOUT
Swing, and Turn-on/off Test Circuit
CM Input
The circuit shown in Figure 78 is used to measure the
frequency response and input impedance of the CM
input. Frequency response is measured single-ended
20
RCM
VIN
VS–
49.9 W
RCMT
RF
From
50-ohm
source
Figure 78. CM Input Test Circuit
CMRR and PSRR
The circuit shown in Figure 79 is used to measure the
CMRR and PSRR of VS+ and VS–. The input is
switched appropriately to match the test being performed.
49.9 Ω
RG
49.9 W
To
50-ohm
Test
Equipment
348 Ω
VS+
PSRR+
From VIN
50 Ω
CMRR
Source
PSRR−
VS−
VS+
49.9 Ω
100 Ω
100 Ω
THS4509
CM
69.8 Ω
VS−
49.9 Ω
100 Ω
Open
0.22 µF
Output
Measured
Here
With High
Impedance
Differential
Probe
348 Ω
Figure 79. CMRR and PSRR Test Circuit
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APPLICATION INFORMATION
APPLICATIONS
Single-Ended
Input
The following circuits show application information for
the THS4509. For simplicity, power supply decoupling
capacitors are not shown in these diagrams. Please
see the Subsection 1 section for recommendations.
For more detail on the use and operation of fully
differential op amps refer to application report
Fully-Differential Amplifiers (SLOA054) .
Differential Input to Differential Output Amplifier
The THS4509 is a fully differential op amp, and can
be used to amplify differential input signals to differential output signals. A basic block diagram of the
circuit is shown in Figure 80 (CM input not shown).
The gain of the circuit is set by RF divided by RG.
RF
Differential
Input
RG
V IN+
Differential
Output
VS+
+
–
VOUT–
THS4509
VIN–
RG
– +
VOUT+
VS–
RF
Figure 80. Differential Input to Differential Ouput
Amplifier
Depending on the source and load, input and output
termination can be accomplished by adding RIT and
RO.
Single-Ended Input to Differential Output Amplifier
The THS4509 can be used to amplify and convert
single-ended input signals to differential output signals. A basic block diagram of the circuit is shown in
Figure 81 (CM input not shown). The gain of the
circuit is again set by RF divided by RG.
RG
RF
VS
Differential
Output
+
–
VOUT–
THS 4509
RG
–
+
VOUT+
VS
RF
Figure 81. Single-Ended Input to Differential
Output Amplifier
Input Common-Mode Voltage Range
The input common-model voltage of a fully differential
op amp is the voltage at the '+' and '–' input pins of
the op amp.
It is important to not violate the input common-mode
voltage range (VICR) of the op amp. Assuming the op
amp is in linear operation the voltage across the input
pins is only a few millivolts at most. So finding the
voltage at one input pin will determine the input
common-mode voltage of the op amp.
Treating the negative input as a summing node, the
voltage is given by Equation 1:
ö
æ
ö æ
RG
RF
÷
÷ + ç VIN- ´
VIC = çç VOUT + ´
÷
÷ ç
R
R
R
R
+
+
G
F ø
G
F ø è
è
(1)
To determine the VICR of the op amp, the voltage at
the negative input is evaluated at the extremes of
VOUT+.
As the gain of the op amp increases, the input
common-mode voltage becomes closer and closer to
the input common-mode voltage of the source.
Setting the Output Common-Mode Voltage
The output common-mode voltage is set by the
voltage at the CM pin(s). The internal common-mode
control circuit maintains the output common-mode
voltage within 3-mV offset (typ) from the set voltage,
when set within 0.5 V of mid-supply, with less than
4mV differential offset voltage. If left unconnected,
the common-mode set point is set to mid-supply by
internal circuitry, which may be over-driven from an
external source. Figure 82 is representative of the
CM input. The internal CM circuit has about 700 MHz
of –3-dB bandwidth, which is required for best per-
21
THS4509
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SLOS454 – JANUARY 2005
formance, but it is intended to be a DC bias input pin.
Bypass capacitors are recommended on this pin to
reduce noise at the output. The external current
required to overdrive the internal resistor divider is
given by Equation 2:
IEXT =
2VCM - (VS + - VS - )
50 kW
RS
RG
RF
VS+
RT
VSignal
RO
VCM
VBias= VCM
(2)
THS4509
RG
RS
VCM
VS+
to internal
CM circuit
CM
50 kW
V S–
To facilitate testing with common lab equipment, the
THS4509 EVM allows split-supply operation, and the
characterization data presented in this data sheet
was taken with split-supply power inputs. The device
can easily be used with a single-supply power input
without degrading the performance. Figure 83, Figure 84, and Figure 85 show DC and AC-coupled
single-supply circuits with single-ended inputs. These
configurations all allow the input and output common-mode voltage to be set to mid-supply allowing
for optimum performance. The information presented
here can also be applied to differential input sources.
In Figure 83, the source is referenced to the same
voltage as the CM pin (VCM). VCM is set by the
internal circuit to mid-supply. RT along with the input
impedance of the amplifier circuit provides input
termination, which is also referenced to VCM.
Note RS and RT are added to the alternate input from
the signal input to balance the amplifier. Alternately,
one resistor can be used equal to the combined value
RG+ RS||RT on this input. This is also true of the
circuits shown in Figure 84 and Figure 85.
22
RF
Figure 83. THS4509 DC Coupled Single-Supply
with Input Biased to VCM
In Figure 84 the source is referenced to ground and
so is the input termination resistor. RPU is added to
the circuit to avoid violating the VICR of the op amp.
The proper value of resistor to add can be calculated
from Equation 3:
R PU =
Figure 82. CM Input Circuit
Single-Supply Operation (3V to 5V)
VOUT+
VS–
VCM VCM
I EXT
VOUT-
CM
RT
where VCM is the voltage applied to the CM pin.
50 kW
RO
(VIC - VS+ )
æ 1
VCM çç
è RF
æ 1
ö
1 ö
÷÷
÷÷ - VIC çç
+
R
R
F ø
è IN
ø
(3)
VIC is the desire input common-mode voltage, VCM =
CM, and RIN = RG+ RS||RT. To set to mid-supply,
make the value of RPU = RG+ RS||RT.
Table 3 is a modification of Table 1 to add the proper
values with RPU assuming a 50 Ω source impedance
and setting the input and output common-mode
voltage to mid-supply.
There are two drawbacks to this configuration. One is
it requires additional current from the power supply.
Using the values shown for a gain of 10 dB requires
37 mA more current with 5 V supply, and 22 mA
more current with 3 V supply.
The other drawback is this configuration also increases the noise gain of the circuit. In the 10 dB
gain case, noise gain increases by a factor of 1.5.
Table 3. RPU Values for Various Gains
Gain
RF
RG
RIT
RPU
6 dB
348 Ω
169 Ω
64.9 Ω
200 Ω
10 dB
348 Ω
102 Ω
78.7 Ω
133 Ω
14 dB
348 Ω
61.9 Ω
115 Ω
97.6 Ω
20 dB
348 Ω
40.2 Ω
221 Ω
80.6 Ω
THS4509
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SLOS454 – JANUARY 2005
V S+
R PU
RS
RF
RG
RT
V Signal
V S+
V S+
RO
V OUT-
R PU
THS 4509
RG
RO
V OUT+
RS
V S-
RT
CM
RF
Figure 84. THS4509 DC Coupled Single-Supply
with RPU Used to Set VIC
Figure 85 shows AC coupling to the source. Using
capacitors in series with the termination resistors
allows the amplifier to self-bias both input and output
to mid-supply.
C
RS
V Signal
RG
RT
is inserted in series with the input to reduce harmonics and noise from the signal source. Input termination is accomplished via the 69.8-Ω resistor and
0.22-µF capacitor to ground in conjunction with the
input impedance of the amplifier circuit. A 0.22-µF
capacitor and 49.9-Ω resistor is inserted to ground
across the 69.8-Ω resistor and 0.22-µF capacitor on
the alternate input to balance the circuit. Gain is a
function of the source impedance, termination, and
348-Ω feedback resistor. Refer to Table 3 for
component values to set proper 50-Ω termination for
other common gains. A split power supply of +4V and
-1V is used to set the input and output common-mode
voltages to approximately mid-supply while setting
the input common-mode of the ADS5500 to the
recommended +1.55V. This maintains maximum
headroom on the internal transistors of the THS4509
to insure optimum performance.
VIN
From
50-W
source
100 W
100 W
V S+= 3V to 5V
RO
49.9 W
THS 4509
CM
0.22 mF
348 W
V OUT+
RS
RT
C
C
100 W2.7 pF
A IN +
ADS5500
A IN - CM
49.9 W
-1 V
0.22 mF
RO
THS 4509
69.8 W
V OUT-
14 -bit,
125 MSPS
100 W
0.22 mF
C
RG
4V
69.3 W
RF
348 W
0.1 mF
0.1 mF
CM
V S-
Figure 86. THS4509 + ADS5500 Circuit
RF
90
SFDR (dBc)
Figure 85. THS4509 AC Coupled Single-Supply
85
80
THS4509 + ADS5500 Combined Performance
The THS4509 is designed to be a high performance
drive amplifier for high performance data converters
like the ADS5500 14-bit 125-MSPS ADC. Figure 86
shows a circuit combining the two devices, and
Figure 87 shows the combined SNR and SFDR
performance versus frequency with –1 dBFS input
signal level sampling at 125 MSPS. The THS4509
amplifier circuit provides 10 dB of gain, converts the
single-ended input to differential, and sets the proper
input common-mode voltage to the ADS5500. The
100-Ω resistors and 2.7-pF capacitor between the
THS4509 outputs and ADS5500 inputs along with the
input capacitance of the ADS5500 limit the bandwidth
of the signal to 115 MHz (–3 dB). For testing, a signal
generator is used for the signal source. The generator is an AC-coupled 50-Ω source. A band-pass filter
SNR (dBFS)
75
70
65
10
20
30
40
50
60
70
80
Input Frequency - MHz
90
100
110
Figure 87. THS4509 + ADS5500 SFDR and SNR
Performance versus Frequency
Figure 88 shows the 2-tone FFT of the THS4509 +
ADS5500 circuit with 65 MHz and 70 MHz input
frequencies. The SFDR is 90 dBc.
23
THS4509
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SLOS454 – JANUARY 2005
From
50-W
source
V IN
348 W
100 W
5V
69 .8 W
THS4509
100
49 .9 W
0.22 mF
14-bit,
105 MSPS
A IN+
ADS 5424
A IN– VBG
225 W
0.22 mF
225 W
2 .7 pF
CM
69 .8 W
0.22 mF
348 W
49.9 W
0.1 mF
0.1 mF
Figure 89. THS4509 + ADS5424 Circuit
95
SFDR (dBc)
90
Figure 88. THS4509 + ADS5500 2-Tone FFT with
65 MHz and 70 MHz Input
THS4509 + ADS5424 Combined Performance
Figure 89 shows the THS4509 driving the ADS5424
ADC, and Figure 90 shows their combined SNR and
SFDR performance versus frequency with –1 dBFS
input signal level and sampling at 80 MSPS.
As before, the THS4509 amplifier provides 10 dB of
gain, converts the single-ended input to differential,
and sets the proper input common-mode voltage to
the ADS5424. Input termination and circuit testing is
the same as described above for the THS4509 +
ADS5500 circuit.
The 225-Ω resistors and 2.7-pF capacitor between
the THS4509 outputs and ADS5424 inputs (along
with the input capacitance of the ADC) limit the
bandwidth of the signal to about 100MHz (-3dB).
Since the ADS5424s recommended input common-mode voltage is 2.4 V, the THS4509 is operated
from a single power supply input with VS+ = 5 V and
VS– = 0 V (ground).
24
85
80
SNR (dBFS)
75
70
10
20
30
40
50
Input Frequency - MHz
60
70
Figure 90. THS4509 + ADS5424 SFDR and SNR
Performance vs Frequency
THS4509
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SLOS454 – JANUARY 2005
Layout Recommendations
It is recommended to follow the layout of the external
components near the amplifier, ground plane construction, and power routing of the EVM as closely as
possible. General guidelines are:
1. Signal routing should be direct and as short as
possible into and out of the opamp circuit.
2. The feedback path should be short and direct
avoiding vias.
3. Ground or power planes should be removed from
directly under the amplifier’s input and output
pins.
4. An output resistor is recommended on each
output, as near to the output pin as possible.
5. Two 10-µF and two 0.1-µF power-supply decoupling capacitors should be placed as near to the
power-supply pins as possible.
6. Two 0.1-µF capacitors should be placed between
the CM input pins and ground. This limits noise
coupled into the pins. One each should be placed
to ground near pin 4 and pin 9.
7. It is recommended to split the ground pane on
layer 2 (L2) as shown below and to use a solid
ground on layer 3 (L3). A single-point connection
should be used between each split section on L2
and L3.
8. A single-point connection to ground on L2 is
recommended for the input termination resistors
R1 and R2. This should be applied to the input
gain resistors if termination is not used.
9. The THS4509 recommended PCB footprint is
shown in Figure 91.
0.144
0.049
0.012
Pin 1
0.0095
0.015
0.144
0.0195 0.0705
0.010
vias
0.032
0.030
0.0245
Top View
Figure 91. QFN Etch and Via Pattern
25
THS4509
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SLOS454 – JANUARY 2005
THS4509 EVM
Figure 92 is the THS4509 EVAL1 EVM schematic, layers 1 through 4 of the PCB are shown Figure 93, and
Table 4 is the bill of material for the EVM as supplied from TI.
GND
VS−
J4
VS+
J5
J6
VEE
0.1 µF
TP1
C9
C10
0.1 µF
VCC
10 µF
C4
C15
R12
49.9 Ω
12
0.22 µF
J2
2
3
VO+
−
U1 11
+
R4
100 Ω
R2
69.8 Ω
TP2
C14
0.1 µF
VO−
PwrPad 10
4
R9
open
7
PD
100 Ω
R7
86.6 Ω
R8
86.6 Ω
Vocm
9
15 13
14 16 VEE
R6
J3
T1
R11
69.8 Ω
6
5
4
3
XFMR_ADT4−1WT
R10
open
C1
open
1
C8
open
C7
open
C2
open
J7
348 Ω
TP3
C11
0.1 µF
Figure 92. THS4509 EVAL1 EVM Schematic
Figure 93. THS4509 EVAL1 EVM Layer 1 through 4
26
0.1 µF
C12
VCC
VCC
8
6
5
0.1 µF
C5
J8
348 Ω
R1
69.8 Ω
R3
10 µF
C3
R5
J1
10 µF
10 µF
C6
VEE
C13
THS4509
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SLOS454 – JANUARY 2005
Table 4. THS4509 EVAL1 EVM Bill of Materials
ITEM
DESCRIPTION
SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
PART NUMBER
1
CAP, 10.0 µF, Ceramic, X5R, 6.3V
0805
C3, C4, C5, C6
4
(AVX) 08056D106KAT2A
2
CAP, 0.1 µF, Ceramic, X5R, 10V
0402
C9, C10, C11, C12, C13, C14
6
(AVX) 0402ZD104KAT2A
3
CAP, 0.22 µF, Ceramic, X5R, 6.3V
0402
C15
1
(AVX) 04026D224KAT2A
4
OPEN
0402
C1, C2, C7, C8
4
5
OPEN
0402
R9, R10
2
6
Resistor, 49.9 Ω, 1/16W, 1%
0402
R12
1
(KOA) RK73H1ETTP49R9F
8
Resistor, 69.8 Ω, 1/16W, 1%
0402
R1, R2, R11
3
(KOA) RK73H1ETTP69R8F
9
Resistor, 86.6 Ω, 1/16W, 1%
0402
R7, R8
2
(KOA) RK73H1ETTP86R6F
10
Resistor, 100 Ω, 1/16W, 1%
0402
R3, R4
2
(KOA) RK73H1ETTP1000F
11
Resistor, 348 Ω, 1/16W, 1%
0402
R5, R6
2
(KOA) RK73H1ETTP3480F
12
Transformer, RF
T1
1
(MINI-CIRCUITS) ADT1-1WT
13
Jack, banana receptance, 0.25" diameter
hole
J4, J5, J6
3
(HH SMITH) 101
14
OPEN
J1, J7, J8
3
15
Connector, edge, SMA PCB Jack
J2, J3
2
(JOHNSON) 142-0701-801
16
Test point, Red
TP1, TP2, TP3
3
(KEYSTONE) 5000
17
IC, THS4509
U1
1
(TI) THS4509RGT
18
Standoff, 4-40 HEX, 0.625" length
4
(KEYSTONE) 1808
19
SCREW, PHILLIPS, 4-40, 0.250"
4
SHR-0440-016-SN
20
Printed circuit board
1
(TI) EDGE# 6468901
27
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
THS4509RGTR
ACTIVE
QFN
RGT
16
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
THS4509RGTT
ACTIVE
QFN
RGT
16
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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