FAIRCHILD 4069UB

Revised January 1999
CD4069UBC
Inverter Circuits
General Description
The CD4069UB consists of six inverter circuits and is manufactured using complementary MOS (CMOS) to achieve
wide power supply operating range, low power consumption, high noise immunity, and symmetric controlled rise
and fall times.
This device is intended for all general purpose inverter
applications where the special characteristics of the
MM74C901, MM74C907, and CD4049A Hex Inverter/Buffers are not required. In those applications requiring larger
noise immunity the MM74C14 or MM74C914 Hex Schmitt
Trigger is suggested.
All inputs are protected from damage due to static discharge by diode clamps to VDD and VSS.
Features
■ Wide supply voltage range:
■ High noise immunity:
3.0V to 15V
0.45 VDD typ.
■ Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
■ Equivalent to MM74C04
Ordering Code:
Package Number
Package Description
CD4069UBCM
Order Number
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
CD4069UBCSJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4069UBCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix “X” to the ordering code.
Connection Diagram
Schematic Diagram
Pin Assignments for SOIC and DIP
© 1999 Fairchild Semiconductor Corporation
DS005975.prf
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CD4069UBC Inverter Circuits
October 1987
CD4069UBC
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
(Note 2)
−0.5V to +18 VDC
DC Supply Voltage (VDD)
DC Supply Voltage (VDD)
−0.5V to VDD +0.5 VDC
Input Voltage (VIN)
−65°C to +150°C
Storage Temperature Range (TS)
700 mW
Small Outline
500 mW
−40°C to +85°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and Electrical Characteristics table provide
conditions for actual device operation.
Lead Temperature (TL)
(Soldering, 10 seconds)
0V to VDD VDC
Operating Temperature Range (TA)
Power Dissipation (PD)
Dual-In-Line
3V to 15VDC
Input Voltage (VIN)
Note 2: VSS = 0V unless otherwise specified.
260°C
DC Electrical Characteristics (Note 3)
Symbol
IDD
Parameter
Quiescent Device Current
−40°C
Conditions
Min
VDD = 5V,
Max
+25°C
Min
Typ
+85°C
Max
Min
Max
Units
1.0
1.0
7.5
µA
2.0
2.0
15
µA
4.0
4.0
30
µA
VIN = VDD or VSS
VDD = 10V,
VIN = VDD or VSS
VDD = 15V,
VIN = VDD or VSS
VOL
VOH
VIL
VIH
IOL
IOH
LOW Level Output Voltage
HIGH Level Output Voltage
LOW Level Input Voltage
HIGH Level Input Voltage
VDD = 5V
0.05
0
0.05
0.05
V
VDD = 10V
0.05
0
0.05
0.05
V
VDD = 15V
0.05
0
0.05
0.05
V
|IO| < 1 µA
VDD = 5V
4.95
4.95
4.95
V
VDD = 10V
9.95
9.95
9.95
V
VDD = 15V
14.95
14.95
14.95
V
|IO| < 1 µA
VDD = 5V, VO = 4.5V
1.0
1.0
1.0
VDD = 10V, VO = 9V
2.0
2.0
2.0
V
VDD = 15V, VO = 13.5V
3.0
3.0
3.0
V
V
|IO| < 1 µA
VDD = 5V, VO = 0.5V
4.0
4.0
4.0
VDD = 10V, VO = 1V
8.0
8.0
8.0
V
VDD = 15V, VO = 1.5V
12.0
12.0
12.0
V
V
LOW Level Output Current
VDD = 5V, VO = 0.4V
0.52
0.44
0.88
0.36
mA
(Note 4)
VDD = 10V, VO = 0.5V
1.3
1.1
2.25
0.9
mA
VDD = 15V, VO = 1.5V
3.6
3.0
8.8
2.4
mA
HIGH Level Output Current
VDD = 5V, VO = 4.6V
−0.52
−0.44
−0.88
−0.36
mA
VDD = 10V, VO = 9.5V
−1.3
−1.1
−2.25
−0.9
mA
VDD = 15V, VO = 13.5V
−3.6
−3.0
−8.8
−2.4
(Note 4)
IIN
|IO| < 1 µA
Input Current
−0.30
−10−5
−0.30
−1.0
µA
VDD = 15V, VIN = 15V
0.30
10−5
0.30
1.0
µA
Note 3: VSS = 0V unless otherwise specified.
Note 4: IOH and IOL are tested one output at a time.
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mA
VDD = 15V, VIN = 0V
2
(Note 5)
Symbol
tPHLor tPLH
tTHL or tTLH
Typ
Max
Units
Propagation Delay Time from
Parameter
VDD = 5V
50
90
ns
Input to Output
VDD = 10V
30
60
ns
VDD = 15V
25
50
ns
VDD = 5V
80
150
ns
VDD = 10V
50
100
ns
VDD = 15V
40
80
ns
15
pF
Transition Time
Conditions
Min
CIN
Average Input Capacitance
Any Gate
6
CPD
Power Dissipation Capacitance
Any Gate (Note 6)
12
pF
Note 5: AC Parameters are guaranteed by DC correlated testing.
Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note—
AN-90.
AC Test Circuits and Switching Time Waveforms
3
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CD4069UBC
AC Electrical Characteristics
TA = 25°C, CL = 50 pF, RL = 200 kΩ, tr and tf ≤ 20 ns, unless otherwise specified
CD4069UBC
Typical Performance Characteristics
Ambient Temperature
Gate Transfer Characteristics
Power Dissipation vs
Frequency
Propagation Delay vs
Ambient Temperature
Propagation Delay vs
Propagation Delay Time
vs Load Capacitance
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4
CD4069UBC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm wide
Package Number M14D
5
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CD4069UBC Inverter Circuits
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.