Revised January 1999 MM74C32 Quad 2-Input OR Gate General Description The MM74C32 employs complementary MOS (CMOS) transistors to achieve low power and high noise margin, these gates provide the basic functions used in the implementation of digital integrated circuit systems. The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage. This results in high noise immunity over a wide supply voltage range. No DC power other than that caused by leakage current is consumed during static con- ditions. All inputs are protected against static discharge damage. Features ■ Wide supply voltage range: ■ Guaranteed noise margin: ■ High noise immunity: 3.0V to 15V 1.0V 0.45V VCC (typ.) ■ Low power TTL compatibility: fan out of 2 driving 74L Ordering Code: Order Number Package Number Package Description MM74C32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Top View © 1999 Fairchild Semiconductor Corporation DS005881.prf www.fairchildsemi.com MM74C32 Quad 2-Input OR Gate October 1987 MM74C32 Absolute Maximum Ratings(Note 1) Absolute Maximum VCC −0.3V to VCC + 0.3V Voltage at Any Pin Operating Temperature Range Storage Temperature Range (Soldering, 10 seconds) −40°C to +85°C −65°C to +150°C 700 mW Small Outline 500 mW Operating VCC Range 260°C Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. Power Dissipation (PD) Dual-In-Line 18V Lead Temperature 3.0V to 15V DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VIN(1) Logical “1” Input Voltage VCC = 5.0V 3.5 VCC = 10V 8.0 V V VIN(0) Logical “0” Input Voltage VCC = 5.0V VOUT(1) Logical “1” Output Voltage VCC = 5.0V, IO = −10 µA 4.5 VCC = 10V, IO = −10 µA 9.0 VOUT(0) Logical “0” Output Voltage VCC = 5.0V, IO = 10 µA 0.5 V VCC = 10V, IO = 10 µA 1.0 V 1.5 VCC = 10V 2.0 IIN(1) Logical “1” Input Current VCC = 15V, VIN = 15V IIN(0) Logical “0” Input Current VCC = 15V, VIN = 0V ICC Supply Current VCC = 15V V V V 0.005 −1.0 V 1.0 −0.005 0.05 µA µA 15 µA 0.8 V CMOS/LPTTL INTERFACE VIN(1) Logical “1” Input Voltage VCC = 4.75V VIN(0) Logical “0” Input Voltage VCC = 4.75V VCC − 1.5 VOUT(1) Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA VOUT(0) Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA V 2.4 V 0.4 V OUTPUT DRIVE (see Family Characteristics Data Sheet) TA = 25°C (short circuit current) ISOURCE Output Source Current VCC = 5.0V, VOUT = 0V −1.75 −3.3 mA VCC = 10V, VOUT = 0V −8.0 −15 mA VCC = 5.0V, VOUT = VCC 1.75 3.6 mA VCC = 10V, VOUT = VCC 8.0 16 mA Min (P-Channel) ISOURCE Output Source Current (P-Channel) ISINK Output Sink Current (N-Channel) ISINK Output Sink Current (N-Channel) AC Electrical Characteristics (Note 2) TA = 25°C, CL = 50 pF, unless otherwise specified Symbol Typ Max Units Propagation Delay Time to VCC = 5.0V 80 150 ns Logical “1” or “0” VCC = 10V 35 70 CIN Input Capacitance Any Input (Note 3) 5 pF CPD Power Dissipation Capacitance Per Gate (Note 4) 15 pF tpd Parameter Conditions ns Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: Capacitance is guaranteed by periodic testing. Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note— AN-90. www.fairchildsemi.com 2 MM74C32 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A 3 www.fairchildsemi.com MM74C32 Quad 2-Input OR Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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