Revised August 1999 74F827 • 74F828 10-Bit Buffers/Line Drivers General Description Features The 74F827 and 74F828 10-bit bus buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NOR output enables for maximum control flexibility. ■ 3-STATE output ■ 74F828 is inverting The 74F828 is an inverting version of the 74F827. Ordering Code: Order Number 74F827SC Package Number Package Description M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F827SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 74F828SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F828SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 74F827 © 1999 Fairchild Semiconductor Corporation 74F828 DS009598 www.fairchildsemi.com 74F827 • 74F828 10-Bit Buffers/Line Drivers April 1988 74F827 • 74F828 Logic Symbols 74F827 74F828 IEEE/IEC 74F827 IEEE/IEC 74F828 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL OE1, OE2 Output Enable Input 1.0/1.0 20 µA/−0.6 mA D0–D7 Data Inputs 1.0/1.0 20 µA/−0.6 mA O0–O7 Data Outputs, 3-STATE 600/106.6 (80) −12 mA/64 mA (48 mA) Function Table Functional Description The 74F827 and 74F828 are line drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. The devices have 3-STATE outputs controlled by the Output Enable (OE) pins. The outputs can sink 64 mA and source 15 mA. Input clamp diodes limit high-speed termination effects. Inputs OE Outputs Dn 2 Function 74F828 L H H L Transparent L L L H Transparent H X Z Z High Z H = HIGH Voltage level L = LOW Voltage Level Z = High Impedance X = Immaterial www.fairchildsemi.com On 74F827 74F827 • 74F828 Logic Diagrams 74F827 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F828 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74F827 • 74F828 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output Note 2: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA VOH Output HIGH 10% VCC 2.4 Voltage 10% VCC 2.0 V Min IOH = −15 mA 5% VCC 2.7 Output LOW Voltage IIH V Conditions Input HIGH Voltage VOL 2.0 Units VIH IOH = −3 mA 10% VCC Input HIGH Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD Circuit Current Input LOW Current IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Bus Drainage Test ICCH Power Supply Current (74F827) ICCL 0.55 V Min IOL = 64 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V 50 µA Max VOUT = 2.7V 4.75 Output Leakage IIL Recognized as a LOW Signal IOH = −3 mA Current IBVI Recognized as a HIGH Signal IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded −50 µA Max VOUT = 0.5V −225 mA Max VOUT = 0V 500 µA 0.0V VOUT = 5.25V 30 45 mA Max VO = HIGH Power Supply Current (74F827) 60 90 mA Max VO = LOW ICCZ Power Supply Current (74F827) 40 60 mA Max VO = HIGH Z ICCH Power Supply Current (74F828) 14 20 mA Max VO = HIGH ICCL Power Supply Current (74F828) 56 85 mA Max VO = LOW ICCZ Power Supply Current (74F828) 35 50 mA Max VO = HIGH Z www.fairchildsemi.com −100 4 Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max Min tPLH Propagation Delay 1.0 3.0 5.5 1.0 7.5 1.0 6.5 tPHL Data to Output (74F827) 1.5 3.3 5.5 1.5 7.0 1.5 6.0 Max tPLH Propagation Delay 1.0 3.0 5.0 1.0 5.5 tPHL Data to Output (74F828) 1.0 2.0 4.0 1.0 4.0 tPZH Output Enable Time 3.0 5.7 9.0 2.5 10.0 2.5 9.5 tPZL OE to On 3.5 6.8 11.5 3.0 12.5 3.0 12.0 tPHZ Output Disable Time 1.5 3.3 8.0 1.5 9.0 1.5 8.5 tPLZ OE to On 1.0 3.5 8.0 1.0 9.0 1.0 8.5 5 Units ns ns ns ns www.fairchildsemi.com 74F827 • 74F828 AC Electrical Characteristics 74F827 • 74F828 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B www.fairchildsemi.com 6 74F827 • 74F828 10-Bit Buffers/Line Drivers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com