TPS2410 TPS2411 www.ti.com SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 Full Featured N+1 and ORing Power Rail Controller FEATURES • • • • • • • • • • • • • Control External FET for N+1 and ORing Wide Supply Voltage Range of 3 V to 16.5 V Controls Buses From 0.8 V to 16.5 V Linear or On/Off Control Method Internal Charge Pump for N-Channel MOSFET Rapid Device Turnoff Protects Bus Integrity Positive Gate Control on Hot Insertion Soft Turn on Reduces Bus Transients Input Voltage Monitoring Shorted Gate Monitor MOSFET Control-State Indicator Industrial Temperature Range: –40°C to 85°C Industry-Standard 14-Pin TSSOP Package APPLICATIONS • • • • N+1 Power Supplies Server Blades Telecom Systems High Availability Systems A DESCRIPTION The TPS2410/11 controller, in conjunction with an external N-channel MOSFET, emulates the function of a low forward-voltage diode. The TPS2410/11 can be used to combine multiple power supplies to a common bus in an N+1 configuration, or to combine redundant input power buses. The TPS2410 provides a linear turn-on control while the TPS2411 has an on/off control method. Applications for the TPS2410/11 include a wide range of systems including servers and telecom. These applications often have either N+1 redundant power supplies, redundant power buses, or both. These redundant power sources must have the equivalent of a diode OR to prevent reverse current during faults and hotplug. A TPS2410/11 and N-channel MOSFET provide this function with less power loss than a schottky diode. Accurate voltage sensing, programmable fast turn-off threshold, and input filtering allow operations to be tailored for a wide range of implementations and bus characteristics. A number of monitoring features are provided to indicate voltage bus UV/OV, ON/OFF state, and a shorted MOSFET gate. C C GN D RSV D RSET OV VDD GA TE FL TR A BY P V ol tage Source UV PG FLTB STAT Common V oltage Rail Linear gate control √ √ √ ON/OFF gate control TPS2413 TPS2412 TPS2411 C(FLTR) C(BYP) TPS2410 Table 1. Family Features R(SET) Adjustable turn-off threshold √ √ Fast comparator filtering √ √ Voltage monitoring √ √ Enable control √ √ Mosfet fault monitoring √ √ Status pin √ √ √ √ √ Note: Components on RSET, FLTR, UV and OV are OPTIONAL. Figure 1. Typical Application Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2007, Texas Instruments Incorporated TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) DEVICE TPS2410 TPS2411 (1) (2) TEMPERATURE PACKAGE (2) –40°C to 85°C PW (TSSOP-14) ORDERING CODE MARKING TPS2410PW TPS2410 TPS2411PW TPS2411 Add an R suffix to the device type for tape and reel. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range, voltage are referenced to GND (unless otherwise noted) A, C, FLTR, VDD, STAT voltage –0.3 to 18 V 7.5 V C above A voltage 18 V –0.3 to 30 V –0.3 to 13 V 0.3 V FLTR (3) to C voltage –0.3 to 0.3 V OV, UV voltage –0.3 to 5.5 V RSET voltage (3) –0.3 to 7 V FLTB, PG voltage –0.3 to 18 V STAT, PG, FLTB sink current 40 mA GATE short to A or C or GND Indefinite BYP voltage BYP (3) to A voltage GATE above BYP voltage Human body model Maximum junction temperature Tstg Storage temperature (2) (3) 2 Charged device model TJ (1) UNIT A above C voltage (2) GATE (3), ESD VALUE kV 500 V Internally limited °C –65 to 150 °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. See the section "Bidirectional Blocking and Protection of C." Voltage should not be applied to these pins. DISSIPATION RATINGS 2 PACKAGE θJA– Low k °C/W θJA– High k °C/W POWER RATING High k TA = 85°C (mW) PW (TSSOP) 173 99 404 Submit Documentation Feedback TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 RECOMMENDED OPERATING CONDITIONS voltages are referenced to GND (unless otherwise noted) MIN VDD = V(C) (1) NOM MAX UNIT 3 16.5 0.8 16.5 0 5.25 V 6.8 mA 1.5 ∞ kΩ 0 1000 pF 10k pF A, C Input voltage range TPS2410 A to C Operating voltage (2) OV, UV Voltage range STAT, PG, FLTB Continuous sinking current R(RSET) Resistance range (3) C(FLTR) Capacitance Range (3) C(BYP) Capacitance Range (3) (4) 800 TJ Operating junction temperature –40 125 °C TA Operating free-air temperature –40 85 °C MAX UNIT (1) (2) (3) (4) 3 ≤ VDD ≤ 16.5 V V 5 2200 V VDD must exceed 3 V to meet GATE drive specifications See the section "Bidirectional Blocking and Protection of C." Voltage should not be applied to these pins. Capacitors should be X7R, 20% or better ELECTRICAL CHARACTERISTICS: TPS2410/11 (1) (2) (3) (4) (5) (6) (7) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP V(A), V(C), VDD VDD UVLO A current C current VDD current VDD rising 2.25 2.5 Hysteresis 0.25 | I(A) |, Gate in active range 0.66 | I(A) |, Gate saturated high 0.1 | I(C) |, VAC ≤ 0.1 V 1 10 Worst case, gate in active range 4.25 Gate saturated high 6 1.2 V mA µA mA UV / OV / PG UV threshold voltage V(UV) rising, V(OV) = 0 V, PG goes high 0.583 0.6 0.615 OV threshold voltage V(OV) rising, V(UV) = 1 V, PG goes low 0.583 0.6 0.615 V Response time 50-mV overdrive 0.3 0.6 µs Hysteresis V(UV) and V(OV) PG sink current V(UV) = 0 V, V(OV) = 0 V, V(PG) = 0.4 V 7 mV 4 mA UV / OV leakage current (source or sink) PG leakage current (source or sink) V V(UV) = 1 V, V(OV) = 0 V, 0 ≤ V(PG) ≤ 5 V 1 µA 1 µA FLTB Sink current V(FLTB) = 0.4 V, V(GATE-)A = 0 V, V(A-C) = 0.1 V V(GATE-A) fault threshold V(A) = V(C) + 20 mV, V(GATE-A) falling until FLTB switches low V(A-C) fault threshold V(A-C) = 0.1 V, increase V(A-C) until FLTB switches low Deglitch on assertion mA 0.5 0.78 1 V 0.325 0.425 0.525 V 3.4 Leakage current (source or sink) (1) (2) (3) (4) (5) (6) (7) 4 ms 1 µA [3 V ≤ V(A) ≤ 18 V, V(C) = VDD] or [0.8 V ≤ V(A) ≤ 3 V, 3 V ≤ VDD ≤ 18 V] C(FLTR) = open, C(BYP) = 2200 pF, R(RSET) = open, STAT = open, FLT = open UV = 1 V, OV = GND –40°C ≤ TJ ≤ 125°C Positive currents are into pins Typical values are at 25°C All voltages are with respect to GND. Submit Documentation Feedback 3 TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 ELECTRICAL CHARACTERISTICS: TPS2410/11 (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STAT Sink current V(STAT) = 0.4 V, V(A) = V(C) + 0.1 V Input threshold VDD ≥ 3 V Response time From fast turn-off initiation Source pull-up resistance 4 mA VDD/2 30 46 V 50 ns 60 kΩ FLTR Filter resistance R(FLTR-C) Ω 520 TURN ON TPS2410 forward turn-on and regulation voltage TPS2410 forward turn-on / turn-off difference 7 10 7 10 R(RSET) = open TPS2411 forward turn-on voltage 13 7 mV mV 13 mV TURN OFF GATE sinks > 10 mA at V(GATE-A) = 2 V Fast turn-off threshold voltage V(A-C) falling, R(RSET) = open 1 3 5 V(A-C) falling, R(RSET) = 28.7 kΩ -17 -13.25 -10 V(A-C) falling, R(RSET) = 3.24 kΩ -170 -142 -114 Additional threshold shift with STAT held low mV -157 mV Turn-off delay V(A) = 12 V, V(A-C): 20 mV → -20 mV, V(GATE-A) begins to decrease 70 ns Turn-off time V(A) = 12 V, C(GATE-GND) = 0.01 µF, V(A-C) : 20 mV → -20 mV, measure the period to V(GATE) = V(A) 130 ns GATE Gate positive drive voltage, V(GATE-A) VDD = 3 V, V(A-C) = 20 mV 6 7 8 5 V ≤ VDD≤ 18 V, V(A-C) = 20 mV 9 10.2 11.5 250 290 350 2 5 V(GATE) = 8 V 1.75 2.35 V(GATE) = 5 V Gate source current V(A-C) = 50 mV, V(GATE-A) = 4 V Soft turn-off sink current (TPS2410) V(A-C) = 4 mV, V(GATE-A) = 2 V V µA mA V(A-C) = -0.1 V Fast turn-off pulsed current, I(GATE) Sustain turn-off current, I(GATE) A 1.25 1.75 Period 7.5 12.5 µs V(A-C) = –0.1 V, V(C) = VDD, 3 ≤ VDD ≤ 18 V, 2 V ≤ V(GATE) ≤ 18 V 15 19.5 mA 135 °C 10 °C MISCELLANEOUS Thermal shutdown temperature Temperature rising, TJ Thermal hysteresis 4 Submit Documentation Feedback TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 FUNCTIONAL BLOCK DIAGRAM + - 10 V VDD HVUV A Charge Pump and Bias Supply BYP ’10: AMP. ’11: COMP. + A GATE 10 mV 3 mV ON + - RSET - + - C 0.4 V EN + FLTR EN A FAST COMP. FLTB + - 0.75 V A 3 ms + - C 0.4 V UV o T > 135 C VDC UVLO STAT 0.6V 1 ON PG OV RSVD GND VDC HVUV Bias and Control UVLO EN VBIAS 0.6 V Submit Documentation Feedback 5 TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 PW PACKAGE (TOP VIEW) VDD RSET STAT FLTB OV UV GND PG BYP FLTR A C RSVD GATE TERMINAL FUNCTIONS TERMINAL NAME 6 NO. I/O DESCRIPTION Input power for the gate drive charge pump and internal controls. VDD must be connected to a supply voltage ≥ 3 V. VDD 1 PWR RSET 2 I Connect a resistor to ground to program the turn-off threshold. Leaving RSET open results in a slightly positive V(A-C) turn-off threshold. STAT 3 O STAT is a logical representation of the state of the internal gate-driver. A high output indicates that the MOSFET gate is being driven high. STAT has a weak pull-up to VDD. FLTB 4 O Open drain fault output. Fault is active (low) for any of the following conditions: 1. Insufficient VDD 2. GATE should be high but is not. 3. The MOSFET should be ON but the forward voltage exceeds 0.4 V. OV 5 I OV is a voltage monitor that contributes to the PG output, and also causes the MOSFET to turn off if it is above the 0.6-V threshold. OV is programmable via an external resistor divider. An OV voltage above 0.6 V indicates a bus voltage that is too high. UV 6 I UV is a voltage monitor that contributes to the PG output. The UV input has a 0.6 V threshold and is programmable via an external resistor divider. A UV voltage above 0.6V indicates a bus voltage that is above its minimum acceptable voltage. A low UV input does not effect the gate drive. GND 7 PWR GATE 8 O RSVD 9 PWR C 10 I Voltage sense input that connects to the simulated diode cathode. Connect to the MOSFET drain in the typical configuration. A 11 I Voltage sense input that connects to the simulated diode anode. A also serves as the reference for the charge-pump bias supply on BYP. Connect to the MOSFET source in the typical configuration. FLTR 12 I A capacitor connected from FLTR to A filters the input to the fast comparator. Filtering allows the TPS2410 to ignore spurious transients on the A and C inputs. This pin may be left open to achieve the fastest response time. BYP 13 I/O Connect a storage capacitor from BYP to A to filter the gate drive supply voltage. PG 14 O An open-drain Power Good indicator. PG is open if the UV input is above its threshold, the OV is below its threshold, and the internal UVLO is satisfied. Device ground. Connect to the gate of the external MOSFET. Controls the MOSFET to emulate a low forward-voltage diode. This pin must be connected to GND. Submit Documentation Feedback TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 DETAILED DESCRIPTION The following descriptions refer to the pinout and the functional block diagram. A, C: The A pin serves as the simulated diode anode and the C as the cathode. GATE is driven high when V(AC) exceeds 10 mV. Both devices provide a strong GATE pull-down when V(AC) is less than the programmable fast turn-off threshold. The TPS2410 has a soft pull-down when V(AC) is less than 10 mV but above the fast turn-off threshold. Several internal comparator and amplifier circuits monitor these two pins. The inputs are protected from excess differential voltage by a clamp diode and series resistance. If C falls below A by more than about 0.7 V, a small current flows out of A. Protect the internal circuits with an external clamp if C can be more than 6 V lower than A. A small signal clamp diode and 1-kΩ resistor, or circuit per Figure 18 are suitable. The internal charge pump output, which provides bias power to the comparators and voltage to drive GATE, is referenced to A. Some charge pump current appears on A due to this topology. The A and C pins should be Kelvin connected to the MOSFET source and drain. A and C connections should also be short and low impedance, with special attention to the A connection. Residual noise from the charge pump can be reduced with a bypass capacitor at A if the application permits. BYP: BYP is the internal charge pump output, and the positive supply voltage for internal comparator circuits and GATE driver. A capacitor must be connected from BYP to A. While the capacitor value is not critical, a 2200-pF ceramic is recommended. Traces to this part must be kept short and low impedance to provide adequate filtering. Shorting this pin to a voltage below A damages the TPS2410/11. FLTR: The internal fast comparator input may be filtered by placing a small capacitor from FLTR to A. This is useful in situations where the ambient noise or transients might falsely trigger a MOSFET turnoff. While C(FLTR) will suppress small transients, large voltage reversals will see relatively small additional turn-off delay. FLTR is clamped to C and should only be used with a capacitor as shown in Figure 14. Connections to FLTR should be short and direct to minimize parasitic capacitive loading and crosstalk. The filter pin may not be shorted to any other voltage. FLTB: The FLTB pin is the open-drain fault output. FLTB sinks current when the MOSFET should be enabled, but either there is no GATE voltage, V(AC) is greater than 0.4 V with GATE driven ON, the internal UVLO is not satisfied. FLTB has a 3-ms deglitch filter on the falling edge to prevent transients from creating false signals. FLTB may not be valid at voltages below the internal VDD UVLO. GATE: Gate connects to the external N channel MOSFET gate. GATE is driven positive with respect to A by a driver operating from the voltage on BYP. A time-limited high current discharge source pulls GATE to GND when the fast turn-off comparator is activated. The high-current discharge is followed by a sustaining pull-down. The turn-off circuits are disabled by the thermal shutdown, leaving a resistive pull-down to keep the gate from floating. The gate connection should be kept low impedance to maximize turn-off current. GND: This is the input supply reference. GND should have a low impedance connection to the ground plane. It carries several Amperes of rapid-rising discharge current when the external MOSFET is turned off, and also carries significant charge pump currents. RSET: A resistor connected from this pin to GND sets the MOSFET fast turn-off comparator threshold. The threshold is slightly positive when the RSET pin is left open. Current drawn by the resistor programs the turn-off voltage to increasing negative values. The TPS2411 must have a negative threshold programmed to avoid an unstable condition at light load. The expression for R(RSET) in terms of the fast comparator-trip voltage, V(OFF), follows. æ ö -470.02 ÷ R(RSET) = ç ç V(OFF) - 0.00314 ÷ è ø (1) The units of the numerator are (V × V/A). V(OFF) is positive for V(A) greater than V(C), V(OFF) is less than 3 mV, and R(RSET) is in ohms. RSVD: Connect to ground. Submit Documentation Feedback 7 TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 DETAILED DESCRIPTION (continued) STAT: STAT indicates the status of the GATE pin drive. The internal weak pull-up drives STAT high when GATE is being driven high and V(GATE) is 0.4 V greater than V(A). Redundant devices may tie their STAT pins tied together to desensitize turnoff. If STAT is externally pulled low while the pin would otherwise be high, the turn-off threshold is shifted negative from the RSET programmed value. UV, OV, PG: These signals are used to monitor an input voltage for proper range. PG sinks current to GND if UV is below its threshold, OV is above its threshold, or VDD is below the internal UVLO. PG may not be valid when VDD is below the UVLO. A high input on OV causes GATE to be driven low. UV does not effect the MOSFET operation. This permits OV to be used as an active-high disable. OV and UV should be connected to ground when not used, and PG may be left open. Multiple PG pins to be wire ORed using a common pull-up resistor. VDD: VDD is the primary supply for the gate drive charge pump and other internal circuits. This pin must be connected a source that is 3 V or greater when the external MOSFET is to be turned on. VDD may be greater or lower than the controlled bus voltage. A 0.01-µF bypass capacitor, or 10-Ω and a 0.0 1-µF filter, is recommended because charge pump currents are drawn through VDD. 8 Submit Documentation Feedback TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS TPS2410 V(AC) REGULATION VOLTAGE vs TEMPERATURE FAST TURNOFF THRESHOLD vs TEMPERATURE PULSED GATE SINKING CURRENT vs GATE VOLTAGE 3.0 5.0 12.0 R(RSET) = Open o TJ = -40 C 4.5 11.5 2.5 4.0 11.0 o TJ = 25 C 10.0 3.5 I(GATE) − A V(AC) − mV 10.5 3.0 9.5 2.5 9.0 2.0 8.5 1.5 o TJ = 85 C 1.5 TJ = 125oC 1.0 0.5 −20 0 20 40 60 80 100 1.0 −40 120 0.0 −20 0 20 40 60 80 100 0 120 2 TJ − Junction Temperature − C TJ − Junction Temperature − C Figure 2. Figure 3. TURNON DELAY vs VDD (POWER APPLIED UNTIL GATE IS ACTIVE) 4 6 8 10 V(GATE - GND) − V o o Figure 4. VDD CURRENT vs VDD VOLTAGE (GATE SATURATED HIGH) 3.0 60 2.5 50 TJ = -40oC 40 2.0 o TJ = 25 C I(VDD) − mA 8.0 −40 Delay − ms V(AC) − mV 2.0 30 TJ = 125oC o TJ = 25 C 1.5 1.0 20 o TJ = -40 C o TJ = 125 C 10 0.5 0.0 0 2 4 6 8 10 12 14 16 18 2 4 6 8 10 12 VDD − V VDD − V Figure 5. Figure 6. Submit Documentation Feedback 14 16 18 9 TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) TYPICAL TURNOFF WITH TWO ORED DEVICES ACTIVE (VDD = 12 V, I(LOAD) = 5 A, IRL3713, TRANSIENT APPLIED TO LEFT SIDE) V(AC) (Left) at 20 mV/div V(GATE) (Right) at 5 V/div V(AC) V(GATE) (Left) at 5 V/div V(STAT) GATE V(STAT) (Left) at 10 V/div 50 ns/div Figure 7. TYPICAL TURNOFF AND RECOVERY WITH TWO ORED DEVICES ACTIVE (VDD = 3 V, VA = 18 V, I(LOAD) = 5 A, IRL3713, TRANSIENT APPLIED TO LEFT SIDE) V(AC) (Left) at 10 mV/div V(IN) V(AC) V(IN) (Right) at 20 mVac/div V(GATE) (Right) at 10 V/div V(GATE) (Left) at 10 V/div GATE 500 μs/div Figure 8. 10 Submit Documentation Feedback TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 TYPICAL CHARACTERISTICS (continued) TURNOFF TIME WITH C(GATE) = 10 nF and V(AC) = -20 mV, VDD = VA = 12 V V(AC) V(GATE) at 5 V/div V(AC) at 20 mV/div I(GATE) at 2 A/div I(GATE GATE Delay = 68 ns, V(GATE) = 12 V at 103 ns 20 ns/div Figure 9. TURNOFF TIME WITH C(GATE) = 10 nF, V(AC) = -20 mV, VDD = 5, VA = 1 V V(AC) V(GATE) at 2 V/div V(AC) at 20 mV/div I(GATE) at 2A/div I(GATE GATE Delay = 70 ns, V(GATE) = 1 V at 113 ns 20 ns/div Figure 10. Submit Documentation Feedback 11 TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 APPLICATION INFORMATION OVERVIEW The TPS2410/11 is designed to allow output ORing in N+1 power supply applications (see Figure 12) and input-power bus ORing in redundant source applications (see Figure 13). The TPS2410/11 and external MOSFET emulate a discrete diode to perform this unidirectional power combining function. The advantage to this emulation is lower forward voltage drop and the ability to tune operation. The TPS2410 turns the MOSFET on with a linear control loop that regulates V(AC) to 10 mV as shown in Figure 11. With the gate low, and V(AC) increasing to 10 mV, the amplifier drives GATE high with all available output current until regulation is reached. The regulator controls V(GATE) to maintain V(AC) at 10 mV as long as the MOSFET rDS(on) × I(DRAIN) is less than this the regulated voltage. The regulator drives GATE high, turning the MOSFET fully ON when the rDS(on) × I(DRAIN) exceeds 10 mV, otherwise V(GATE) will be near V(A) plus the MOSFET gate threshold voltage. If the external circuits force V(AC) below 10 mV and above the programmed fast turnoff, GATE is slowly turned off. GATE is rapidly pulled to ground if V(AC) falls to the RSET programmed fast turn-off threshold. The TPS2411 turns the MOSFET on and off like a comparator with hysteresis as shown in Figure 11. GATE is driven high when V(AC) exceeds 10 mV, and rapidly turned off if V(AC) falls to the RSET programmed fast turn-off threshold. System designs should account for the inherent delay between a TPS2410/11 circuit becoming forward biased, and the MOSFET actually turning ON. The delay is the result of the MOSFET gate capacitance charge from ground to its threshold voltage by the 270 µA gate current. If there are no additional sources holding the ORed rail voltage up, the MOSFET internal diode will conduct and maintain voltage on the ORed output, but there will be some voltage droop. This condition is analogous to the power source being ORed in this case. The DC/DC converter output voltage droops when its load increases from zero to a high value. Load sharing techniques that keep all ORed sources active solve this condition. TPS2410 (See Text) TPS2411 (See Text) V(GATE) V(GATE) Slow Turn-off Range V(A) + 10 V Active Regulation Gnd V(A) + V(T) Gate ON Gate OFF V(AC) 10mV Programmable Fast Turn-off Threshold 3mV 10mV Programmable Fast Turn-off Threshold 3mV V(AC) Figure 11. TPS2410/11 Operation The operation of the two parts is summarized in Table 2. Table 2. Operation as a Function of VAC V(AC) ≤ Turnoff Turnoff Threshold (1)≤ VAC ≤ 10 mV Threshold (1) TPS2410 Strong GATE pull-down (OFF) TPS2411 Strong GATE pull-down (OFF) (1) 12 V(AC) Forced < 10 mV Weak GATE pull-down (OFF) (MOSFET rDS(on) × ILOAD) ≤ 10 mV V(AC) regulated to 10 mV Depends on previous state (Hysteresis region) Turnoff threshold is established by the value of RSET. Submit Documentation Feedback V(AC) > 10 mV GATE pulled high (ON) GATE pulled high (ON) TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 TPS2410 vs TPS2411 – MOSFET CONTROL METHODS The TPS2410 control method yields several benefits. First, the low current GATE driver provides a gentle turn-on and turn-off for slowly rising and falling input voltage. Second, it reduces the tendency for on/off cycling of a comparator based solution at light loads. Third, it avoids reverse currents if the fast turn-off threshold is left positive. The drawback to this method is that the MOSFET appears to have a high resistance at light load when the regulation is active. A momentary output voltage droop occurs when a large step load is applied from a light-load condition. The TPS2410 is a better solution for a mid-rail bus that will be re-regulated. The TPS2411 turns the MOSFET on if V(AC) is greater than 10 mV, and hard off when V(AC) is less than the RSET programmed threshold. There is no linear control range and slow turn-off. The disadvantage is that the turn-off threshold must be negative (unless a specified load is always present) permitting a continuous reverse current. Under a dynamic reverse voltage fault, the lower threshold voltage may permit a higher peak reverse current. There are a number of advantages to this control method. Step loads from a light load condition are handled without a voltage droop beyond I × R. If the redundant converter fails, applications with redundant synchronous converters may permit a small amount of reverse current at light load in order to assure that the MOSFET is all ready on. The TPS2411 is a better solution for low-voltage busses that will not be re-regulated, and that may see large load steps transients. These applications recommendations are meant as a starting point, with the needs of specific implementations over-riding them. N+1 POWER SUPPLY – TYPICAL CONNECTION The N+1 power supply configuration shown in Figure 12 is used where multiple power supplies are paralleled for either higher capacity, redundancy or both. If it takes N supplies to power the load, adding an extra, identical unit in parallel permits the load to continue operation in the event that any one of the N supplies fails. The supplies are ORed together, rather than directly connected to the bus, to isolate the converter output from the bus when it is plugged-in or fails short. The TPS2410/11 with an external MOSFET emulates the function of the ORing diode. It is possible for a malfunctioning converter in an ORed topology to create a bus overvoltage if the loading is less than the converter’s capacity (e.g. N = 1). The ORed topology shown cannot protect the bus from this condition, even if the ORing MOSFET can be turned off. One common solution is to use two MOSFETs in a back-to-back configuration to provide bidirectional blocking. See the section on BIDIRECTIONAL BLOCKING AND PROTECTION OF C. ORed supplies are usually designed to share power by various means, although the desired operation could implement an active and standby concept. Sharing approaches include both passive, or voltage droop, and active methods. Not all of the output ORing devices may be active depending on the sharing control method, bus loading, distribution resistences, and TPS2410/11 settings. Implementation Concept C(BYP) V DD C GATE A BYP Input Voltage GND Power Conversion Block DC/DC Converter CommonBus DC/DC Converter Power Bus Figure 12. N+1 Power Supply Example Submit Documentation Feedback 13 TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 INPUT ORing – TYPICAL CONNECTION Figure 13 shows how redundant buses may be ORed to a common point to achieve higher reliability. It is possible to have both MOSFETs ON at once if the bus voltages are matched, or the combination of tolerance and regulation causes both TPS2410/11 circuits to see a forward voltage. The ORing MOSFET disconnects the lower-voltage bus, protecting the remaining bus from potential overload by a fault. Backplane Power Buses Concept Implementation Common Buses C(BYP) C(BYP) BYP VDD C GATE A BYP VDD C GATE A DC/DC Converter BUS2 BUS1 Hotswap LOAD GND GND Plug-In Unit Figure 13. Example ORing of Input Power Buses SYSTEM DESIGN AND BEHAVIOR WITH TRANSIENTS The power system, perhaps consisting of multiple supplies, interconnections, and loads, is unique for every product. A power distribution has low impedance, and low loss, which yields high Q by its nature. While the addition of lossy capacitors helps at low frequencies, their benefit at high frequencies is compromised by parasitics. Transient events with rise times in the 10-ns range may be caused by inserting or removing units, load fluctuations, switched loads, supply fluctuations, power supply ripple, and shorts. These transients cause the distribution to ring, creating a situation where ORing controllers may trip off unnecessarily. In particular, when an ORing device turns off due to a reverse current fault, there is an abrupt interruption of the current, causing a fast ringing event. Since this ringing occurs at the same point in the topology as the other ORing controllers, they are the most likely to be effected. The ability to operate in the presence of noise and transients is in direct conflict with the goal of precise ORing with rapid response to actual faults. A fast response reduces peak stress on devices, reduces transients, and promotes un-interrupted system operation. However, a control with small thresholds and high speed is most likely to be falsely tripped by transients that are not the result of a fault. The power distribution system should be designed to control the transient voltages seen by fast-responding devices such as ORing and hotswap devices. The TPS2410 was designed with several features to help tune its speed and sensitivity to individual systems. The FLTR pin provides a convenient place to filter the bus voltage before it causes undesired tripping (see Fast Comparator Input Filtering – CFLTR). Some applications may find it possible to use RSET to advantage by setting the reverse turn-off threshold more negative. Last, the STAT pin may be used to desensitize the turnoff threshold of an on-line TPS2410 when a redundant TPS2410 has turned off. This is especially attractive in dual redundant systems (see Input ORing and STAT). Ultimately, the performance may have to be tuned to fit the characteristics of each particular system. 14 Submit Documentation Feedback TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 RECOMMENDED OPERATING RANGE The maximum recommended bus voltage is lower than the absolute maximum voltage ratings on A, C, and VDD solely to provide margin for transients on the bus. Most power systems experience transient voltages above the normal operating level. Short transients, or voltage spikes, may be clamped by the ORing MOSFET to an output capacitor and/or voltage rail depending on the system design. Transient protection, e.g. a TVS diode (transient voltage suppressor, a type of Zener diode), may be required on the input or output if the system design does not inherently limit transient voltages below the TPS2410/11 absolute maximum ratings. If a TVS is required, it must protect to the absolute maximum ratings at the worst case clamping current. The TPS2410/11 will operate properly up to the absolute maximum voltage ratings on A, C, and VDD. TPS2410 REGULATION-LOOP STABILITY The TPS2410 uses an internal linear error amplifier to keep the external MOSFET from saturating at light load. This feature has the benefits of setting a turn-off above 0 V, providing a soft turn-off for slowly decaying input voltages, and helps droop-sharing redundancy at light load. Although the control loop has been designed to accommodate a wide range of applications, there are a few guidelines to be followed to assure stability. • Select a MOSFET C(ISS) of 1 nF or greater • Use low ESR bulk capacitors on the output C terminal, typically greater than 100 µF with less than 50 mΩ ESR • Maintain some minimum operational load (e.g. 100 mA or more) Symptoms of stability issues include V(AC) undershoot and possible fast turn-off on large-transient recovery, and a worst-case situation where the gate continually cycles on and off. These conditions are solved by following the rules above. Loop stability should not be confused with tripping the fast comparator due to V(AC) tripping the gate off. Although not common, a condition may arise where the dc/dc converter transient response may cause the GATE to cycle on and off at light load. The converter experiences a load spike when GATE transitions from OFF to ON because the ORed bus capacitor voltage charges abruptly by as much as a diode drop. The load spike may cause the supply output to droop and overshoot, which can result in the ORed capacitor peak charging to the overshoot voltage. When the supply output settles to its regulated value, the ORed bus may be higher than the source, causing the TPS2410/11 to turn the GATE off. While this may not actually cause a problem, its occurrence may be mitigated by control of the power supply transient characteristic and increasing its output capacitance while increasing the ORed load to capacitance ratio. Adjusting the TPS2410 turn-off threshold or using STAT if possible to desensitize the redundant ORing device may help as well. Careful attention to layout and charge-pump noise around the TPS2410/11 helps with noise margin. The linear gate driver has a pull-up current of 290 µA and pull-down current of 3 mA typical. MOSFET SELECTION AND R(RSET) MOSFET selection criteria include voltage rating, voltage drop, power dissipation, size, and cost. The voltage rating consists of both the ability to withstand the rail voltage with expected transients, and the gate breakdown voltage. The MOSFET gate rating should be the minimum of 12 V or the controlled rail voltage. Typically this requires a ±20 V GATE voltage rating. While rDS(on) is often chosen with the power dissipation, voltage drop, size and cost in mind, there are several other factors to be concerned with in ORing applications. When using the TPS2410, the minimum voltage across the device is 10 mV. A device that would have a lower voltage drop at full-load would be overspecified. When using a TPS2411 or TPS2410 with RSET programmed to a negative voltage, the permitted static reverse current is equal to the turn-off threshold divided by the rDS(on). While this current may actually be desirable in some systems, the amount may be controlled by selection of rDS(on) and RSET. The practical range of rDS(on) runs from the low milliohms to 40 mΩ for a single MOSFET. MOSFETs may be paralleled for lower voltage drop (power loss) at high current. For TPS2410 operation, one should plan for only one of the MOSFETs to carry current until the 10 mV regulation point is exceeded and the loop forces GATE fully ON. TPS2411 operation does not rely on linear range operation, so the MOSFETs are all ON or OFF together except for short transitional times. Beyond the control issues, current sharing depends on the resistance match including both the rDS(on) and the connection resistance. Submit Documentation Feedback 15 TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 The TPS2410 may be used without a resistor on RSET. In this case, the turnoff V(AC) threshold is about 3 mV. The TPS2411 may only be operated without an RSET programming resistor if the loading provides a higher V(AC). A larger negative turnoff threshold reduces sensitivity to false tripping due to noise on the bus, but permits larger static reverse current. Installing a resistor from RSET to ground creates a negative shift in the fast turn-off threshold per Equation 2. æ ö -470.02 ÷ R(RSET) = ç ç V(OFF) - 0.00314 ÷ è ø (2) To obtain a –10 mV fast turnoff ( V(A) is less than V(C) by 10 mV ), R(RSET) = (–470.02/ ( –0.01–0.00314) ) ≈ 35,700Ω. If a 10 mΩ rDS(on) MOSFET was used, the reverse turnoff current is calculated as follows. V(THRESHOLD) I(TURN_OFF) = r DS(on) I(TURN_OFF) = -10 mV 10 mW I(TURN_OFF) = - 1 A (3) The sign indicates that the current is reverse, or flows from the MOSFET drain to source ( C to A ). The turn-off speed of a MOSFET is influenced by the effective gate-source and gate-drain capacitance (CISS). Since these capacitances vary a great deal between different vendor parts and technologies, they should be considered when selecting a MOSFET where the fastest turn-off is desired. GATE DRIVE, CHARGE PUMP AND C(BYP) Gate drive of 270 µA typical is generated by an internal charge pump and current limiter. A separate supply, VDD, is provided to avoid having the large charge pump currents interfere with voltage sensing by the A and C pins. The GATE drive voltage is referenced to V(A) as GATE will only driven high when V(A) > V(C). The recommended capacitor on BYP (bypass) must be used in order to form a quiet supply for the internal high-speed comparator. V(GATE) must not exceed V(BYP). FAST COMPARATOR INPUT FILTERING – C(FLTR) The FLTR (filter) pin enables a simple method of filtering the input to the fast turn-off comparator as demonstrated in Figure 14. To minimize the impact of a bus fault, the ORing controller turns off the external MOSFET as fast as possible when a voltage reversal occurs. However, having a fast reaction increases the likelihood that noise or non-fault transients may cause false triggering. Examples of such transients are ESD, EFT, RF induction, step loads, and insertion of high-inrush units. The effect of the filter on a time-domain transient are illustrated by assuming a step input from positive to negative. The expression for the time to reach 0 V across the fast comparator inputs follows, where the variables are defined in Figure 14. æ v ö tDLY = - R × C(FLTR) × ln ç 2 ÷ è v 2 -v1 ø (4) ( ) Figure 14 graphically illustrates that the external MOSFET is turned off after a longer delay for a small transient than a large voltage reversal. For example, the delay from 10 mV forward to 10-mV reverse is about 52 ns (R = 520 Ω, C = 150 pF), while the delay for a 100-mV reverse transient is 7 ns. It is unlikely that the transient in a real system is a step response, making exact calculations on the effect of the R-C filter to a specific transient difficult. The need for a C(FLTR), and its value, is dependent on the electrical noise environment of the particular system. If the electrical environment is understood, the need for the filter, or its value, is selected based on approximations or simulations. If the system is not understood or does not exist when the TPS2410 circuit design is completed, it is recommended that a C(FLTR) of 100 pF be included in initial schematics. Evaluation of system performance may allow removal of C(FLTR). The tolerance of the internal resistance is about ±25% including temperature variations. 16 Submit Documentation Feedback TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 v1 V 1 Source Comparator Input time Load C(FLTR) V C FLTR-A V(FLTR-A) A V2 Bus Transient Dt DLY Turn-on Amplifier/ Comparator FLTR t DLY vV1 1 VF LTR -A V(FLTR-A) Fast Comparator t DLY Comparator Input time V2 Bus Transient Figure 14. Fast Comparator Input Filtering UV, OV, AND PG The UV and OV inputs can be used in a several ways. These include voltage monitoring and forcing the pass MOSFET off. A voltage bus may be monitored for undervoltage with the UV pin, and overvoltage with the OV pin. Figure 15 demonstrates a basic three resistor divider, however, two separate two resistor dividers may be used. PG is high if V(UV) exceeds the UV threshold, and V(OV) is below the OV threshold, else PG is low. Each of these inputs has a 0.6-V threshold and 7 mV of hysteresis. Optionally, UV and OV may be independently disabled by connecting them to ground, and PG may be left floating if not used. The state of PG is undefined until the internal UVLO is satisfied. GATE is forced low if V(OV) exceeds 0.6 V. This allows OV to be used as an enable as shown in Figure 15. This can be used for testing purposes, or control of back-to-back MOSFETs to force an output off even though V(AC) is greater than 10 mV. Basic Supply Monitoring OV used as an Enable Logic Supply P/O TPS2410 Logic Supply UV RB PG To Monitor P/O TPS2410 UV OV GND OV GND Monitored Input Supply Logic Supply RA PG To Monitor RC Figure 15. UV, OV, AND PG VDD, BYP, and POWERING OPTIONS The separate VDD pin provides flexibility for operational power and controlled rail voltage. While the internal UVLO has been set to 2.5 V, the TPS2410/1 requires at least 3 V to generate the specified GATE drive voltage. Sufficient BYP voltage to run internal circuits occurs at VDD voltages between 2.5 V and 3 V. There are three choices for power, A, C, or a separate supply, two of which are demonstrated in Figure 16. One choice for voltage rails over 3.3 V is to power from C, since it is typically the source of reliable power. Voltage rails below 3.3 V, e.g. 2.5 V and below, should use a separate supply such as 5 V. A separate VDD supply can be used to control voltages above it, for example 5 V powering VDD to control a 12-V bus. Submit Documentation Feedback 17 TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 VDD is the main source of power for the internal control circuits. The charge pump that powers BYP draws most of its power from VDD. The input should be low impedance, making a bypass capacitor a preferred solution. A 10-Ω series resistor may be used to limit inrush current into the bypass capacitor, and to provide noise filtering for the supply. BYP is the interconnection point between a charge pump, V(AC) monitor amplifiers and comparators, and the gate driver. C(BYP) must be used to filter the charge pump. A 2200 pF is recommended, but the value is not critical. Common Bus Common Bus Powering Common Bus Separate Bus Powering 5V 2200pF 10* Input 0.01 mF * Optional Filtering 10* V DD C GATE GND Voltage 0.8 V - 18 V BYP A 0.01 mF V DD C GATE GND BYP A 3.3 V - 18 V 2200pF Input Voltage * Optional Filtering Figure 16. VDD Powering Examples INPUT ORing AND STAT STAT provides information regarding the state of the MOSFET gate drive. STAT is high if GATE is being driven high and V(GATE) exceeds V(A) plus 0.4 V. The STAT pin has a 46-kΩ internal pullup to VDD. The STAT pin may be directly connected to low-voltage logic by using the logic gate' input ESD clamp to control the voltage or by using a much lower pullup resistor (e.g., 5 kΩ) to the logic supply voltage. STAT must be allowed to rise above VDD/2 to avoid effecting the reverse turn-off threshold. The STAT pin can be used to reduce sensitivity in topologies such as Figure 13 by connecting the two STAT pins together. If one of the MOSFET is off, a reverse voltage or transient condition on the second input does not compromise system redundancy. The TPS2410/11 shifts its fast turnoff threshold 157 mV negative when GATE is high, but STAT is low. If the two STAT pins were tied together in Figure 13, a common transient on both input buses is less likely to effect both ORing devices if they were both ON. If the timing of the transient is skewed between the buses, the first device that turns off will pull STAT low, skewing the turnoff threshold on the second device. The transient then is less likely to turn the second device off as its threshold is now more negative. Maintaining at least one device ON avoids both a bus transient due to the current interruption, and momentary downstream hotswap overload when the ORing recovers. The unit's bulk capacitance will undergo a small input voltage step as the ORing MOSFET's diode is shorted by the channel resistance, leading to a current surge. The current surge can generate transient voltages on the power bus that may be of concern. Figure 17 shows how STAT and OV can be used to latch the TPS2410 off. This is useful when a system operation benefits from preventing a failed power module from repeatedly disturbing the bus, and may be used in conjunction with back-to-back MOSFETs. The OV pin must be help low until V(GATE) is 0.4 V above V(A) in order to accomplish a reset. 18 Submit Documentation Feedback TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 Logic Rail OV GND Pull Low to Reset STAT Figure 17. Use of STAT and OV to Latch TPS2411 OFF BIDIRECTIONAL BLOCKING AND PROTECTION OF C The TPS2410/11 may be used in applications where bidirectional blocking is desired. This may occur in situations where two different voltages are ORed together, and operation from the lower voltage is desired. Another important application allows isolation of a redundant unit that is generating too high an output voltage. There are two considerations, first is the selection of the VDD source, and second is protection of the C pin from excessive current. Figure 18 provides an example of this type of application. VDD needs to have voltage applied when A is to be connected to the load. Connecting VDD to C only works when voltage on C is always present before A is connected. VDD may be connected to A, a separate supply, or have voltage from A ORed with voltage from C. OV may be used to force GATE low, even when V(A) is greater than V(C), by driving OV to a voltage between 0.6 V and less than 5.25 V. The C pin must be protected from excessive current if V(A) can exceed V(C) by more than 5.5 V. With a single MOSFET, V(C) will never be more than a diode drop lower than V(A). When V(AC) is greater than a diode drop, a small current flows out of the C pin into the load. If V(AC) exceeds 5.5 V, a current limiting circuit should be used to protect C. Figure 18 provides an example circuit. Inserting this protection circuit creates a small offset in the forward regulation and threshold voltage. C GATE BY P A SST270 VDD 1kW C(BYP) Switchable Input Power Bus UV OV GND Control Figure 18. Bidirectional Blocking Example Submit Documentation Feedback 19 TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 ORing EXAMPLES Applications with the TPS2410/11 are not limited to ORIng of identical sections. The TPS2410/11 and external MOSFET form a general purpose function block. Figure 19 shows a circuit with ORing between a discrete diode and a TPS2410/MOSFET section. This circuit can be used to combine two different voltages in cases where the output is reregulated, and the additional voltage drop in the Input 1 path is not a concern. An example is ORing of an ac adapter on Input 1 with a lower voltage on Input 2 Figure 20 shows an improved efficiency version of the first in which a P MOSFET replaces the simple diode. This circuit may not be useful in applications where Input 1 may be shorted because the P MOSFET is not managed, permitting reverse current flow. Input 2 should be the lower of the two voltage rails. If Input 1 was the lower voltage rail and connected first, then Input 2 is connected, there will be a momentary reverse current in the P MOSFET. The reverse current occurs because the STAT signal will not go high until VGATE ramps above Input 2 (the higher voltage) by 0.4 V. The Input 1 to Input 2 difference voltage momentarily appears across the PMOS device which is turned on until STAT switches high, causing a reverse current. The highest efficiency with the best fault tolerance is provided by two TPS2410/MOSFET sections. Input 1 Input 1 Input 2 Output Output Input 2 2 2 0 0 pF 2200 pF 10 kW VDD C GATE BYP A VDD C GATE A BYP GND GND Figure 19. ORing Circuit STAT Figure 20. P MOSFET Circuit The TPS2410 may be a better choice in applications where inputs may be removed, causing an open-circuit input. If the MOSFET was ON when the input is removed, VAC will be virtually zero. If the reverse turn-off threshold is programmed negative, the TPS2410/11 will not pull GATE low. A system interruption could then be created if a short is applied to the floating input. For example, if an ac adapter is first connected to the unit, and then connected to the ac mains, the adapter's output capacitors will look like a momentary short to the unit. A TPS2410 with RSET open will turn the MOSFET OFF when the input goes open circuit. SUMMARIZED DESIGN PROCEDURE The following is a summarized design procedure: 1. Choose between the TPS2410 or 2411, see TPS2410 vs TPS2411 – MOSFET Control Methods 2. Choose the VDD source. Table 3 provides a guide for where to connect VDD that covers most cases. VDD may be directly connected to the supply, but an R(VDD) / C(VDD) of 10 Ω / 0.01 µF is recommended. Table 3. VDD Connection Guide VA < 3 V Bias Supply > 3 V 20 3 V ≤ VA ≤ 3.5 V VA or Bias Supply > 3 V. VC if always > 3 V Submit Documentation Feedback VA > 3.5 V VC, VA or Bias for special configurations TPS2410 TPS2411 SLVS727B – NOVEMBER 2006 – REVISED FEBRUARY 2007 3. Noise voltage and impedance at the A pin should be kept low. C(A) may be required if there is noise on the bus, or A is not low impedance. If either of these is a concern, a C(A) of 0.01 µF or more may be required. 4. Select C(BYP) as 2200 pF, X7R, 25-V or 50-V ceramic capacitor. 5. If the noise and transient environment is not well known, design C(FLTR) in, then experimentally determine if it is required. Start with a 100 pF, X7R, 25-V or 50-V ceramic capacitor and adjust if necessary. 6. Select M1 based on considerations of voltage drop, power dissipated, voltage ratings, and gate capacitance. See sections: MOSFET Selection and RSET and TPS2410 Regulation-Loop Stability. 7. Select R(RSET) based on which MOSFET was chosen and reverse current considerations – see MOSFET Selection and RSET. If the noise and transient environment is not well known, make provision for R(RSET) even when using the TPS2410. 8. Configure the UV and OV inputs per the desired behavior – UV, OV, and PG. Calculate the resistor dividers. 9. Add optional interface for PG, FLTB, and STAT as desired. 10. Make sure to connect RSVD to ground. C(VDD) C Logic Voltage FLTB GND STAT R(RSET) R(C) R SV D OV Optional Logic Interface PG R SET R(B) V DD GA TE FLTR A BY P UV Input Voltage See Text Common Voltage 10 kW C(FLTR) C(BYP) C(A) R(A) R(VDD) 10 kW M1 Figure 21. Design Template Layout Considerations See Figure 21 for reference designations. 1. The TPS2410/11, M1, and associated components should be used over a ground plane. 2. The GND connection should be short with multiple vias to ground. 3. C(VDD) should be adjacent to the VDD pin with a minimal ground connection length to the plane. 4. The GATE connection should be short and wide (e.g., 0.025" minimum). 5. The C pin should be Kelvin connected to M1. 6. The A pin should be a short, wide, Kelvin connection to M1 and the bus. 7. C(BYP), C(FLTR), and R(RSET) should be kept immediately adjacent to the TPS2410/11 with short leads. 8. Do not run noisy signals adjacent to FLTR. Submit Documentation Feedback 21 PACKAGE OPTION ADDENDUM www.ti.com 7-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS2410PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2410PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2410PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2410PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2411PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2411PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2411PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2411PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device TPS2410PWR 17-May-2007 Package Pins PW 14 Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) MLA 330 12 7.0 5.6 1.6 8 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) TPS2410PWR PW 14 MLA 342.9 336.6 20.6 Pack Materials-Page 2 W Pin1 (mm) Quadrant 12 PKGORN T1TR-MS P MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. 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