ONSEMI NTLUS4195PZ

NTLUS4195PZ
Power MOSFET
−30 V, −4.0 A, mCoolt Single P−Channel,
ESD, 1.6x1.6x0.55 mm UDFN Package
Features
• UDFN Package with Exposed Drain Pads for Excellent Thermal
•
•
•
•
•
Conduction
Low Profile UDFN 1.6 x 1.6 x 0.55 mm for Board Space Saving
Lowest RDS(on) in 1.6x1.6 Package
ESD Protected
This is a Halide Free Device
This is a Pb−Free Device
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MOSFET
V(BR)DSS
−30 V
RDS(on) MAX
ID MAX
90 mW @ −10 V
−3.0 A
155 mW @ −4.5 V
−2.0 A
Applications
• High Side Load Switch
• PA Switch and Battery Switch
• Optimized for Power Management Applications for Portable
S
Products, such as Cell Phones, PMP, DSC, GPS, and others
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol
Value
Units
Drain-to-Source Voltage
VDSS
−30
V
Gate-to-Source Voltage
VGS
±20
V
ID
−3.0
A
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
Continuous Drain
Current (Note 2)
Steady
State
TA = 25°C
TA = 85°C
−2.3
t≤5s
TA = 25°C
−4.0
Steady
State
TA = 25°C
t≤5s
TA = 25°C
Steady
State
TA = 25°C
PD
ID
W
1.5
A
−2.0
−1.5
TA = 25°C
PD
0.6
W
Pulsed Drain Current
tp = 10 ms
IDM
−17
A
TJ,
TSTG
-55 to
150
°C
Source Current (Body Diode) (Note 2)
IS
−1.0
A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Gate-to-Source ESD Rating
(HBM) per JESD22−A114F
ESD
June, 2009 − Rev. 0
1
AC MG
G
AC = Specific Device Code
M = Date Code
G = Pb−Free Package
Class 1B
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface-mounted on FR4 board using the minimum recommended pad size
of 30 mm2, 2 oz. Cu.
© Semiconductor Components Industries, LLC, 2009
1
UDFN6
CASE 517AU
mCOOLt
(Note: Microdot may be in either location)
Power Dissipation (Note 2)
Operating Junction and Storage
Temperature
MARKING
DIAGRAM
6
2.3
TA = 85°C
D
P−Channel MOSFET
1
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Publication Order Number:
NTLUS4195PZ/D
NTLUS4195PZ
THERMAL RESISTANCE RATINGS
Symbol
Max
Units
Junction-to-Ambient – Steady State (Note 3)
RθJA
85
°C/W
Junction-to-Ambient – t ≤ 5 s (Note 3)
RθJA
55
Junction-to-Ambient – Steady State min Pad (Note 4)
RθJA
200
Parameter
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
−30
Typ
Max
Units
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = −250 mA
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
ID = −250 mA, ref to 25°C
Zero Gate Voltage Drain Current
Gate-to-Source Leakage Current
IDSS
VGS = 0 V,
VDS = −30 V
V
28
mV/°C
TJ = 25°C
−1.0
TJ = 85°C
−10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = −250 mA
10
mA
mA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temp. Coefficient
Drain-to-Source On Resistance
Forward Transconductance
−1.0
VGS(TH)/TJ
−3.0
3.8
RDS(on)
gFS
V
mV/°C
mW
VGS = −10 V, ID = −3.0 A
75
90
VGS = −4.5 V, ID = −2.0 A
120
155
VDS = −5.0 V, ID = −0.2 A
1.3
S
250
pF
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
CISS
VGS = 0 V, f = 1 MHz,
VDS = −15 V
COSS
CRSS
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate-to-Source Charge
QGS
Gate-to-Drain Charge
QGD
60
40
3.2
VGS = −4.5 V, VDS = −15 V;
ID = −3.0 A
5.0
nC
0.2
1.0
1.5
SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6)
Turn-On Delay Time
td(ON)
30
tr
95
Rise Time
Turn-Off Delay Time
td(OFF)
Fall Time
VGS = −4.5 V, VDD = −15 V,
ID = −3.0 A, RG = 1 W
tf
ns
50
70
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
3.
4.
5.
6.
VGS = 0 V,
IS = −1.0 A
TJ = 25°C
0.8
TJ = 85°C
0.7
11
VGS = 0 V, dISD/dt = 100 A/ms,
IS = −1.0 A
QRR
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2
V
ns
7.5
3.5
5.0
Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 1 oz. Cu.
Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
Switching characteristics are independent of operating junction temperatures.
1.2
nC
NTLUS4195PZ
TYPICAL CHARACTERISTICS
−6.0 V
−8.0 V
14
−5.0 V
12
−4.5 V
10
−4.0 V
8
−3.5 V
6
4
−3.0 V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.5
4.0
6
5
4
5.0
TJ = 25°C
3
2
TJ = 125°C
1
1.5
2
TJ = −55°C
2.5
3
3.5
4.5
4
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
TJ = 25°C
0.200
0.175
ID = −3.0 A
0.150
0.125
0.100
0.075
4.0
5.0
6.0
7.0
8.0
9.0
10
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−VGS, GATE−TO−SOURCE VOLTAGE (V)
0.225
5
0.250
0.225
TJ = 25°C
0.200
0.175
VGS = −4.5 V
0.150
0.125
0.100
VGS = −10 V
0.075
0.050
0.025
0
0
2
4
6
8
10
12
14
16
18
20
−VGS, GATE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.6
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE (W)
7
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.250
0.050
3.0
8
1
0
−2.5 V
0
VDS ≤ −10 V
9
1000
VGS = −10 V
ID = −3.0 A
1.5
1.4
1.3
−IDSS, LEAKAGE (nA)
−ID, DRAIN CURRENT (A)
−7.0 V
−9.0 V
16
2
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
10
VGS = −10 V
18
−ID, DRAIN CURRENT (A)
20
VGS = −4.5 V
ID = −2.0 A
1.2
1.1
1.0
0.9
0.8
TJ = 150°C
100
TJ = 125°C
10
TJ = 85°C
0.7
0.6
−50
−25
0
25
50
75
100
125
150
1
0
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
30
NTLUS4195PZ
VGS = 0 V
TJ = 25°C
f = 1 MHz
350
C, CAPACITANCE (pF)
300
Ciss
250
200
150
100
Coss
50
0
Crss
0
5
10
15
20
30
25
5
4
QGS
12
9
2
6
VDS = −15 V
ID = −3.0 A
TJ = 25°C
1
0
0
0.5
1
1.5
2
2.5
3
0
3.5
3
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
10
1000
100
−IS, SOURCE CURRENT (A)
VGS = −4.5 V
VDD = −15 V
ID = −3.0 A
t, TIME (ns)
VGS
QGD
3
Figure 7. Capacitance Variation
tr
tf
td(off)
td(on)
1
10
TJ = 150°C
1
0.1
0.3
100
0.4
0.5
0.6
TJ = 25°C
0.7
0.8
0.9
1.0
1.1
RG, GATE RESISTANCE (W)
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
2.0
1.9
1.8
ID = −250 mA
1.7
POWER (W)
−VGS(th) (V)
15
VDS
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
10
18
QT
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
400
−VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
1.6
1.5
1.4
1.3
1.2
−50
−25
0
25
50
75
100
125
150
65
60
55
50
45
40
35
30
25
20
15
10
5
0
1.E−04 1.E−03 1.E−02 1.E−01 1.E+00 1.E+01 1.E+02 1.E+03
TJ, JUNCTION TEMPERATURE (°C)
SINGLE PULSE TIME (s)
Figure 11. Threshold Voltage
Figure 12. Single Pulse Maximum Power
Dissipation
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4
1.2
NTLUS4195PZ
TYPICAL CHARACTERISTICS
−ID, DRAIN CURRENT (A)
100
10
10 ms
100 ms
1
0.1
0.01
1 ms
VGS > 4.5 V
Single Pulse
TC = 25°C
10 ms
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
dc
10
100
R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
90
RqJA = 85°C/W
80
70
60
50
Duty Cycle = 0.5
40
30
20 0.2
0.05
0.02
0.01
10 0.1
0
1E−06
Single Pulse
1E−05
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
1E+02
1E+03
t, TIME (s)
Figure 14. FET Thermal Response
DEVICE ORDERING INFORMATION
Package
Shipping†
NTLUS4195PZTAG
UDFN6
(Pb−Free)
3000 / Tape & Reel
NTLUS4195PZTBG
UDFN6
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
NTLUS4195PZ
PACKAGE DIMENSIONS
UDFN6 1.6x1.6, 0.5P
CASE 517AU−01
ISSUE O
A
B
D
2X
0.10 C
ÉÉ
ÉÉ
PIN ONE
REFERENCE
2X
DETAIL A
OPTIONAL
CONSTRUCTION
0.10 C
EXPOSED Cu
TOP VIEW
A
DETAIL B
0.05 C
0.05 C
A1
SIDE VIEW
C
ÉÉ
ÉÉ
F
3
1
A3
DETAIL B
OPTIONAL
CONSTRUCTION
SEATING
PLANE
D2
0.82
E2
G
0.10 C A B
6
4
D1
BOTTOM VIEW
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.13 REF
0.20
0.30
1.60 BSC
1.60 BSC
0.50 BSC
0.62
0.72
0.15
0.25
0.57
0.67
0.55 BSC
0.25 BSC
0.20
0.30
−−−
0.15
SOLDERMASK DEFINED
MOUNTING FOOTPRINT*
L
DETAIL A
DIM
A
A1
A3
b
D
E
e
D1
D2
E2
F
G
L
L1
MOLD CMPD
e
0.10 C A B
6X
(A3)
A1
NOTE 4
L1
L
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
6X
0.16
0.43
0.68
2X
0.35
b
0.10 C A B
0.05 C
1.90
NOTE 3
0.28
1
6X
0.32
0.50 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION
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6
ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
Sales Representative
NTLUS4195PZ/D