ONSEMI NTLJD2104PTAG

NTLJD2104P
Power MOSFET
−12 V, −4.3 A, mCOOLE Dual P−Channel,
2x2 mm, WDFN package
Features
• WDFN 2x2 mm Package with Exposed Drain Pads for Excellent
•
•
•
•
•
Thermal Conduction
Lowest RDS(on) in 2x2 mm Package
Footprint Same as SC−88 Package
Low Profile (<0.8 mm) for Easy Fit in Thin Environments
Bidirectional Current Flow with Common Source Configuration
These are Pb−Free Devices
Applications
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−12 V
• Optimized for Battery and Load Management Applications in
•
•
Portable Equipment
Li Ion Battery Charging and Protection Circuits
Dual High Side Load Switch
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
−12
V
Gate−to−Source Voltage
VGS
±8.0
V
ID
−3.5
A
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
Steady
State
TJ = 25°C
TJ = 85°C
−2.5
t≤5s
TJ = 25°C
−4.3
Steady
State
PD
Continuous Drain
Current (Note 2)
Power Dissipation
(Note 2)
ID
TJ = 85°C
W
IDM
−20
A
TJ, TSTG
−55 to
150
°C
Source Current (Body Diode) (Note 2)
IS
−1.5
A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
tp = 10 ms
Operating Junction and Storage Temperature
85 mW @ −2.5 V
−3.0 A
110 mW @ −1.8 V
−0.7 A
140 mW @ −1.5 V
−0.5 A
190 mW @ −1.3 V
−0.2 A
230 mW @ −1.2 V
−0.2 A
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface Mounted on FR4 Board using the minimum recommended pad size
of 30 mm2, 2 oz. Cu.
S2
D1
P−CHANNEL MOSFET
D2
P−CHANNEL MOSFET
MARKING
DIAGRAM
D1
WDFN6
CASE 506AN
−1.7
0.7
Pulsed Drain Current
−3.0 A
G2
A
−2.4
PD
TJ = 25°C
60 mW @ −4.5 V
G1
D2
2.3
TJ = 25°C
Steady
State
W
1.5
TJ = 25°C
t≤5s
ID MAX
S1
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
RDS(on) TYP
V(BR)DSS
Pin 1
1
6
2 JCMG 5
G
3
4
JC = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
D1
S1
1
G1
2
6
D1
5
G2
4
S2
D2
D2
3
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
October, 2008 − Rev. 2
1
Publication Order Number:
NTLJD2104P/D
NTLJD2104P
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
Junction−to−Ambient – Steady State (Note 3)
RqJA
83
Junction−to−Ambient – Steady State Min Pad (Note 4)
RqJA
177
Junction−to−Ambient – t ≤ 5 s (Note 3)
RqJA
54
Unit
SINGLE OPERATION (SELF−HEATED)
°C/W
DUAL OPERATION (EQUALLY HEATED)
Junction−to−Ambient – Steady State (Note 3)
RqJA
58
Junction−to−Ambient – Steady State Min Pad (Note 4)
RqJA
133
Junction−to−Ambient – t ≤ 5 s (Note 3)
RqJA
40
°C/W
3. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
4. Surface Mounted on FR4 Board using the minimum recommended pad size (30 mm2, 2 oz Cu).
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Test Conditions
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = −250 mA
−12
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
ID = −250 mA, Ref to 25°C
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
VDS = −12 V, VGS = 0 V
V
−7.0
mV/°C
TJ = 25°C
−1.0
TJ = 85°C
−10
IGSS
VDS = 0 V, VGS = ±8.0 V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = −250 mA
Gate Threshold
Temperature Coefficient
VGS(TH)/TJ
mA
$100
nA
−0.8
V
ON CHARACTERISTICS (Note 5)
Drain−to−Source On−Resistance
Forward Transconductance
−0.35
−0.6
2.4
RDS(on)
VGS = −4.5, ID = −3.0 A
gFS
mV/°C
60
90
mW
VGS = −2.5, ID = −3.0 A
85
120
VGS = −1.8, ID = −0.7 A
110
150
VGS = −1.5, ID = −0.5 A
140
200
VGS = −1.3, ID = −0.2 A
190
VGS = −1.2, ID = −0.2 A
230
VDS = −10 V, ID = −3.0 A
6.0
S
467
pF
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VGS = 0 V, f = 1.0 MHz,
VDS = −6.0 V
125
79
Total Gate Charge
QG(TOT)
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
1.5
RG
12.2
Gate Resistance
5.5
VGS = −4.5 V, VDS = −6.0 V,
ID = −3.0 A
5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
8.0
nC
0.3
0.8
W
NTLJD2104P
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
td(ON)
tr
Turn−Off Delay Time
Fall Time
td(OFF)
ns
6.6
VGS = −4.5 V, VDD = −6.0 V,
ID = −3.0 A, RG = 2.0 W
tf
12.3
14
16.2
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Recovery Voltage
Reverse Recovery Time
VSD
VGS = 0 V, IS = −1.0 A
TJ = 25°C
−0.7
TJ = 85°C
−0.65
tRR
23
Charge Time
ta
8.0
Discharge Time
tb
Reverse Recovery Time
VGS = 0 V, dISD/dt = 100 A/ms,
IS = −1.0 A
QRR
−1.0
V
45
ns
20
nC
15
10
5. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
Package
Shipping†
NTLJD2104PTBG
WDFN6
(Pb−Free)
3000 / Tape & Reel
NTLJD2104PTAG
WDFN6
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
NTLJD2104P
TYPICAL CHARACTERISTICS
10
−2.5 V
VDS = −5.0 V
−ID, DRAIN CURRENT (A)
12
10
8.0
−2.0 V
6.0
−1.8 V
4.0
−1.5 V
2.0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VGS = −4.5 V to −3 V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
TJ = 25°C
2.0
4.0
4.5
0
5.0
0.75
1.0
1.25
1.5
1.75
−VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
TJ = 25°C
ID = −3 A
0.16
0.14
0.12
0.10
0.08
0.06
0.04
1.0
0.5
TJ = −55°C
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.18
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.50
VGS = −1.5 V
0.45
−1.8 V
−2.0 V
2.0
TJ = 25°C
0.40
0.35
0.30
0.25
0.20
0.15
−2.5 V
0.10
0.05
0
−4.5 V
0
2.0
4.0
6.0
8.0
10
−VGS, GATE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10,000
1.5
1.4
TJ = 150°C
VGS = −4.5 V
ID = −3 A
1.3
IDSS, LEAKAGE (nA)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE (W)
6.0
TJ = 125°C
0.20
0.02
8.0
−1.2 V
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (A)
14
1.2
1.1
1.0
0.9
TJ = 125°C
0.8
0.7
−50
−25
0
25
50
75
100
125
150
1000
1
TJ, JUNCTION TEMPERATURE (°C)
2
3
4
5
6
7
8
9
10
11
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
12
NTLJD2104P
TYPICAL CHARACTERISTICS
VGS = 0 V
TJ = 25°C
f = 1 MHz
Ciss
600
−VGS, GATE−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
700
4
500
Coss
300
0
2
4
6
8
10
QGS
QGD
VDS = −6 V
ID = −3 A
TJ = 25°C
0
1
2
3
4
5
2
6
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
QG, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
0
100
100
−IS, SOURCE CURRENT (A)
VGS = −4.5 V
VDD = −6 V
ID = −3 A
t, TIME (ns)
4
0
12
1000
td(off)
tf
tr
10
td(on)
1
10
TJ = 150°C
10
TJ = 25°C
1
0.1
100
0.2
0.4
0.6
0.8
1.0
1.2
1.4
RG, GATE RESISTANCE (W)
−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
30
0.8
0.7
25
ID = −250 mA
0.6
POWER (W)
−VGS(th) (V)
−VGS
1
Crss
100
1
−VDS
2
200
0
6
3
400
8
QT
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
5
800
0.5
0.4
20
15
10
5
0.3
0.2
−50
*See Note 2 on Page 1
−25
0
25
50
75
100
125
0
150
0.001
0.01
0.1
1
10
100
TJ, TEMPERATURE (°C)
SINGLE PULSE TIME (s)
Figure 11. Threshold Voltage
Figure 12. Single Pulse Maximum Power
Dissipation
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5
1000
NTLJD2104P
TYPICAL CHARACTERISTICS
−ID, DRAIN CURRENT (A)
100
*See Note 2 on Page 1
VGS = −8 V
Single Pulse
TC = 25°C
10
100 ms
1 ms
1
10 ms
0.1
0.01
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
dc
10
100
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
1000
R(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
*See Note 2 on Page 1
100
Duty Cycle = 0.5
0.2
0.1
10
0.05
1
0.1
Single Pulse
1E−06
1E−05
1E−04
1E−03
1E−02
1E−01
t, TIME (s)
Figure 14. FET Thermal Response
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6
1E+00
1E+01
1E+02
1E+03
NTLJD2104P
PACKAGE DIMENSIONS
D
WDFN6 2x2
CASE 506AN−01
ISSUE C
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
PIN ONE
REFERENCE
0.10 C
2X
2X
ÍÍÍ
ÍÍÍ
ÍÍÍ
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
J
0.10 C
A3
0.10 C
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.25
0.35
2.00 BSC
0.57
0.77
2.00 BSC
0.90
1.10
0.65 BSC
0.25 REF
0.30
0.20
0.15 REF
A
6X
0.08 C
SOLDERING FOOTPRINT*
A1
C
D2
D2
6X
1
2.30
6X
0.43
e
L
SEATING
PLANE
4X
1
3
0.65
PITCH
2X E2
6X
K
6
6X
6X
0.35
4
0.25
b
J
BOTTOM VIEW
6X
0.10 C A
0.05 C
2X
B
0.72
NOTE 3
1.05
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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NTLJD2104P/D