TI THS4011CD

THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
D
1
8
2
7
3
6
4
1OUT
1IN –
1IN +
–VCC
NULL
VCC+
OUT
NC
5
1
8
2
7
3
6
4
5
VCC+
2OUT
2IN–
2IN+
NC – No internal connection
Cross Section View Showing
PowerPAD Option (DGN)
† This device is in the Product Preview stage of development.
Please contact your local TI sales office for availability.
THS4011
FK PACKAGE
(TOP VIEW)
NULL
NC
NULL
The THS4011 and THS4012 are very high speed,
single/dual, voltage feedback amplifiers ideal for
a wide range of applications. The devices offer
very good ac performance with 290-MHz
bandwidth, 310-V/µs slew rate, and 37-ns settling
time (0.1%). These amplifiers have a high output
drive capability of 110 mA and draw only 7.8-mA
supply current per channel. For applications
requiring low distortion, the THS4011/12 operate
with a total harmonic distortion (THD) of –80 dBc
at f = 1 MHz. For video applications, the
THS4011/12 offer 0.1 dB gain flatness to 70-MHz,
0.006% differential gain error, and 0.01°
differential phase error.
NC
description
3
2
1
20 19
NC
D
D
NULL
IN –
IN +
VCC–
THS4012
D AND DGN† PACKAGE
(TOP VIEW)
NC 4
18 NC
IN– 5
17 VCC+
NC 6
16 NC
IN+ 7
15 OUT
14 NC
9
10 11 12 13
NC
V CC–
NC 8
NC
D
D
D
THS4011
JG, D AND DGN PACKAGE
(TOP VIEW)
NC
D
Very High Speed
– 290 MHz Bandwidth (G = 1, –3 dB)
– 310 V/µs Slew Rate
– 37 ns Settling Time (0.1%)
Very Low Distortion
– THD = –80 dBc (f = 1 MHz, RL = 150 Ω)
110 mA Output Current Drive (Typical)
7.5 nV/√Hz Voltage Noise
Excellent Video Performance
– 70 MHz Bandwidth (0.1 dB, G = 1)
– 0.006% Differential Gain Error
– 0.01° Differential Phase Error
±5 V to ±15 V Supply Voltage
Available in Standard SOIC, MSOP
PowerPAD, JG, or FK Packages
Evaluation Module Available
NC
D
RELATED DEVICES
DEVICE
THS4011/2
THS4031/2
THS4061/2
DESCRIPTION
290-MHz Low Distortion High-Speed Amplifiers
100-MHz Low Noise High Speed-Amplifiers
180-MHz High-Speed Amplifiers
CAUTION: THE THS4011 AND THS4012 provide ESD protection circuitry. However, permanent damage can still occur if this device
is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance
degradation or loss of functionality.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
DISTORTION
vs
FREQUENCY
–40
Distortion – dB
–50
VCC = ± 15 V
RL = 150 Ω
G=2
–60
2nd Harmonic
–70
–80
–90
3rd Harmonic
–100
–110
100k
1M
10M
f – Frequency – Hz
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
NUMBER OF
CHANNELS
PLASTIC
SMALL
OUTLINE†
(D)
0°C to
70°C
1
THS4011CD
2
THS4012CD
–40°C to
85°C
1
THS4011ID
2
THS4012ID
PLASTIC
MSOP†
(DGN)
CERAMIC
DIP
(JG)
CHIP
CARRIER
(FK)
MSOP
SYMBOL
THS4011CDGN
THS4012CDGN‡
—
—
TIACM
THS4011EVM
—
—
TIABD
THS4012EVM
THS4011IDGN
THS4012IDGN‡
—
—
TIACN
—
—
—
TIABZ
—
–55°C to
1
—
—
THS4011MJG
THS4011MFK
—
125°C
† The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4011CDGNR).
‡ This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
EVALUATION
MODULE
—
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
functional block diagram
Null
2
IN–
3
IN+
1
8
–
6
OUT
+
Figure 1. THS4011 – Single Channel
VCC
1IN–
2
8
–
1
1IN+
2IN–
3
6
–
7
2IN+
5
1OUT
+
2OUT
+
4
–VCC
Figure 2. THS4012 – Dual Channel
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 mA
Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Maximum junction temperature, TJ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Operating free-air temperature, TA, THS401xC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
THS401xI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
THS4011M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds, D, DGN package . . . . . . . . . . . . . . . 300°C
Lead temperature, 1,6 mm (1/16 inch) from case for 60 seconds, JG package . . . . . . . . . . . . . . . . . . . 300°C
Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
θJA
(°C/W)
θJC
(°C/W)
TA = 25°C
POWER RATING
D
167†
38.3
740 mW
DGN‡
58.4
4.7
2.14 W
JG
119
28
1050 mW
FK
87.7
20
1375 mW
† This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed
High-K test PCB, the θJA is 95°C/W with a power rating at TA = 25°C of 1.32 W.
‡ This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in.
PC. For further information, refer to Application Information section of this data sheet.
recommended operating conditions
MIN
Operating free-air temperature, TA
4
POST OFFICE BOX 655303
MAX
±4.5
±16
Single supply
9
32
C suffix
0
70
Split supply
Supply voltage
voltage, VCC
NOM
I suffix
–40
85
M suffix
–55
125
• DALLAS, TEXAS 75265
UNIT
V
°C
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics, VCC = ±15 V, RL = 150 Ω, TA = 25°C, (unless otherwise noted)
dynamic performance
THS4011C/I,
THS4012C/I
TEST CONDITIONS†
PARAMETER
MIN
BW
SR
TYP
Unity gain bandwidth (–3
Unity-gain
( 3 dB)
Gain = 1
VCC = ±15 V
VCC = ±5 V
290
0 1 dB flatness
Bandwidth for 0.1
Gain = 1
VCC = ±15 V
VCC = ±5 V
70
Full power bandwidth (see Note 2)
VCC = ±15 V, RL = 150 Ω
VCC = ±5 V, RL = 150 Ω,
VO(PP) = 20 V,
VO(PP) = 5 V,
4.9
Slew rate
Gain = –1,
1
VCC = ±15 V
VCC = ±5 V
310
Settling time to 0.1%
0 1%
VI = –2.5
2 5 V to 2.5
2 5 V,
V Gain = –1
1
VCC = ±15 V
VCC = ±5 V
37
Settling time to 0.01%
0 01%
VI = –2.5
2 5 V to 2.5
2 5 V,
V Gain = –1
1
VCC = ±15 V
VCC = ±5 V
90
RL = 150 Ω
ts
UNIT
MAX
MHz
270
MHz
35
MHz
16
V/µs
260
ns
35
ns
70
† Full range = 0°C to 70°C for the C suffix and – 40°C to 85°C for the I suffix.
noise/distortion performance
THS4011C/I,
THS4012C/I
TEST CONDITIONS†
PARAMETER
MIN
THD
Total harmonic distortion
Vn
In
Input voltage noise
Input current noise
Differential gain error
Differential phase error
TYP
UNIT
MAX
VCC = ±15 V,
VO(PP) = 2 V
fc = 1 MHz,
– 80
dBc
VCC = ±5 V or ±15 V,
VCC = ±5 V or ±15 V,
f = 10 kHz
7.5
nV/√Hz
f = 10 kHz
1
pA/√Hz
Gain = 2,
RL = 150 Ω
Ω,
NTSC
VCC = ±15 V
0.01%
VCC = ±5 V
0.01%
Gain = 2,
RL = 150 Ω
Ω,
NTSC
VCC = ±15 V
0.01°
VCC = ±5 V
0.001°
† Full range = 0°C to 70°C for the C suffix and – 40°C to 85°C for the I suffix.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) (continued)
dc performance
Open loop gain
VIO
Input offset voltage
THS4011C/I,
THS4012C/I
TEST CONDITIONS†
PARAMETER
MIN
TYP
10
25
VCC = ±15 V,
VO = ±10 V,
V
RL = 1 kΩ
TA = 25°C
TA = full range
8
VCC = ±5 V,
VO = ±2
±2.5
5V
V,
RL = 250 Ω
TA = 25°C
7
TA = full range
5
UNIT
MAX
V/mV
12
V/mV
VCC = ±5 V or ±15 V
TA = 25°C
TA = full range
1
2
25
6
8
Input offset voltage drift
15
IIB
Input bias current
VCC = ±5 V or ±15 V
TA = 25°C
TA = full range
IIO
Input offset current
VCC = ±5 V or ±15 V
TA = 25°C
TA = full range
6
8
250
400
Offset current drift
VCC = ±5 V or ±15 V
† Full range = 0°C to 70°C for the C suffix and – 40°C to 85°C for the I suffix.
0.3
mV
µV/°C
µA
nA
nA/°C
input characteristics
VICR
CMRR
RI
Common mode input voltage range
Common-mode
Common mode rejection ratio
Common-mode
THS4011C/I,
THS4012C/I
TEST CONDITIONS†
PARAMETER
VCC = ±15 V
VCC = ±5 V
MIN
TYP
±13
±14.1
±3.8
±4.3
110
VCC = ±15 V,,
VIC = ±12 V
TA = 25°C
TA = full range
82
VCC = ±5 V,,
VIC = ±2.5 V
TA = 25°C
TA = full range
90
UNIT
MAX
V
dB
77
dB
95
dB
83
Input resistance
CI
Input capacitance
† Full range = 0°C to 70°C for the C suffix and – 40°C to 85°C for the I suffix.
2
MΩ
1.2
pF
output characteristics
TEST CONDITIONS†
PARAMETER
VO
IO
Output voltage swing
Output current
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
RL = 20 Ω
Ω,
POST OFFICE BOX 655303
MIN
TYP
±13
±13.5
±3.4
±3.7
±12
±13
RL = 150 Ω
±3
±3.4
VCC = ±15 V
VCC = ±5 V
70
110
50
75
RL = 1 kΩ
RL = 250 Ω
IOS
Short-circuit output current
VCC = ±15 V
RO
Output resistance
Open loop
† Full range = 0°C to 70°C for the C suffix and – 40°C to 85°C for the I suffix.
6
THS4011C/I,
THS4012C/I
• DALLAS, TEXAS 75265
UNIT
MAX
V
mA
150
mA
12
Ω
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) (continued)
power supply
TEST CONDITIONS†
PARAMETER
THS4011C/I,
THS4012C/I
MIN
VCC
ICC
PSRR
Supply voltage
Dual supply
Single supply
UNIT
MAX
±4.5
±16.5
9
33
VCC = ±15 V
TA = 25°C
TA = full range
7.8
9.5
VCC = ±5 V
TA = 25°C
TA = full range
6.9
8.5
VCC = ±5 V to ±15 V
TA = 25°C
TA = full range
Supply current (each amplifier)
Power supply rejection ratio
TYP
11
V
mA
10
75
68
83
dB
† Full range = 0°C to 70°C for the C suffix and – 40°C to 85°C for the I suffix.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics, VCC = ±15 V, RL = 150 Ω, TA = 25°C, (unless otherwise noted)
dynamic performance
BW
Unity-gain bandwidth
Closed loop,
Bandwidth for 0.1 dB flatness
Gain = 1
RL = 1 kΩ
VCC = ±15 V
VCC = ±15 V
MIN
TYP
*160
200
35
UNIT
MHz
VO(PP) = 20 V
VO(PP) = 20 V
2.5
MHz
30
Slew rate
Settling time to 0.1%
0 1%
VI = –2.5
2 5 V to 2.5
2 5 V,
V Gain = –1
1
VCC = ±15 V
VCC = ±5 V
37
Settling time to 0.01%
0 01%
VI = –2.5
2 5 V to 2.5
2 5 V,
V Gain = –1
1
VCC = ±15 V
VCC = ±5 V
90
ts
MAX
70
VCC = ±5 V
VCC = ±2.5 V
VCC = ±15 V, RL = 150 Ω,
VCC = ±5 V, RL = 150 Ω,
VCC = ±15 V, RL = 1 kΩ
Full power bandwidth (see Note 1)
SR
THS4011M
TEST CONDITIONS†
PARAMETER
MHz
8
*300
400
V/µs
ns
35
ns
70
† Full range = –55°C to 125°C for the M suffix.
*This parameter is not tested.
NOTE 1: Full pwer bandwidth = slew rate/2π V(PP).
noise/distortion performance
THD
Total harmonic distortion
Vn
In
Input voltage noise
Input current noise
Differential gain error
Differential phase error
THS4011M
TEST CONDITIONS†
PARAMETER
MIN
MAX
UNIT
VCC = ±15 V,
VO(PP) = 1 V
fc = 1 MHz,
– 80
dBc
VCC = ±5 V or ±15 V,
VCC = ±5 V or ±15 V,
f = 10 kHz
7.5
nV/√Hz
f = 10 kHz
1
pA/√Hz
Gain = 2,
RL = 150 Ω
Ω,
NTSC
VCC = ±15 V
0.006
VCC = ±5 V
0.001
Gain = 2,
RL = 150 Ω
Ω,
NTSC
VCC = ±15 V
0.01°
VCC = ±5 V
0.002°
† Full range = –55°C to 125°C for the M suffix.
8
TYP
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
%
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
(continued)
dc performance
Open loop gain
VIO
VCC = ±15 V,
RL = 1 kΩ
VO = ±10 V,
VCC = ±5 V,
RL = 1 kΩ
VO = ±2.5 V,
Input offset voltage
VCC = ±5 V or ±15 V
Input offset voltage drift
VCC = ±5 V or ±15 V
IIB
Input bias current
VCC = ±5 V or ±15 V
IIO
Input offset current
VCC = ±5 V or ±15 V
VCC = ±5 V or ±15 V
Offset current drift
THS4011M
TEST CONDITIONS†
PARAMETER
TYP
TA = full range
6
14
V/mV
TA = full range
5
10
V/mV
TA = 25°C
TA = full range
MAX
UNIT
MIN
2
6
2
8
µV/°C
15
TA = 25°C
TA = full range
TA = 25°C
mV
2
6
4
8
25
250
0.3
µA
nA
nA/°C
† Full range = –55°C to 125°C for the M suffix.
input characteristics
TEST CONDITIONS†
PARAMETER
VICR
Common mode input voltage range
Common-mode
VCC = ±15 V
VCC = ±5 V
CMRR
Common mode rejection ratio
Common-mode
VCC = ±15 V,
VCC = ±5 V,
RI
Input resistance
VIC = ±12 V
VIC = ±2.5 V
THS4011M
MIN
TYP
±13
±14.1
±3.8
±4.3
75
90
84
95
CI
Input capacitance
† Full range = –55°C to 125°C for the M suffix.
MAX
UNIT
V
dB
2
MΩ
1.2
pF
output characteristics
PARAMETER
VO
Output voltage swing
IO
Output current
IOS
RO
Short-circuit output current
Output resistance
TEST CONDITIONS†
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
Open loop
THS4011M
MIN
TYP
±13
±13.5
±3.4
±3.7
RL = 250 Ω
±12
±13
RL = 150 Ω
±3
±3.4
70
115
50
75
RL = 1 kΩ
RL = 20 Ω
TA = 25°C
MAX
UNIT
V
mA
150
mA
12
Ω
† Full range = –55°C to 125°C for the M suffix.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
(continued)
power supply
VCC
ICC
PSRR
THS4011M
TEST CONDITIONS†
PARAMETER
MIN
Dual supply
Supply voltage
Single supply
±4.5
±16.5
9
33
TA = 25°C
TA = full range
7.8
9.5
VCC = ±5 V
TA = 25°C
TA = full range
6.9
8.5
VCC = ±5 V to ±15 V
TA = 25°C
TA = full range
11
80
86
78
83
PARAMETER MEASUREMENT INFORMATION
1.5 kΩ
1.5 kΩ
_
VI1
+
CH1
50 Ω
1.5 kΩ
_
VO1
150 Ω
VO2
150 Ω
+
CH2
50 Ω
Figure 3. THS4012 Crosstalk Test Circuit
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
mA
10
† Full range = –55°C to 125°C for the M suffix.
1.5 kΩ
MAX
VCC = ±15 V
Quiescent current
Power supply rejection ratio
TYP
VI2
dB
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
TYPICAL CHARACTERISTICS
VCC = ±15 V
1
0.8
0.6
0.4
|VO | – Output Voltage Swing – V
1.2
2.5
2
1.5
1
0.5
0.2
–20
0
20
40
60
80
–20
0
Figure 4
V IC – Input Common-Mode Range – V
40
60
80
5
100
VCC = ± 15 V
RL = 1 kΩ
13
VCC = ± 15 V
RL = 250 Ω
VCC = ± 5 V
RL = 1 kΩ
3.5
VCC = ± 5 V
RL = 150 Ω
3
2.5
–40
0
20
40
60
80
13
11
9
7
5
100
5
7
9
100
11
13
80
60
50
40
30
20
10
0
1k
15
10k
VCC ± 5V
VCC ± 15V
Crosstalk – dB
40
VCC ± 15V
80
–20
–30
–40
–50
100M
10M
OPEN-LOOP GAIN RESPONSE
100
100
60
1M
Figure 9
–10
VCC ± 15V
100k
f – Frequency – Hz
CROSSTALK
vs
FREQUENCY
0
15
70
Figure 8
CMRR
vs
FREQUENCY
13
VCC = ±15 V or ±5 V
90
± VCC – Supply Voltage – V
Figure 7
11
PSRR
vs
FREQUENCY
TA = 25° C
TA – Free-Air Temperature – _C
80
9
Figure 6
3
–20
7
± VCC – Supply Voltage – V
Open0Loop Gain – dB
Maximum Output Voltage Swing –± V
20
15
4
4
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
14
13.5
4.5
6
Figure 5
MAXIMUM OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
12
RL = 150 Ω
8
TA – Free-Air Temperature – _C
TA – Free-AIR Temperature – _C
12.5
RL = 1 kΩ
10
2
0
–40
100
12
PSRR – Power-Supply Rejection Ratio – dB
0
–40
CMRR – Common-Mode Rejection Ratio – dB
TA = 25° C
VCC = ±15 V or ±5 V
Iib – Input Bias Current – uA
V IO – Input Offset Voltage – mV
14
3
1.4
120
OUPUT VOLTAGE
vs
SUPPLY VOLTAGE
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
VI = CH2
VO = CH1
–60
VI = CH1
VO = CH2
–70
60
VCC ± 5V
40
20
0
20
–80
0
1k
10k
100k
1M
10M
f – Frequency – Hz
Figure 10
100M
–90
100k
1M
10M
100M
1G
f – Frequency – Hz
Figure 11
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1k
10K
100K
1M
10M
100M
1G
f – Frequency – Hz
Figure 12
11
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
TYPICAL CHARACTERISTICS
DISTORTION
vs
FREQUENCY
DISTORTION
vs
FREQUENCY
–40
–40
–50
–60
–70
–80
–40
VCC = ± 5 V
RL = 1 kΩ
G=2
VCC = ± 15 V
RL = 150 Ω
G=2
–50
Distortion – dB
VCC = ± 15 V
RL = 1 kΩ
G=2
Distortion – dB
Distortion – dB
–50
DISTORTION
vs
FREQUENCY
–60
–70
2nd Harmonic
–80
–60
2nd Harmonic
–70
–80
2nd Harmonic
–90
–90
–100
–90
3rd Harmonic
–100
3rd Harmonic
–100
3rd Harmonic
–110
100k
1M
–110
100k
10M
10M
f – Frequency – Hz
Figure 13
Figure 14
Figure 15
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
5
2nd Harmonic
–70
–80
–90
3rd Harmonic
–100
1M
Rf = 100 Ω
–5
–10
–15
0
–20
–25
100k
10M
Rf = 270 Ω
0
Output Amplitude – dB
Output Amplitude – dB
–60
–110
100k
5
Rf = 270 Ω
VCC = ± 5 V
RL = 150 Ω
G=2
1M
0
Rf = 100 Ω
–5
–10
–15
VCC = ± 15 V
RL = 150 Ω
G=1
10M
100M
VCC = ± 5 V
RL = 150 Ω
G=1
–20
100k
1G
1M
10M
100M
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 16
Figure 17
Figure 18
NOISE SPECTRAL DENSITY
vs
FREQUENCY
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.35°
100
Gain = 2
VCC = ± 15 V
RF = 1 kΩ
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
Differential Phase
0.3°
Noise Spectral Density
1M
f – Frequency – Hz
–40
Distortion – dB
–110
100k
10M
f – Frequency – Hz
DISTORTION
vs
FREQUENCY
–50
1M
10
0.25°
0.2°
0.15°
VCC = ± 5 V
0.1°
0.05°
VCC = ±15 V or ±5 V
1
10
0°
100
1k
10k
100k
1
f – Frequency – Hz
Figure 19
12
2
3
Number of 150-Ω Loads
Figure 20
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1G
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
TYPICAL CHARACTERISTICS
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.25°
VCC = ± 15 V
0.2°
0.15°
Gain = 2
RF = 1 kΩ
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
0.04
Differential Gain – %
Differential Phase
0.3°
0.06
0.05
Gain = 2
RF = 1 kΩ
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
0.35°
VCC = ± 5 V
0.1°
Gain = 2
RF = 1 kΩ
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
0.05
Differential Gain – %
0.4°
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.03
0.02
VCC = ± 15 V
0.04
0.03
VCC = ± 15 V
0.02
VCC = ± 5 V
0.01
0.01
0.05°
VCC = ± 5 V
0°
0
1
2
3
Number of 150-Ω Loads
Figure 21
4
0
1
2
3
4
Number of 150-Ω Loads
Figure 22
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1
2
3
4
Number of 150-Ω Loads
Figure 23
13
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
theory of operation
The THS401x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built
using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing
fTs of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high
slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 24.
(7) VCC +
(6) OUT
IN – (2)
IN + (3)
(4) VCC –
NULL (1)
NULL (8)
Figure 24. THS4011 Simplified Schematic
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true when amplifying small signals. The noise
model for the THS401x is shown in Figure 25. This model includes all of the noise sources as follows:
•
•
•
•
14
en = Amplifier internal voltage noise (nV/√Hz)
IN+ = Noninverting current noise (pA/√Hz)
IN– = Inverting current noise (pA/√Hz)
eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx )
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noise calculations and noise figure (continued)
eRs
RS
en
Noiseless
+
_
eni
IN+
eno
eRf
RF
eRg
IN–
RG
Ǹǒ Ǔ
Figure 25. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
e
+
ni
Where:
en
2
ǒ
) IN )
Ǔ )ǒ ǒ
2
R
S
IN–
R
ǓǓ
ǒ
Ǔ
ø RG ) 4 kTRs ) 4 kT RF ø RG
F
2
k = Boltzmann’s constant = 1.380658 × 10–23
T = Temperature in degrees Kelvin (273 +°C)
RF || RG = Parallel resistance of RF and RG
ǒ Ǔ
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
e no
+ eni AV + e
ni
1
) RR
F
(noninverting case)
G
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, please refer to the Noise Analysis section in Operational Amplifier
Circuits Applications Report (literature number SLVA043).
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SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
noise calculations and noise figure (continued)
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
NF
+ 10log
ȱȧ
Ȳǒ
ȳȧ
Ǔȴ
e 2
ni
2
e
Rs
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
ȱȧ ȡȧǒ
ȧȧ )Ȣ
ȧȲ
NF
+ 10log
Ǔ )ǒ )
2
e
n
1
IN
4 kTR
Ǔ ȣȧȤȳȧ
2
R
S
S
ȧȧ
ȧȴ
Figure 26 shows the noise figure graph for the THS401x.
NOISE FIGURE
vs
SOURCE RESISTANCE
30
f = 10 kHz
TA = 25°C
Noise Figure – dB
25
20
15
10
5
0
10
10 k
1k
100
Source Resistance – Ω
100 k
Figure 26. Noise Figure vs Source Resistance
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APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS401x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 27. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
1.3 kΩ
1.3 kΩ
Input
_
20 Ω
Output
THS401x
+
CLOAD
Figure 27. Driving a Capacitive Load
offset nulling
The THS401x has very low input offset voltage for a high-speed amplifier. However, if additional correction is
required, an offset nulling function has been provided on the THS4011. The input offset can be adjusted by
placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply. This
is shown in Figure 28.
VCC+
0.1 µF
+
THS4011
_
10 kΩ
0.1 µF
VCC –
Figure 28. Offset Nulling Schematic
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APPLICATION INFORMATION
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
RF
IIB–
RG
+
–
VI
VO
+
RS
ǒ ǒ ǓǓ ǒ ǒ ǓǓ
IIB+
V
OO
+ VIO 1 )
R
R
F
G
" IIB) RS
1
)
R
R
F
G
" IIB– RF
Figure 29. Output Offset Voltage Model
optimizing unity gain response
Internal frequency compensation of the THS401x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 100 Ω should
be used as shown in Figure 30. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
Input
+
Output
THS401x
_
100 Ω
Figure 30. Noninverting, Unity Gain Schematic
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APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifer
(see Figure 31).
RG
RF
–
VO
+
VI
R1
V
O
V
I
C1
ǒ Ǔǒ
+ 1 ) RRF
G
1
f
–3dB
Ǔ
1
+ 2pR1C1
) sR1C1
1
Figure 31. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
–3dB
RG =
+ 2p1RC
(
RF
1
2–
Q
)
Figure 32. 2-Pole Low-Pass Sallen-Key Filter
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APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high frequency performance of the THS401x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS401x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
D
D
D
D
D
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
Surface-mount passive components – Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
general PowerPAD design considerations
The THS401x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 33(a) and Figure 33(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 33(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away
from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
20
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 33. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 34. PowerPAD PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 34. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS401xDGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS401xDGN package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS401xDGN IC is simply placed in position and run through
the solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The actual thermal performance achieved with the THS401xDGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θJA, is about 58.4_C/W. For comparison, the non-PowerPAD version of
the THS401x IC (SOIC) is shown. For a given θJA, the maximum power dissipation is shown in Figure 35 and
is calculated by the following formula:
P
+
D
Where:
ǒ Ǔ
T
–T
MAX A
q JA
PD = Maximum power dissipation of THS401x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
Maximum Power Dissipation – W
3.5
DGN Package
θJA = 58.4°C/W
2 oz. Trace And Copper Pad
With Solder
3
2.5
SOIC Package
High-K Test PCB
θJA = 98°C/W
2
TJ = 150°C
DGN Package
θJA = 158°C/W
2 oz. Trace And
Copper Pad
Without Solder
1.5
1
0.5
SOIC Package
Low-K Test PCB
θJA = 167°C/W
0
–40
–20
60
80
0
20
40
TA – Free-Air Temperature – °C
100
NOTE A: Results are with no air flow and PCB size = 3”× 3”
Figure 35. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be
found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be
ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
22
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially muti-amplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents. Figure 36 to Figure 39 show this effect,
along with the quiescent heat, with an ambient air temperature of 50°C. When using VCC = ±5 V, there is
generally not a heat problem, even with SOIC packages. But, when using VCC = ±15 V, the SOIC package is
severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how
the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But,
the device should always be soldered to a copper plane to fully use the heat dissipation properties of the
PowerPAD. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As
more trace and copper area is placed around the device, θJA decreases and the heat dissipation capability
increases. The currents and voltages shown in these graphs are for the total package. For the dual amplifier
package (THS4012), the sum of the RMS output currents and voltages should be used to choose the proper
package.
THS4011
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
VCC = ± 5 V
Tj = 150°C
TA = 50°C
180
1000
Maximum Output
Current Limit Line
| IO | – Maximum RMS Output Current – mA
| IO | – Maximum RMS Output Current – mA
200
160
140
Package With
θJA < = 120°C/W
120
100
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
80
60
40
Safe Operating
Area
20
THS4011
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
TJ = 150°C
TA = 50°C
VCC = ± 15 V
DGN Package
θJA = 58.4°C/W
Maximum Output
Current Limit Line
100
SO-8 Package
θJA = 98°C/W
High-K Test PCB
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
10
0
0
4
1
2
3
| VO | – RMS Output Voltage – V
5
0
Safe Operating
Area
3
6
9
12
| VO | – RMS Output Voltage – V
15
Figure 37
Figure 36
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THS4011, THS4012
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
THS4012
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
1000
Maximum Output
Current Limit Line
Package With
θJA ≤ 60°C/W
| IO | – Maximum RMS Output Current – mA
| IO | – Maximum RMS Output Current – mA
200
160
140
120
100
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
80
60
Safe Operating Area
40
SO-8 Package
θJA = 98°C/W
High-K Test PCB
20
0
0
VCC = ± 5 V
TJ = 150°C
TA = 50°C
Both Channels
4
1
2
3
| VO | – RMS Output Voltage – V
THS4012
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
VCC = ± 15 V
TJ = 150°C
TA = 50°C
Both Channels
100
SO-8 Package
θJA = 98°C/W
High-K Test PCB
10
DGN Package
θJA = 58.4°C/W
Safe Operating Area
5
1
0
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
3
6
9
12
| VO | – RMS Output Voltage – V
Figure 39
Figure 38
24
Maximum Output
Current Limit Line
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15
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
APPLICATION INFORMATION
evaluation board
An evaluation board is available for the THS4011 (literature number SLOP128) and THS4012 (literature number
SLOP230). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the THS4011 evaluation board is shown in Figure 40. The circuitry
has been designed so that the amplifier may be used in either an inverting or noninverting configuration. For
more information, please refer to the THS4011 EVM User’s Guide (literature number SLOU028) or the THS4012
EVM User’s Guide (literature number SLOU041) To order the evaluation board contact your local TI sales office
or distributor.
VCC+
+
C2
0.1 µF
R1
1 kΩ
IN +
C1
6.8 µF
NULL
R2
49.9 Ω
+
R3
49.9 Ω
OUT
THS4011
_
NULL
R5
1 kΩ
+
C4
0.1 µF
C3
6.8 µF
IN –
VCC –
R4
49.9 Ω
Figure 40. THS4011 Evaluation Board
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• DALLAS, TEXAS 75265
25
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
1
Gage Plane
7
A
0.010 (0,25)
0°– 8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
4040047 / D 10/96
NOTES: A.
B.
C.
D.
26
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
MECHANICAL INFORMATION
DGN (S-PDSO-G8)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
8
0,25 M
5
Thermal Pad
(See Note D)
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
1
0°– 6°
4
3,05
2,95
0,69
0,41
Seating Plane
1,07 MAX
0,15
0,05
0,10
4073271/A 04/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions include mold flash or protrusions.
The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments Incorporated.
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27
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
25
5
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
28
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
THS4011, THS4012
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
SLOS216B – JUNE 1999 – FEBRUARY 2000
MECHANICAL INFORMATION
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE PACKAGE
0.400 (10,20)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.063 (1,60)
0.015 (0,38)
0.100 (2,54)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
Falls within MIL-STD-1835 GDIP1-T8
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