TI TLV4112ID

TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
D
D
D
D
D
D
D
D
TLV4112
D, DGN, OR P PACKAGE
(TOP VIEW)
High Output Drive . . . >300 mA
Rail-To-Rail Output
Unity-Gain Bandwidth . . . 2 MHz
Slew Rate . . . 1.5 V/µs
Supply Current . . . 700-µA/Per Channel
Supply Voltage Range . . . 2.5 V to 6 V
Specified Temperature Range:
– TA = 0°C to 70°C . . . Commercial Grade
– TA = –40°C to 125°C . . . Industrial Grade
Universal OpAmp EVM
1OUT
1IN –
1IN +
GND
1
8
2
7
3
6
4
5
VDD
2OUT
2IN –
2IN+
description
The TLV411x single supply operational amplifiers provide output currents in excess of 300 mA at 5 V. This
enables standard pin-out amplifiers to be used as high current buffers or in coil driver applications. The TLV4110
and TLV4113 comes with a shutdown feature.
The TLV411x is available in the ultra small MSOP PowerPAD package, which offers the exceptional thermal
impedance required for amplifiers delivering high current levels.
All TLV411x devices are offered in PDIP, SOIC (single and dual) and MSOP PowerPAD (dual).
FAMILY PACKAGE TABLE
PACKAGE TYPES
NUMBER OF
CHANNELS
MSOP
PDIP
SOIC
TLV4110†
TLV4111†
1
8
8
8
Yes
1
8
8
8
—
TLV4112
TLV4113†
2
8
8
8
—
2
10
14
14
Yes
DEVICE
SHUTDOWN
UNIVERSAL
EVM BOARD
Refer to the EVM
Selection Guide
(Lit# SLOU060)
† This device is in the Product Preview stage of development. Contact the local TI sales office for more
information.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1.0
2.9
VOL – Low-Level Output Voltage – V
V OH – High-Level Output Voltage – V
3.0
VDD = 3 V
2.8
2.7
TA = 125°C
TA = –40°C
2.6
2.5
TA = 0°C
2.4
TA = 25°C
2.3
TA = 70°C
2.2
2.1
2.0
0
50
100
150
200
250
300
IOH – High-Level Output Current – mA
VDD = 3 V
0.9
0.8
TA = 70°C
0.7
TA = 25°C
TA = 0°C
TA = –40°C
TA = 125°C
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
50
100
150
200
250
300
IOL – Low-Level Output Current – mA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
TLV4110 AND TLV4111 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(D)†‡
SMALL OUTLINE
(DGN)†
SYMBOL
PLASTIC DIP
(P)
TLV4110CD
TLV4110CDGN
xxTIAHL
TLV4110CP
TLV4111CD
TLV4111CDGN
xxTIAHN
TLV4111CP
TLV4110ID
TLV4110IDGN
xxTIAHM
TLV4110IP
0°C to 70°C
– 40°C to 125°C
TLV4111ID
TLV4111IDGN
xxTIAHO
TLV4111IP
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part
number (e.g., TLV4110CDR).
‡ In the SOIC package, the maximum RMS output power is thermally limited to 350 mW; 700 mW peaks can be driven, as
long as the RMS value is less than 350 mW.
TLV4112 AND TLV4113 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(DGN)†
SYMBOL
TLV4112CD
TLV4113CD‡
TLV4112DGN
xxTIAHP
—
—
—
TLV4113CDGN‡
xxTIAHR
TLV4112ID
TLV4112IDGN
xxTIAHQ
—
—
—
TLV4113IDGN‡
xxTIAHS
SMALL OUTLINE
(D)†§
0°C to 70°C
– 40°C to 125°C
TLV4113ID‡
—
SMALL OUTLINE
(DGQ)†
PLASTIC DIP
(P)
SYMBOL
—
TLV4112CP
TLV4113CN‡
TLV4112IP
TLV4113IN‡
† This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV4112CDR).
‡ This device is in the Product Preview stage of development. Contact the local TI sales office for more information.
§ In the SOIC package, the maximum RMS output power is thermally limited to 350 mW; 700 mW peaks can be driven, as long as the
RMS value is less than 350 mW.
TLV411x PACKAGE PINOUTS
TLV4110
D, DGN OR P PACKAGE
(TOP VIEW)
NC
IN –
IN +
GND
1
8
2
7
3
6
4
5
TLV4111
D, DGN OR P PACKAGE
(TOP VIEW)
SHDN
NC
VDD
OUT
NC
IN –
IN +
GND
1
8
2
7
3
6
4
5
NC
VDD
OUT
NC
1
2
3
4
5
10
9
8
7
6
1OUT
1IN –
1IN +
GND
8
2
7
3
6
4
5
(TOP VIEW)
VDD+
2OUT
2IN –
2IN+
2SHDN
1OUT
1IN –
1IN+
GND
NC
1SHDN
NC
NC – No internal connection
2
1
TLV4113
D OR N PACKAGE
TLV4113
DGQ PACKAGE
(TOP VIEW)
1OUT
1IN –
1IN+
GND
1SHDN
TLV4112
D, DGN, OR P PACKAGE
(TOP VIEW)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VDD
2OUT
2IN –
2IN+
NC
2SHDN
NC
VDD
2OUT
2IN –
2IN+
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Differential input voltage, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VDD
Output current,IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mA
Continuous /RMS output current, IO (each output of amplifier): TJ ≤ 105°C . . . . . . . . . . . . . . . . . . . . 350 mA
TJ ≤ 150°C . . . . . . . . . . . . . . . . . . . . 110 mA
Peak output current, IO (each output of amplifier: TJ ≤ 105°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
TJ ≤ 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to GND.
2. To prevent permanent damage the die temperature must not exceed the maximum junction temperature.
DISSIPATION RATING TABLE
PACKAGE
θJC
(°C/W)
θJA
(°C/W)
TA ≤ 25°C
POWER RATING
D (8)
38.3
176
710 mW
D (14)
26.9
122.3
1022 mW
DGN (8)‡
DGQ (10)‡
4.7
52.7
2.37 W
4.7
52.3
2.39 W
P (8)
41
104
1200 mW
N (14)
32
78
1600 mW
‡ See The Texas Instruments document, PowerPAD Thermally Enhanced Package Application
Report (literature number SLMA002), for more information on the PowerPAD package. The
thermal data was measured on a PCB layout based on the information in the section entitled
Texas Instruments Recommended Board for PowerPAD on page 33 of the before mentioned
document.
recommended operating conditions
Supply voltage, VDD
Common-mode input voltage range, VICR
C-suffix
Operating free-air
free air temperature,
temperature TA
I-suffix
V(on)
VDD = 3 V
VDD = 5 V
V(off)
VDD = 3 V
VDD = 5 V
Shutdown turn on/off voltage level§
MIN
MAX
2.5
6
UNIT
V
0
VDD–1.5
70
V
0
–40
125
°C
2.1
3.8
0.9
V
1.65
§ Relative to GND
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
electrical characteristics at recommend operating conditions, VDD = 3 V and 5 V (unless otherwise
noted)
dc performance
PARAMETER
VIO
Input offset voltage
αVIO
Offset voltage draft
CMRR
Common mode rejection ratio
Common-mode
TEST CONDITIONS
VIC = VDD/2,
/2
RL = 100 Ω
Ω,
VO = VDD/2 ,
RS = 50 Ω
VDD = 3 V,
RS = 50 Ω
VDD = 5 V,
RS = 50 Ω
VDD = 3 V,,
VO(PP)=0 to 1V
AVD
Large-signal
g
g
differential voltage
g
amplification
VDD = 5 V,,
VO(PP)=0 to 3V
TA†
25°C
MIN
TYP
MAX
175
3500
Full range
4000
25°C
3
VIC = 0 to 2 V,
25°C
63
VIC = 0 to 4 V,
25°C
68
RL=100 Ω
RL=10 kΩ
RL=100 Ω
RL=10 kΩ
UNITS
µV
µV/°C
dB
25°C
78
Full range
67
25°C
85
Full range
75
25°C
88
Full range
75
25°C
90
Full range
85
84
100
dB
94
110
† Full range is 0°C to 70°C for C suffix and – 40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
input characteristics
PARAMETER
VICR
Common mode input voltage range
Common-mode
TA†
MIN
VDD = 3 V
25°C and
Full range
0
to
1.5
VDD = 5 V
25°C and
Full range
0
to
3.5
TEST CONDITIONS
Measured over
CMRR range,
range
RS = 50 Ω
25°C
IIO
Input offset current
VIC = VDD/2
TLV411xC
TLV411xI
ri(d)
Input bias current
/2
VO = VDD/2,
RS = 50 Ω
TLV411xC
TLV411xI
Differential input resistance
4
25°C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.3
UNITS
25
50
250
0.3
50
pA
100
Full range
CIC
Common-mode input capacitance
f = 100 Hz
25°C
† Full range is 0°C to 70°C for C suffix and – 40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
MAX
V
Full range
25°C
IIB
TYP
500
1000
GΩ
5
pF
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
electrical characteristics at specified free-air temperature, VDD = 3 V and 5 V (unless otherwise
noted) (continued)
output characteristics
PARAMETER
TEST CONDITIONS
IOH = –10
10 mA
VDD = 3 V
V, VIC = VDD/2
IOH =–100
= 100 mA
VOH
10 mA
IOH = –10
High-level output voltage
VDD = 5 V, VIC = VDD/2
IOH = –100
100 mA
IOH = –200 mA
IOL = 10 mA
VDD = 3 V and 5 V,,
VIC = VDD/2
VOL
IOL = 100 mA
Low–level output voltage
TA†
25°C
MIN
TYP
2.7
2.97
Full range
2.7
25°C
2.6
Full range
2.6
25°C
4.7
Full range
4.7
25°C
4.6
Full range
4.6
25°C
4.45
–40°C to
85°C
4.35
25°C
IO
Output current‡
IOS
Short circuit output current‡
Short-circuit
IOL = 200 mA
Measured at 0.5
0 5 V from rail
VDD = 3 V
VDD = 5 V
Sourcing
4.96
4.76
V
4.6
0.03
0.1
0.1
25°C
0.33
Full range
0.4
0.55
0.38
–40°C to
85°C
V
0.6
0.7
±220
25°C
mA
±320
800
25°C
Sinking
UNITS
V
2.73
Full range
25°C
VDD = 5 V, VIC = VDD/2
MAX
mA
800
† Full range is 0°C to 70°C for C suffix and – 40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
‡ When driving output currents in excess of 200 mA, the MSOP PowerPAD package is required for thermal dissipation.
power supply
PARAMETER
IDD
KSVR
TEST CONDITIONS
Supply current (per channel)
VO = VDD/2
Power supply rejection ratio (∆VDD / ∆VIO)
TA
25°C
MIN
TYP
MAX
700
1000
Full range
VDD =2.7 to 3.3 V,,
VIC = VDD/2 V
No load,,
VDD =4.5 to 5.5 V,
VIC = VDD/2 V
No load,
1500
25°C
70
Full range
65
25°C
70
UNITS
µA
82
79
dB
Full range
65
† Full range is 0°C to 70°C for C suffix and – 40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
electrical characteristics at specified free-air temperature, VDD = 3 V and 5 V (unless otherwise
noted) (continued)
dynamic performance
PARAMETER
GBWP
SR
φM
Gain bandwidth product
Slew rate at unity gain
Phase margin
RL=100 Ω
CL=10 pF
Vo(pp) = 2 V,
RL = 100 Ω,
Ω
CL = 10 pF
F
RL = 100 Ω,
Ω
Gain margin
ts
TEST CONDITIONS
VDD = 5 V
CL = 10 pF
V(STEP)pp = 1 V,
AV = –1,
CL = 10 pF,
RL = 100 Ω
Settling time
VDD = 3 V
TA†
25°C
MIN
TYP
25°C
0.8
1.57
Full range
0.55
25°C
Full range
MAX
2.7
1
UNITS
MHz
V/µs
1.57
0.7
66
25°C
16
0.1%
dB
0.7
µs
25°C
0.01%
1.3
† Full range is 0°C to 70°C for C suffix and – 40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
noise/distortion performance
PARAMETER
THD+N
Total harmonic distortion plus noise
Vn
Equivalent input noise voltage
In
Equivalent input noise current
TEST CONDITIONS
VO(pp) = VDD/2 V,
RL = 100 Ω,
f = 100 Hz
TA
MIN
AV = 1
AV = 10
AV = 100
f = 100 Hz
TYP
MAX
UNITS
0.025
0.035
0.15
25°C
55
f = 10 kHz
nV/√Hz
10
f = 1 kHz
0.31
fA/√Hz
shutdown characteristics
PARAMETER
IDD(SHDN)
TEST CONDITIONS
Supply
y current in shutdown mode (per
(
channel))
(TLV4110, TLV4113)
SHDN = 0 V
TA†
25°C
Full range
MIN
TYP
TBD
TBD
MAX
UNITS
µA
t(ON)
Amplifier turnon time‡
TBD
RL = 100 Ω
25°C
µs
‡
t(Off)
Amplifier turnoff time
TBD
† Full range is 0°C to 70°C for C suffix and – 40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
‡ Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current
has reached half its final value.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
CMRR
Input offset voltage
vs Common-mode input voltage
Common-mode rejection ratio
vs Frequency
VOH
VOL
High-level output voltage
vs High-level output current
4, 6
Low-level output voltage
vs Low-level output current
5, 7
Zo
IDD
Output impedance
vs Frequency
Supply current
vs Supply voltage
9
kSVR
Supply voltage rejection ratio
vs Frequency
10
AVD
Differential voltage amplification and phase
vs Frequency
11
Gain-bandwidth product
vs Supply voltage
12
vs Supply voltage
13
vs Temperature
14
Total harmonic distortion+noise
vs Frequency
15
Equivalent input voltage noise
vs Frequency
16
Phase margin
vs Capacitive load
Voltage-follower signal pulse response
vs Time
18, 19
Inverting large-signal pulse response
vs Time
20, 21
Small-signal inverting pulse response
vs Time
22
Crosstalk
vs Frequency
23
SR
Vn
Slew rate
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1, 2
3
8
17
7
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
6000
VDD = 3 V
TA = 25°C
4000
V IO – Input Offset Voltage – µ V
2000
0
–2000
–4000
VDD = 5 V
TA = 25°C
4000
2000
0
–2000
–4000
–6000
–0.2 0
–6000
–0.2 0 0.4 0.8 1.2 1.6 2
2.4 2.8 3.2
VICR – Common-Mode Input Voltage – V
0.4 1.0 1.6 2.2 2.8 3.4 4.0 4.6 5.2
Figure 1
VOL – Low-Level Output Voltage – V
2.7
TA = 125°C
TA = –40°C
TA = 0°C
TA = 25°C
2.3
TA = 70°C
2.2
2.1
2.0
0
50
100
150
200
250
0.8
TA = 70°C
0.7
TA = 25°C
0.6
TA = 0°C
TA = –40°C
0.5
0.4
0.3
0.2
0.1
0.0
300
TA = 125°C
0
50
Z o – Output Impedance – Ω
VOL – Low-Level Output Voltage – V
0.8
TA = 70°C
TA = 25°C
TA = 0°C
TA = –40°C
TA = 125°C
0.3
0.2
100
150
200
250
10 k
100 k
1M
10 M
VDD = 5 V
4.9
4.8
TA = 125°C
4.7
4.6
TA = –40°C
4.5
TA = 0°C
4.4
TA = 25°C
4.3
TA = 70°C
4.2
4.1
4.0
300
0
50
100
150
200
250
300
IOH – High-Level Output Current – mA
Figure 6
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
1200
VDD = 3 & 5 V
TA = 25°C
AV = 1
VIN = VDD/2 V
10
A = 100
1
A = 10
TA = 125°C
1000
TA = 70°C
800
TA = 25°C
600
TA = 0°C
TA = –40°C
400
200
0.1
A=1
0.0
0
50
100
150
200
250
IOL – Low-Level Output Current – mA
Figure 7
8
1k
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
100
VDD = 5 V
0.4
40
100
OUTPUT IMPEDANCE
vs
FREQUENCY
1.0
0.5
50
Figure 5
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.6
60
IOL – Low-Level Output Current – mA
Figure 4
0.7
70
5.0
VDD = 3 V
0.9
IOH – High-Level Output Current – mA
0.9
80
Figure 3
I DD – Supply Current – µ A
V OH – High-Level Output Voltage – V
2.8
2.4
90
f – Frequency – Hz
1.0
VDD = 3 V
2.5
100
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
3.0
2.6
VDD = 3 V
TA = 25°C
110
Figure 2
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.9
120
VICR – Common-Mode Input Voltage – V
V OH – High-Level Output Voltage – V
V IO – Input Offset Voltage – µ V
6000
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
CMRR – Common-Mode Rejection Ratio – dB
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
300
0.10
100
1k
10k
100k
1M
10M
f – Frequency – Hz
Figure 8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0
0
1
2
3
4
VDD – Supply Voltage – V
Figure 9
5
6
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
VDD = 3 & 5 V
RF = 1 kΩ
RI = 100 Ω
VIN = 0 V
TA = 25°C
80
70
60
50
40
30
20
10
1k
10 k
100 k
1M
10 M
100
PHASE
80
90
60
40
GAIN
–20
VDD = 3 & 5 V
RL = 100 kΩ
CL = 10 pF
TA = 25°C
–40
100
1k
f – Frequency – Hz
1M
1.75
SR – Slew Rate – V/ µ s
SR+
1.25
SR–
1.00
0.75
0.50
0.25
0.00
3.5
1.50
VDD = 3 & 5 V
AV = 1
RL = 100 Ω
CL = 10 pF
4
4.5
SR+
1.00
0.75
0.50
5
5.5
0.00
–40 –25 –10 5
6
3
3.5
4
4.5
5
5.5
10
VDD = 5 V
RL = 100 Ω
VO(PP) = VDD/2
AV = 1, 10, & 100
1
A = 100
0.1
A = 10
A=1
0.01
20 35 50 65 80 95 110 125
10
100
TA – Temperature – °C
1k
10 k
100 k
f – Frequency – Hz
Figure 14
Figure 15
PHASE MARGIN
vs
CAPACITIVE LOAD
100
160
VDD = 3 & 5 V
TA = 25°C
90
Hz
2.5
TOTAL HARMONIC DISTORTION+NOISE
vs
FREQUENCY
EQUIVALENT INPUT VOLTAGE NOISE
vs
FREQUENCY
VDD = 5 V
80
Phase Margin – °
120
VDD = 3 V
100
80
60
40
RL = 100
70
RL = 600
RNULL = 20
60
50
RNULL = 20
40
30
RNULL = 0
20
RNULL = 0
10
20
0
10
0.5
Figure 12
SR–
Figure 13
140
TA = 25°C
RL = 100 Ω
CL = 10 pF
f = 1 kHz
AV =open loop
1.0
VDD – Supply Voltage – V
1.25
VDD – Supply Voltage – V
V n – Voltage Noise – nV/
3
1.5
0.0
0.25
2.5
2.0
–45
10 M
2.00
AV = 1
RL = 100 Ω
CL = 10 pF
2.5
SLEW RATE
vs
TEMPERATURE
2.00
SR – Slew Rate – V/ µ s
100 k
3.0
Figure 11
SLEW RATE
vs
SUPPLY VOLTAGE
1.50
10 k
0
3.5
f – Frequency – Hz
Figure 10
1.75
45
20
0
4.0
135
THD+N –Total Harmonic Distortion + Noise
0
100
120
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
Phase Margin – °
Gain-Bandwidth Product – MHz
100
90
AMPLIFICATION AND PHASE
vs
FREQUENCY
A VD – Differential Voltage Amplification – dB
k SVR – Supply Voltage Rejection Ratio – V
SUPPLY VOLTAGE REJECTION RATIO
vs
FREQUENCY
0
100
1k
10 k
100 k
10
100
1k
10 k
100 k
Capacitive Load – pF
f – Frequency – Hz
Figure 16
Figure 17
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
4
VIN
2
1
VO
0
4
VDD = 5 V
AV = 1
RL = 100 Ω
CL = 10 pF
TA = 25°C
3
2
1
0
–2
0
2
4
6
8
10
12
14
VIN
2.55
VDD = 5 V
AV = 1
RL = 100 Ω
CL = 10 pF
TA = 25°C
VIN = 100 mV
2.5
2.45
2.55
VO
2.5
2.45
2.4
–0.2 0.0
0.2
3
2
0
–2
5
VIN
4
3
2
VO
1
0
–1
0
1
2
3
4
t – TIME – µs
Figure 21
10
5
6
7
8
V O – Output Voltage – V V I – Input Voltage – V
V O – Output Voltage – V V I – Input Voltage – V
INVERTING LARGE-SIGNAL
PULSE RESPONSE
–1
0.8
1.0
1.2
1.4
2
1
VDD = 5 V
AV = –1
RL = 100 Ω
CL = 50 pF
TA = 25°C
VIN = 2.5 V
0
–1
–2
5
VIN
4
3
2
VO
1
0
–1
0
1
2
3
4
5
6
7
8
t – TIME – µs
Figure 19
Figure 20
SMALL-SIGNAL INVERTING
PULSE RESPONSE
CROSSTALK
vs
FREQUENCY
Figure 18
VDD = 5 V
AV = –1
RL = 100 Ω
CL = 50 pF
TA = 25°C
VIN = 2.5 V
0.6
3
t – TIME – µs
t – TIME – µs
1
0.4
2.58
0
2.54
VIN
–20
2.5
VDD = 5 V
AV = –1
RL = 100 Ω
CL = 50 pF
TA = 25°C
VIN = 2.5 V
2.46
2.42
2.54
Crosstalk – dB
3
2.6
INVERTING LARGE-SIGNAL
PULSE RESPONSE
V O – Output Voltage – V V I – Input Voltage – V
5
VOLTAGE-FOLLOWER
SMALL-SIGNAL PULSE RESPONSE
V O – Output Voltage – V V I – Input Voltage – V
V O – Output Voltage – V V – Input Voltage – V
I
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
VDD = 3 & 5 V
RL = 100 Ω
All Channels
–40
–60
VIN = 4 VPP
–80
2.5
VO
2.46
–100
VIN = 2 VPP
2.42
0 0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
t – TIME – µs
Figure 22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
–120
10
100
1k
10 k
f – Frequency – Hz
Figure 23
100 k
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
APPLICATION INFORMATION
shutdown function
Two members of the TLV411x family (TLV4110/3) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to just nano amps
per channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. In order to save
power in shutdown mode, an external pullup resistor is required, thererfore, to enable the amplifier the shutdown
terminal must be pulled high. When the shutdown terminal is left floating, care should be taken to ensure that
parasitic leakage current at the shutdown terminal does not inadvertently place the operational amplifier into
shutdown.
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 1 nF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown
in Figure 24. A maximum value of 20 Ω should work well for most applications.
RF
RG
–
Input
RF
RG
RNULL
Output
+
RL
RNULL
–
Input
Output
+
Snubber
CLOAD
RL
CL
C
(a)
(b)
Figure 24. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
RF
IIB–
RG
+
–
VI
VO
+
RS
ǒ ǒ ǓǓ ǒ ǒ ǓǓ
IIB+
V
OO
+ VIO 1 )
R
R
F
G
" IIB) RS
1
)
R
R
F
G
" IIB– RF
Figure 25. Output Offset Voltage Model
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
APPLICATION INFORMATION
Rnull
_
+
RL
CL
Figure 26
general power design considerations
When driving heavy loads at high junction temperatures there is an increased probability of electromigration
affecting the long term reliability of ICs. Therefore for this not to be an issue either
D
D
the output current must be limited (at these high junction temperatures) or
the junction temperature must be limited.
The maximum continuous output current at a die temperature 150°C will be 1/3 of the current at 105°C.
The junction temperature will be dependent on the ambient temperature around the IC, thermal impedance from
the die to the ambient and power dissipated within the IC.
TJ = TA + θJA × PDIS
Where
PDIS is the IC power dissipation and is equal to the output current multiplied by the voltage dropped across the
output of the IC.
θJA is the thermal impedance between the junction and the ambient temperature of the IC.
TJ is the junction temperature.
TA is the ambient temperature.
Reducing one or more of these factors will result in a reduced die temperature. The 8-pin SOIC (small outline
integrated circuit) has a thermal impedance from junction to ambient of 176°C/W. For this reason we
recommend that the maximum power dissipation of the 8-pin SOIC package be limited to 350 mW, with peak
dissipation of 700 mW as long as the RMS value is less than 350 mW.
The use of the MSOP PowerPAD dramatically reduces the thermal impedance from junction to case. And with
correct mounting, the reduced thermal impedance will greatly increase the IC’s permissible power dissipation
and output current handling capability. For example, the power dissipation of the PowerPAD is increased to
above 1 W. Sinusoidal and pulse-width modulated output signals will also increase the output current capability.
The equivalent dc current is proportional to the square-root of the duty cycle:
I
DC(EQ)
+ ICont
Ǹ(duty cycle)
CURRENT DUTY CYCLE
AT PEAK RATED CURRENT
EQUIVALENT DC CURRENT
AS A PERCENTAGE OF PEAK
100
100
70
84
50
71
Note that with an operational amplifier, a duty cycle of 70% would often result in the op amp sourcing current
70% of the time and sinking current 30%, therefore, the equivalent dc current would still be 0.84 times the
continuous current rating at a particular junction temperature.
12
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
APPLICATION INFORMATION
general PowerPAD design considerations
The TLV411x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 27(a) and Figure 27(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 27(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 27. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
Thermal Pad Area
Single or Dual
68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils
Figure 28. PowerPAD PCB Etch and Via Pattern
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
1. Prepare the PCB with a top side etch pattern as shown in Figure 28. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils
in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLV411x IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the TLV411x PowerPAD package should make their connection to the internal ground plane
with a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the
reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the TLV411x IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
For a given θJA, the maximum power dissipation is shown in Figure 30 and is calculated by the following formula:
P
Where:
+
D
ǒ Ǔ
T
–T
MAX A
q JA
PD = Maximum power dissipation of TLV411x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
4
TJ = 150°C
Maximum Power Dissipation – W
3.5
3
2.5
2
DGN Package
Low-K Test PCB
θJA = 52.7°C/W
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
1.0
1
0.5
0
–55 –40 –25 –10 5 20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 29. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially muti-amplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around
the device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in
these graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output
currents and voltages should be used to choose the proper package.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts , the model generation software used
with Microsim PSpice . The Boyle macromodel (see Note 3) and subcircuit in Figure 30 are generated using
the TLV411x typical electrical and operating characteristics at TA = 25°C. Using this information, output
simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D Maximum positive output voltage swing
D Unity-gain frequency
D Maximum negative output voltage swing
D Common-mode rejection ratio
D Slew rate
D Phase margin
D Quiescent power dissipation
D DC output resistance
D Input bias current
D AC output resistance
D Open-loop voltage amplification
D Short-circuit output current limit
NOTE 3: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
3
99
VDD
+
egnd
rd1
rd2
rss
ro2
css
fb
rp
–
c1
7
11
12
+
c2
vlim
1
+
r2
9
6
IN+
–
vc
D
D
8
+
–
vb
ga
2
G
G
–
IN–
ro1
gcm
ioff
53
S
S
OUT
dp
91
10
iss
GND
4
dlp
–
vlp
–
ve
+ 54
5
92
–
hlim
–
vln
+
de
* TLV4112_5V operational amplifier ”macromodel” subcircuit
* updated using Model Editor release 9.1 on 01/18/00 at 15:50
Model Editor is an OrCAD product.
*
* connections: non–inverting input
*
| inverting input
*
| | positive power supply
*
| | | negative power supply
*
| | | | output
*
|| | | |
.subckt TLV4112_5V
12345
*
c1
11
12
2.2439E–12
c2
6
7
10.000E–12
css
10
99
454.55E–15
dc
5
53
dy
de
54
5
dy
dlp
90
91
dx
dln
92
90
dx
dp
4
3
dx
egnd
99
0
poly(2) (3,0) (4,0) 0 .5 .5
fb
7
99
poly(5) vb vc ve vlp vln 0
+ 33.395E6 –1E3 1E3 33E6 –33E6
ga
6
0
11
12 168.39E–6
gcm
0
6
10
99 168.39E–12
iss
hlim
ioff
j1
J2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model
.model
.model
.ends
*$
10
90
0
11
12
6
3
3
8
7
3
10
9
3
54
7
91
0
dx
dy
jx1
jx2
4
dc
13.800E–6
0
vlim 1K
6
dc
75E–9
2
10 jx1
1
10 jx2
9
100.00E3
11
5.9386E3
12
5.9386E3
5
10
99
10
4
3.3333E3
99
14.493E6
0
dc 0
53
dc .86795
4
dc .86795
8
dc 0
0
dc 300
92
dc 300
D(Is=800.00E–18)
D(Is=800.00E–18 Rs=1m Cjo=10p)
NJF(Is=150.00E–12 Beta=2.0547E–3 +Vto=–1)
NJF(Is=150.00E–12 Beta=2.0547E–3 + Vto=–1)
Figure 30. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
16
90
+
+
dc
dln
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
PINS **
8
14
A MAX
0.197
(5,00)
0.344
(8,75)
A MIN
0.189
(4,80)
0.337
(8,55)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
MECHANICAL INFORMATION
DGN (S-PDSO-G8)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
8
0,25 M
5
Thermal Pad
(See Note D)
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
1
0°– 6°
4
3,05
2,95
0,69
0,41
Seating Plane
1,07 MAX
0,15
0,05
0,10
4073271/A 04/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions include mold flash or protrusions.
The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
MECHANICAL INFORMATION
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
PINS **
DIM
A
16
9
14
A MAX
0.775
(19,69)
A MIN
0.745
(18,92)
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.035 (0,89) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.010 (0,25) M
0°– 15°
0.010 (0,25) NOM
14/18 PIN ONLY
4040049/C 08/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TLV4110, TLV4111, TLV4112, TLV4113
FAMILY OF HIGH OUTPUT DRIVE OPERATIONAL
AMPLIFIERS WITH SHUTDOWN
SLOS289A – DECEMBER 1999 – REVISED APRIL 2000
MECHANICAL INFORMATION
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0°– 15°
0.010 (0,25) M
0.010 (0,25) NOM
4040082 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated