ONSEMI NTP52N10D

NTP52N10
Power MOSFET
52 Amps, 100 Volts
N−Channel Enhancement Mode TO−220
Features
• Source−to−Drain Diode Recovery Time comparable to a Discrete
•
•
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Fast Recovery Diode
Avalanche Energy Specified
IDSS and RDS(on) Specified at Elevated Temperature
52 AMPERES
100 VOLTS
30 mΩ @ VGS = 10 V
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
N−Channel
D
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
100
Vdc
Drain−to−Source Voltage (RGS = 1.0 MΩ)
VDGR
100
Vdc
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tp10 ms)
VGS
VGSM
20
40
ID
ID
52
40
156
Adc
PD
178
1.43
Watts
W/°C
Operating and Storage Temperature Range
TJ, Tstg
−55 to
+150
°C
Single Drain−to−Source Avalanche Energy
− Starting TJ = 25°C
(VDD = 50 V, VGS = 10 Vdc,
IL(pk) = 40 A, L = 1.0 mH, RG = 25 Ω)
EAS
800
mJ
Drain − Continuous @ TA 25°C
− Continuous @ TA 100°C
− Pulsed (Note 1.)
Total Power Dissipation @ TA 25°C
Derate above 25°C
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
G
S
Vdc
IDM
°C/W
RθJC
RθJA
0.7
62.5
TL
260
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
4
TO−220AB
CASE 221A
STYLE 5
1
NTP52N10
LLYWW
1
Gate
2
3
3
Source
2
Drain
°C
NTP52N10
LL
Y
WW
1. Pulse Test: Pulse Width = 10 µs, Duty Cycle = 2%.
= Device Code
= Location Code
= Year
= Work Week
ORDERING INFORMATION
Device
NTP52N10
 Semiconductor Components Industries, LLC, 2003
December, 2003 − Rev. 2
1
Package
Shipping
TO−220AB
50 Units/Rail
Publication Order Number:
NTP52N10/D
NTP52N10
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
100
−
−
160
−
−
−
−
−
−
5.0
50
−
−
±100
2.0
−
2.92
−8.75
4.0
−
−
−
0.023
0.050
0.030
0.060
−
1.25
1.45
gFS
−
31
−
mhos
Ciss
−
2250
3150
pF
Coss
−
620
860
Crss
−
135
265
td(on)
−
15
25
tr
−
95
180
td(off)
−
74
150
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VGS = 0 Vdc, VDS = 100 Vdc, TJ =25°C)
(VGS = 0 Vdc, VDS = 100 Vdc, TJ =125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
µAdc
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−State Resistance
(VGS = 10 Vdc, ID = 26 Adc)
(VGS = 10 Vdc, ID = 26 Adc, TJ = 125°C)
RDS(on)
Drain−to−Source On−Voltage
(VGS = 10 Vdc, ID = 52 Adc)
VDS(on)
Forward Transconductance (VDS = 26 Vdc, ID = 10 Adc)
Vdc
mV/°C
Ω
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Notes 2. & 3.)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 80 Vdc, ID = 52 Adc,
VGS = 10 Vdc, RG = 9.1 Ω)
Fall Time
Gate Charge
(VDS = 80 Vdc,
Vd ID = 52 Adc,
Ad
VGS = 10 Vdc)
ns
tf
−
100
190
Qtot
−
72
135
Qgs
−
13
−
Qgd
−
37
−
VSD
−
−
1.06
0.95
1.5
−
Vdc
trr
−
148
−
ns
ta
−
106
−
tb
−
42
−
QRR
−
0.66
−
nC
BODY−DRAIN DIODE RATINGS (Note 2.)
Diode Forward On−Voltage
(IS = 52 Adc, VGS = 0 Vdc)
(IS = 52 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 52 Adc,
Ad VGS = 0 Vdc,
Vd
diS/dt = 100 A/µs)
Reverse Recovery Stored Charge
2. Indicates Pulse Test: P.W. = 300 µs Max, Duty Cycle = 2%.
3. Switching characteristics are independent of operating junction temperature.
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2
µC
NTP52N10
100
9V
7V
6V
60
5.5 V
40
5V
4.5 V
20
4V
1
2
3
4
5
6
8
7
9
60
40
TJ = 25°C
20
TJ = 100°C
10
2
TJ = −55°C
3
4
5
6
7
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω)
0
8
0.05
0.05
VGS = 10 V
TJ = 25°C
0.04
0.04
TJ = 100°C
0.03
0.03
TJ = 25°C
0.01
TJ = −55°C
20
30
40
50
60
70
90
80
100
0
0
20
40
60
80
100
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Drain Current and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
10000
2.5
2
VGS = 15 V
0.01
0
10
VGS = 10 V
0.02
0.02
VGS = 0 V
ID = 26 A
VGS = 10 V
TJ = 150°C
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω)
80
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
VDS ≥ 10 V
TJ = 25°C
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
80
100
VGS = 10 V
8V
1.5
1
1000
100
TJ = 100°C
0.5
−60
−30
0
30
60
90
120
150
10
30
40
50
60
70
80
90
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
100
NTP52N10
POWER MOSFET SWITCHING
The capacitance (Ciss) is read from the capacitance curve at
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
a voltage corresponding to the off−state condition when
controlled. The lengths of various switching intervals (∆t)
calculating td(on) and is read at a voltage corresponding to the
are determined by how fast the FET input capacitance can
on−state when calculating td(off).
be charged by current from the generator.
At high switching speeds, parasitic circuit elements
complicate
the analysis. The inductance of the MOSFET
The published capacitance data is difficult to use for
source
lead,
inside the package and in the circuit wiring
calculating rise and fall because drain−gate capacitance
which
is
common
to both the drain and gate current paths,
varies greatly with applied voltage. Accordingly, gate
produces
a
voltage
at the source which reduces the gate drive
charge data is used. In most cases, a satisfactory estimate of
current.
The
voltage
is determined by Ldi/dt, but since di/dt
average input current (IG(AV)) can be made from a
is
a
function
of
drain
current, the mathematical solution is
rudimentary analysis of the drive circuit so that
complex. The MOSFET output capacitance also
t = Q/IG(AV)
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
During the rise and fall time interval when switching a
resistance of the driving source, but the internal resistance
resistive load, VGS remains virtually constant at a level
is difficult to measure and, consequently, is not specified.
known as the plateau voltage, VSGP. Therefore, rise and fall
The resistive switching time variation versus gate
times may be approximated by the following:
resistance
(Figure 9) shows how typical switching
tr = Q2 x RG/(VGG − VGSP)
performance is affected by the parasitic circuit elements. If
tf = Q2 x RG/VGSP
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
where
The circuit used to obtain the data is constructed to minimize
VGG = the gate drive voltage, which varies from zero to VGG
common inductance in the drain and gate circuit loops and
RG = the gate drive resistance
is believed readily achievable with board mounted
and Q2 and VGSP are read from the gate charge curve.
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
During the turn−on and turn−off delay times, gate current is
approximates an optimally snubbed inductive load. Power
not constant. The simplest calculation uses appropriate
MOSFETs may be safely operated into an inductive load;
values from the capacitance curves in a standard equation for
however, snubbing reduces switching losses.
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
6000
VDS = 0 V
C, CAPACITANCE (pF)
5000
VGS = 0 V
TJ = 25°C
Ciss
4000
3000
Crss
Ciss
2000
Coss
1000
Crss
0
10
5
0
VGS
5
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
18
QT
16
80
14
12
60
10
VGS
Q1
6
40
Q2
4
20
ID = 52 A
TJ = 25°C
VDS
2
0
0
10
20
30
40
50
QG, TOTAL GATE CHARGE (nC)
60
0
70
1000
td(off)
VDD = 80 V
ID = 52 A
VGS = 10 V
tf
tr
100
t, TIME (ns)
100
20
8
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTP52N10
td(on)
10
1
1
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
IS, SOURCE CURRENT (AMPS)
60
50
VGS = 0 V
TJ = 25°C
40
30
20
10
0
0.25
0.35
0.45
0.55
0.65
0.75
0.85
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
0.95
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
The Forward Biased Safe Operating Area curves define
dissipated in the transistor while in avalanche must be less
the maximum simultaneous drain−to−source voltage and
than the rated limit and adjusted for operating conditions
drain current that a transistor can handle safely when it is
differing from those specified. Although industry practice is
forward biased. Curves are based upon maximum peak
to rate in terms of energy, avalanche energy capability is not
junction temperature and a case temperature (TC) of 25°C.
a constant. The energy rating decreases non−linearly with an
Peak repetitive pulsed power limits are determined by using
increase of peak current in avalanche and peak junction
the thermal response data in conjunction with the procedures
temperature.
discussed
in
AN569,
“Transient
Thermal
Although many E−FETs can withstand the stress of
Resistance−General Data and Its Use.”
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
current (IDM), the energy rating is specified at rated
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
continuous current (ID), in accordance with industry custom.
transition time (tr,tf) do not exceed 10 µs. In addition the total
The energy rating must be derated for temperature as shown
power averaged over a complete switching cycle must not
in the accompanying graph (Figure 12). Maximum energy at
exceed (TJ(MAX) − TC)/(RθJC).
currents below rated continuous ID can safely be assumed to
A Power MOSFET designated E−FET can be safely used
equal the values indicated.
in switching circuits with unclamped inductive loads. For
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5
NTP52N10
ID, DRAIN CURRENT (AMPS)
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
10 µs
100 µs
10
1 ms
10 ms
dc
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
10
1
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1000
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
SAFE OPERATING AREA
800
600
500
400
300
200
100
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
r(t). EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
ID = 40 A
700
150
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
0.00001
0.0001
0.001
0.01
t, TIME (µs)
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RθJC(t)
0.1
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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1.0
10
NTP52N10
PACKAGE DIMENSIONS
TO−220 THREE−LEAD
TO−220AB
CASE 221A−09
ISSUE AA
SEATING
PLANE
−T−
B
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
J
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
STYLE 5:
PIN 1. GATE
2. DRAIN
3 SOURCE
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7
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
NTP52N10
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NTP52N10/D