PJClamp0502Q DUAL ULTRA LOW CAPACITANCE ESD PROTECTOR ARRAY PRELIMINARY This Dual Unidirectional ESD Protector Array family have been designed to protect sensitive equipment against ESD in high speed transmission buses, operating at 5V and demanding the lowest insertion loss. This array offers an integrated solution to protect up to 2 data lines in applications, where the board space is a premium, in a Quad Flat no-Lead package that only occupies an area of 1.8 sq mm. 6 SPECIFICATION FEATURES 5 4 IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance Low Leakage Current, Maximum of 1µA at rated voltage 1 Maximum Capacitance of 1pF per device at 0Vdc 1MHz Peak Power Dissipation of 40W 8/20µs Waveform 1 Quad Flat No Lead package QFN (1.2x1.5 sq mm, Height: 0.75mm) Lead Free Package 100% Tin Plating, Matte finish 2 3 1 2 3 6 5 4 APPLICATIONS USB2.0 and IEEE 1394 Firewire Ports RF Power Amplifier Protection RF/Antenna Circuits QFN 1.2x1.5 sq mm MAXIMUM RATINGS (Per Device) Symbol Value Units Peak Pulse Power (8/20µs Waveform) P PP 40 W Peak Pulse Current (8/20µs Waveform) I PPM 3 A ESD Voltage (HBM Per MIL STD883C - Method 3015-6) V ESD 25 kV Operating Temperature Range TJ -55 to +150 °C Storage Temperature Range Tstg -55 to +150 °C Typical Max Units 5 V Rating ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25°C Parameter Reverse Stand-Off Voltage Conditions Symbol Min V WRM Reverse Breakdown Voltage VBR I BR = 1mA Reverse Leakage Current IR VR = 5V 1 µA Clamping Voltage (8/20µs) Vc I pp = 3A 12 V Off State Junction Capacitance Cj 1 pF 1/25/2006 0 Vdc Bias f = 1MHz between 4&2 or 6&2 Page 1 6 V www.panjit.com PJClamp0502Q TYPICAL CHARACTERISTIC CURVES (Per Device) Tj = 25°C Pulse Waveform 110 80 3 Percent of Ipp Ipp, Amps 100 90 2 50% of Ipp @ 20µs 70 60 50 40 30 Rise time 10-90% - 8µs 20 10 1 0 8 8.5 9 9.5 10 10.5 11 11.5 12 Clamping Voltage, V 0 5 10 15 time, µsec 20 25 30 Typical Capacitance vs. Bias Voltage @1MHz Capacitance, pF PRELIMINARY Clamping Voltage vs 8/20µs Ipp 4 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1/25/2006 1 2 3 Bias Voltage, Vdc 4 5 Page 2 www.panjit.com PJClamp0502Q PACKAGE DIMENSIONS AND SUGGESTED PAD LAYOUT 0.30±0.05 mm PRELIMINARY 1.5±0.05 mm 0.6±0.05 mm 1.2±0.05 mm 0.20±0.05 mm 0.35±0.05 mm 0.5 mm 22.04 mm 0.75±0.025 mm 0.2±0.025 mm 16 mil 31 mil 25.0 23.0 24 mil 49.0 55 mil 12.0 39 mil 19.7 Suggested Pad Layout (in mils) 1/25/2006 Alternate Pad Layout SOT523 (in mils) Page 3 www.panjit.com