LCDA05 through LCDA24 Low Capacitance TVS Diode Array For High-Speed Data Interfaces PROTECTION PRODUCTS Description Features The LCDA series of TVS arrays are designed to protect sensitive electronics from damage or latch-up due to ESD and other voltage-induced transient events. Each device will protect two high-speed lines. They are available with operating voltages of 5V, 12V, 15V and 24V. They are bidirectional devices and may be used on lines where the signal polarities are above and below ground. TVS diodes are solid-state devices designed specifically for transient suppression. They offer desirable characteristics for board level protection including fast response time, low operating and clamping voltage and no device degradation. The LCDA series devices feature low capacitance compensation diodes in series with standard TVS diodes to provide an integrated, low capacitance solution for use on high-speed interfaces. The LCDA series devices may be used to meet the immunity requirements of IEC 61000-4-2, level 4. Transient protection for high-speed data lines to IEC 61000-4-2 (ESD) ±15kV (air), ±8kV (contact) IEC 61000-4-4 (EFT) 40A (5/50ns) IEC 61000-4-5 (lightning) (8/20µs)* Protects two I/O lines Low capacitance for high-speed data lines Working voltages: 5V, 12V, 15V and 24V Low leakage current Low operating and clamping voltages Solid-state silicon avalanche technology Mechanical Characteristics JEDEC SO-8 package Molding compound flammability rating: UL 94V-0 Marking : Part Number, Date Code Packaging : Tape and Reel per EIA 481 Applications High-Speed Data Lines Microprocessor Based Equipment Universal Serial Bus (USB) Port Protection Notebooks, Desktops, and Servers Instrumentation LAN/WAN Equipment Peripherals *See Electrical Characteristics Tables for Ipp Circuit Diagram (Each Line Pair) Schematic & PIN Configuration Pin 1 and 2 1 8 2 7 3 6 4 5 Pin 7 and 8 SO-8 (Top View) Revision 08/15/2006 1 www.semtech.com LCDA05 through LCDA24 PROTECTION PRODUCTS Absolute Maximum Rating R ating Symbol Value Units Peak Pulse Power (tp = 8/20µs) Pp k 300 Watts Lead Soldering Temperature TL 260 (10 sec.) °C Operating Temperature TJ -55 to +125 °C TSTG -55 to +150 °C Storage Temperature Electrical Characteristics LCDA05 Parameter Symbol Conditions Minimum Typical Maximum Units 5 V Reverse Stand-Off Voltage VRWM Reverse Breakdown Voltage V BR It = 1mA Reverse Leakage Current IR VRWM = 5V, T=25°C 20 µA Clamp ing Voltage VC IPP = 1A, tp = 8/20µs 9.8 V Clamp ing Voltage VC IPP = 5A, tp = 8/20µs 11 V Maximum Peak Pulse Current IP P tp = 8/20µs 17 A Junction Cap acitance Cj Between I/O Pins and Ground VR = 0V, f = 1MHz 5 pF Symbol Conditions Maximum Units 12 V 6 V LCDA12 Parameter Minimum Typical Reverse Stand-Off Voltage VRWM Reverse Breakdown Voltage V BR It = 1mA Reverse Leakage Current IR VRWM = 12V, T=25°C 1 µA Clamp ing Voltage VC IPP = 1A, tp = 8/20µs 19 V Clamp ing Voltage VC IPP = 5A, tp = 8/20µs 24 V Maximum Peak Pulse Current IP P tp = 8/20µs 12 A Junction Cap acitance Cj Between I/O Pins and Ground VR = 0V, f = 1MHz 5 pF 2005 Semtech Corp. 2 13.3 V www.semtech.com LCDA05 through LCDA24 PROTECTION PRODUCTS Electrical Characteristics (continued) LCDA15 Parameter Symbol Conditions Minimum Typical Maximum Units 15 V Reverse Stand-Off Voltage VRWM Reverse Breakdown Voltage V BR It = 1mA Reverse Leakage Current IR VRWM = 15V, T=25°C 1 µA Clamp ing Voltage VC IPP = 1A, tp = 8/20µs 24 V Clamp ing Voltage VC IPP = 5A, tp = 8/20µs 30 V Maximum Peak Pulse Current IP P tp = 8/20µs 10 A Junction Cap acitance Cj Between I/O Pins and Ground VR = 0V, f = 1MHz 5 pF Symbol Conditions Maximum Units 24 V 16.7 V LCDA24 Parameter Minimum Typical Reverse Stand-Off Voltage VRWM Reverse Breakdown Voltage V BR It = 1mA Reverse Leakage Current IR VRWM = 24V, T=25°C 1 µA Clamp ing Voltage VC IPP = 1A, tp = 8/20µs 43 V Clamp ing Voltage VC IPP = 5A, tp = 8/20µs 55 V Maximum Peak Pulse Current IP P tp = 8/20µs 5 A Junction Cap acitance Cj Between I/O Pins and Ground VR = 0V, f = 1MHz 5 pF 2005 Semtech Corp. 3 26.7 V www.semtech.com LCDA05 through LCDA24 PROTECTION PRODUCTS Typical Characteristics Non-Repetitive Peak Pulse Power vs. Pulse Time Power Derating Curve 10 110 90 % of Rated Power or IPP Peak Pulse Power - Ppk (kW) 100 1 0.1 80 70 60 50 40 30 20 10 0.01 0 0.1 1 10 100 0 1000 25 50 75 100 125 150 Ambient Temperature - TA (oC) Pulse Duration - tp (µs) Pulse Waveform 110 Waveform Parameters: tr = 8µs td = 20µs 100 90 Percent of IPP 80 70 -t e 60 50 40 td = IPP/2 30 20 10 0 0 5 10 15 20 25 30 Time (µs) ESD Discharge Parameters Per IEC 61000-4-2 ESD Pulse Waveform (Per IEC 61000-4-2) 2005 Semtech Corp. 4 Level First Peak Current (A ) Peak Current at 30ns (A ) Peak Current at 60ns (A ) Test Test Voltage Voltage (Contact (A ir Discharge) Discharge) ( kV ) (kV) 1 7.5 4 8 2 2 2 15 8 4 4 4 3 22.5 12 6 6 8 4 30 16 8 8 15 www.semtech.com LCDA05 through LCDA24 PROTECTION PRODUCTS Applications Information LCDA Connection Diagram Device Connection for Protection of Two High-Speed Data Lines The LCDAxx is designed to protect up to two high-speed data lines. The LCDAxx utilizes a low capacitance compensation diode in series with, but in opposite polarity to a TVS diode in each line. The resulting capacitance is less than 5pF per line. Each line will only suppress transient events in one polarity. Therefore, to achieve protection in both positive and negative polarity, a second TVS/rectifier pair is connected in anti-parallel to the first. Pins 1, 2, 7, and 8 are used to protect one data line. Pins 3, 4, 5, and 6 are used to protect the second data line. The device is connected as follows: z z z z z 2 7 3 6 4 5 I/O 1 I/O 2 I/O Line Protection Pins 1 and 2 are tied together and pins 7 and 8 are tied together providing the protection circuit for one I/O line. Pins 3 and 4 are tied together and pins 5 and 6 are tied together providing the protection circuit for the second I/O line. Since the device is electrically symmetrical, either side of the connected pairs may be used to protect the lines. The other side of the pair is used to make the ground connection. The ground connections should be made directly to the ground plane for best results. The path length is kept as short as possible to reduce the effects of parasitic inductance in the board traces. Connection Options To Protected Device Line 1 In/Out Good circuit board layout is critical for the suppression of ESD induced transients. The following guidelines are recommended: z 8 I/O 2 Circuit Board Layout Recommendations for Suppression of ESD. z 1 I/O 1 Line 2 Ground Place the TVS near the input terminals or connectors to restrict transient coupling. Minimize the path length between the TVS and the protected line. Minimize all conductive loops including power and ground loops. The ESD transient return path to ground should be kept as short as possible. Never run critical signals near board edges. Use ground planes whenever possible. 1 8 2 7 3 6 4 5 Line 1 Ground Line 2 In/Out From Connector To Protected Device Line 1 In/Out 1 8 2 7 3 6 Ground 4 Line 2 In/Out 5 From Connector 2005 Semtech Corp. 5 www.semtech.com LCDA05 through LCDA24 PROTECTION PRODUCTS Applications Information (continued) Matte Tin Lead Finish Matte tin has become the industry standard lead-free replacement for SnPb lead finishes. A matte tin finish is composed of 100% tin solder with large grains. Since the solder volume on the leads is small compared to the solder paste volume that is placed on the land pattern of the PCB, the reflow profile will be determined by the requirements of the solder paste. Therefore, these devices are compatible with both lead-free and SnPb assembly techniques. In addition, unlike other lead-free compositions, matte tin does not have any added alloys that can cause degradation of the solder joint. 2005 Semtech Corp. 6 www.semtech.com LCDA05 through LCDA24 PROTECTION PRODUCTS Outline Drawing - SO-8 A h D e N h H 2X E/2 E1 E 1 0.25 L (L1) e/2 DETAIL B 01 A D aaa C SEATING PLANE A2 A C SEE DETAIL A .053 .069 .010 .004 .065 .049 .012 .020 .010 .007 .189 .193 .197 .150 .154 .157 .236 BSC .050 BSC .010 .020 .016 .028 .041 (.041) 8 8° 0° .004 .010 .008 1.35 1.75 0.10 0.25 1.25 1.65 0.31 0.51 0.17 0.25 4.80 4.90 5.00 3.80 3.90 4.00 6.00 BSC 1.27 BSC 0.25 0.50 0.40 0.72 1.04 (1.04) 8 0° 8° 0.10 0.25 0.20 SIDE VIEW A1 bxN bbb DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc c GAGE PLANE 2 ccc C 2X N/2 TIPS DIM C A-B D NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AA. Land Pattern - SO-8 X DIM (C) G C G P X Y Z Z Y DIMENSIONS INCHES MILLIMETERS (.205) .118 .050 .024 .087 .291 (5.20) 3.00 1.27 0.60 2.20 7.40 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 300A. 2005 Semtech Corp. 7 www.semtech.com LCDA05 through LCDA24 PROTECTION PRODUCTS Ordering Information Part Number Lead Finish Qty per Reel Reel Size LCDA05.TB SnPb 500 7 Inch LCDA12.TB SnPb 500 7 Inch LCDA15.TB SnPb 500 7 Inch LCDA24.TB SnPb 500 7 Inch LCDA05.TBT Pb Free 500 7 inch LCDA12.TBT Pb Free 500 7 inch LCDA15.TBT Pb Free 500 7 inch LCDA24.TBT Pb Free 500 7 inch L C DA 0 5 SnPb 95/Tube N/A L C DA 1 2 SnPb 95/Tube N/A L C DA 1 5 SnPb 95/Tube N/A LCDA24 SnPb 95/Tube N/A LCDA05.T Pb Free 95/Tube N/A LCDA12.T Pb Free 95/Tube N/A LCDA15.T Pb Free 95/Tube N/A LCDA24.T Pb Free 95/Tube N/A Contact Information Semtech Corporation Protection Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2005 Semtech Corp. 8 www.semtech.com