PD85004 RF power transistor the LdmoST plastic family Features ■ Excellent thermal stability ■ Common source configuration ■ Broadband performances POUT = 4 W with 17 dB gain @ 870 MHz ■ Plastic package ■ ESD protection ■ Supplied in tape and reel ■ In compliance with the 2002/95/EC european directive SOT-89 Figure 1. Pin connection Description Source The PD85004 is a common source N-channel, enhancement-mode lateral field-effect RF power transistor. It is designed for high gain, broad band commercial and industrial applications. It operates at 13.6 V in common source mode at frequencies of up to 1 GHz. PD85004’s superior gain and efficiency makes it an ideal solution for mobile radio. Source Gate Table 1. Drain Device summary Order code Marking Package Packaging PD85004 8504 SOT-89 Tape and reel August 2008 Rev 2 1/18 www.st.com 18 Contents PD85004 Contents 1 2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Static . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 ESD protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 Moisture sensitivity level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 DC curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 RF curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Schematic and BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Demonstration board photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 2/18 8.1 Thermal pad and via design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.2 Soldering profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PD85004 Electrical data 1 Electrical data 1.1 Maximum ratings Table 2. Absolute maximum ratings (TCASE = 25 °C) Symbol Value Unit V(BR)DSS Drain-source voltage 40 V VGS Gate-source voltage -0.5 to +15 V Drain current 2 A Power dissipation 6 W 150 °C -65 to +150 °C Value Unit 21 °C/W ID PDISS TJ TSTG 1.2 Parameter Max. operating junction temperature Storage temperature Thermal data Table 3. Symbol RthJC Thermal data Parameter Junction - case thermal resistance 3/18 Electrical characteristics 2 PD85004 Electrical characteristics TCASE = +25 oC 2.1 Static Table 4. Static Symbol 2.2 Test conditions Min VDS = 25 V 1 μA IGSS VGS = 5 V VDS = 0 V 1 μA VGS(Q) VDS = 13.6 V ID = 50 mA 3.9 V VDS(ON) VGS = 10 V ID = 0.25 A 0.27 V CISS VGS = 0 V VDS = 13.6 V f = 1 MHz 16 pF COSS VGS = 0 V VDS = 13.6 V f = 1 MHz 14 pF CRSS VGS = 0 V VDS = 13.6 V f = 1 MHz 1.1 pF Dynamic Dynamic Test conditions Min Typ Max Unit POUT VDD = 13.6 V, IDQ = 50 mA, PIN = 0.1 W, f = 870 MHz 4 5 W GPS VDD = 13.6 V, IDQ = 50 mA, POUT = 4 W, f = 870 MHz 15 17 dB ND VDD = 13.6 V, IDQ = 50 mA, POUT = 4 W, f = 870 MHz 60 65 % Load VDD = 13.6 V, IDQ = 50 mA, POUT = 4 W, f = 870 MHz mismatch All phase angles 20:1 VSWR ESD protection characteristics Table 6. ESD protection characteristics Test conditions Class Human body model 2 Machine model M3 Moisture sensitivity level Table 7. 4/18 Unit VGS = 0 V Symbol 2.4 Max IDSS Table 5. 2.3 Typ Moisture sensitivity level Test methodology Rating J-STD-020B MSL 3 PD85004 3 Impedances Impedances Figure 2. Impedances Table 8. Broadband impedances F(MHz) ZGS ZDL 860 2.46+ j 6.63 8.38+ j 2,83 880 2.59+ j 6.83 8.08+ j 3.46 900 2.63+ j 6.97 7.77 + j 4.10 920 2.57+ j 7.09 7.50+ j 4.77 940 2.42+ j 7.17 7.15+ j 5.37 960 2.27+ j 7.34 6.95+ j 6.07 5/18 DC curves 4 PD85004 DC curves Figure 3. DC output characteristics Figure 4. ID vs VGS ID vs Vgs VGS=10V VGS=9V VGS=8V VGS=7V PD84002 VGS=6V VGS=5V VGS=4V Figure 5. Capacitances vs drain voltage 30 Capacitance (pF) 25 CRSS COSS CISS 20 15 10 5 0 0 2 4 6 8 Vdd (V) 6/18 10 12 14 16 PD85004 RF curves 5 RF curves Figure 6. Output power and drain efficiency vs frequency 13.6 V / 50 mA / Pin = 19 dBm Figure 7. 80 6 30 3 Pout Gain (dB) 40 4 18 Efficiency (%) Pout (W) 19 60 50 880 900 920 Pin=19 dBm 15 12 860 0 960 940 16 13 10 2 860 17 14 20 Eff Gain vs Frequency 13.6V / 50mA 20 70 5 Gain vs frequency 13.6 V / 50 mA 880 900 920 940 960 Frequency (MHz) Frequency (MHz) Figure 8. Input return loss vs frequency 13.6 V / 50 mA Figure 9. Gain vs output power 13.6 V / 50 mA 13.6V / 50mA 0 20 -2 19 Pin=19 dBm -4 18 17 Gain (dB) IRL (dB) -6 -8 -10 16 15 860 MHz 14 900 MHz 960 MHz -12 13 -14 12 -16 11 0 -18 1 2 3 4 5 6 7 Pout (W) -20 820 840 860 880 900 920 940 960 980 1000 Frequency (MHz) Figure 10. Drain current vs output power 13.6 V / 50 mA Figure 11. Output power vs input power 13.6 V / 50 mA 0.8 40 860 MHz 900 MHz 38 960 MHz Output power (dBm) Drain current (A) 0.7 0.6 0.5 0.4 36 34 32 860 MHz 900 MHz 960 MHz 30 28 0.3 26 0.2 24 28 29 30 31 32 33 34 35 Output Power (dBm) 36 37 38 39 40 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Input power (dBm) 7/18 RF curves PD85004 Figure 12. Harmonics vs frequency 13.6 V / 50 mA 0 H2 -10 H3 Harmonics (dB) -20 -30 -40 -50 -60 -70 -80 860 880 900 920 Frequency (MHz) 8/18 940 960 PD85004 6 Schematic and BOM Schematic and BOM Figure 13. Schematic Vcc 1+ MSub R3 + B1 C3 FR4 H=20 mil R2 2- B2 C4 C5 C1 L1 C2 R1 TL4 TL5 TL6 C11 RFin C6 TL1 C8 TL2 C9 C7 RFout C12 TL3 C10 LDMOS PD85004 9/18 Schematic and BOM Table 9. Components part list Component ID Description B1 Manufacturer Part code Ferrite bead Panasonic EXCELDRC35C B2 Ferrite bead Panasonic EXCELDRC35C C1, C2 Capacitor 120 pF 0603 Murata GRM39-C0G121J50D500 C3 Capacitor 1 nF 0603 Murata GRM39-X7R102K50C560 C4 Capacitor 10 nF 0603 Murata GRM39-X7R103K50C560 C5 Capacitor 10 uF SMT Panasonic EEVHB1V100P C6, C7 Capacitor 39 pF 0603 Murata GRM39-C0G390J50D500 C8 Capacitor 3.3 pF 0603 Murata GRM39-C0G3R3C50Z500 C9 Capacitor 12 pF 0603 Murata GRM39-C0G120J50D500 C10 Capacitor 22 pF 0603 Murata GRM39-C0G220J50D500 C11 Capacitor 6,8 pF 0603 Murata GRM39-C0G6R8D50Z500 C12 Capacitor 1,5 pF 0603 Murata GRM39-C0G1R5C50Z500 L1 Inductor 12.55 nH Coilcraft 1606-10 R1 Resistor 150 Ω R2 Potentiometer 10 KΩ R3 Resistor 1K Value Case size 0603 0603 TL1 W= 0.92 mm L = 13.6 mm TL2 W=0.92 mm L = 3.5 mm W=0.92 mm L = 4.2 mm W=0.92 mm L = 3.8 mm TL5 W=0.92 mm L = 4.2 mm TL6 W=0.92 mm L = 11.3 mm 50 Ω 60 mils TL3 TL4 Transmission Line RF in, RF out SMA-CONN PD85004 LDMOS Board 10/18 PD85004 Tyco electronics Bourns electronics 3214W-1-103E Tyco electronics 01623440-1 JOHNSON 142-0701-801 STMicroelectronics PD85004 FR-4 THk = 0.020" 2 OZ Cu both sides PD85004 7 Demonstration board photo Demonstration board photo Figure 14. Demonstration board photo 11/18 Package mechanical data 8 PD85004 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 12/18 PD85004 Package mechanical data Table 10. SOT-89 mechanical data Dim. mm. Min Typ Inch Max Min Typ Max A 1.4 1.6 55.1 63.0 B 0.44 0.56 17.3 22.0 B1 0.36 0.48 14.2 18.9 C 0.35 0.44 13.8 17.3 C1 0.35 0.44 13.8 17.3 D 4.4 4.6 173.2 181.1 D1 1.62 1.83 63.8 72.0 E 2.29 2.6 90.2 102.4 e 1.42 1.57 55.9 61.8 e1 2.92 3.07 115.0 120.9 H 3.94 4.25 155.1 167.3 L 0.89 1.2 35.0 47.2 Figure 15. Package dimensions 13/18 Package mechanical data 8.1 PD85004 Thermal pad and via design Thernal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device. The via pattern is based on thru-hole vias with 0.203 mm to 0.330 mm finished hole size on a 0.5 mm to 1.2 mm grid pattern with 0.025 plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. Figure 16. Pad layout details 14/18 PD85004 8.2 Package mechanical data Soldering profile Figure 17 shows the recommeded solder for devices that have Pb-free terminal plating and where a Pb-free solder is used. Figure 17. Recommended solder profile Figure 18 shows the recommeded solder for devices with Pb-free terminal plating used with leaded solder, or for devices with leaded terminal plating used with a leaded solder. Figure 18. Recommended solder profile for leaded devices 15/18 Package mechanical data Figure 19. Reel information 16/18 PD85004 PD85004 9 Revision history Revision history Table 11. Document revision history Date Revision Changes 05-Dec-2007 1 Initial release. 22-Aug-2008 2 Updated marking in Table 1 on page 1 17/18 PD85004 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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