STL20NM20N N-CHANNEL 200V - 0.088Ω - 20A PowerFLAT™ ULTRA LOW GATE CHARGE MDmesh™ II MOSFET Table 1: General Features TYPE STL20NM20N ■ ■ ■ ■ ■ ■ ■ ■ Figure 1: Package VDSS RDS(on) ID 200 V < 0.105 Ω 20 A WORLDWIDE LOWEST GATE CHARGE TYPICAL RDS(on) = 0.088Ω IMPROVED DIE-TO-FOOTPRINT RATIO VERY LOW PROFILE PACKAGE (1mm MAX) VERY LOW THERMAL RESISTANCE LOW GATE RESISTANCE LOW INPUT CAPACITANCE HIGH dv/dt and AVALANCHE CAPABILITIES DESCRIPTION This 200V MOSFET with a new advanced layout brings all unique advantages of MDmesh technology to lower voltages. The device exhibits worldwide lowest gate charge for any given onresistance.Its use is therefore ideal as primary switch in isolated DC-DC converters for Telecom and Computer applications.Used in combination with secondary-side low-voltage STripFETTM products, it contributes to reducing losses and boosting efficiency.The new PowerFLAT™ package allows a significant reduction in board space without compromising performance. PowerFlat (6x5) (Chip Scale Package) Figure 2: Internal Schematic Diagram APPLICATIONS The MDmeshTM family is very suitable for increasing power density allowing system miniaturization and higher efficiencies Table 2: Order Codes SALES TYPE MARKING PACKAGE PACKAGING STL20NM20N L20NM20N PowerFLAT™(6x5) TAPE & REEL Rev. 6 January 2006 1/10 STL20NM20N Table 3: Absolute Maximum ratings Symbol VDS VDGR Parameter Value Unit Drain-source Voltage (VGS = 0) 200 V Drain-gate Voltage (RGS = 20 kΩ) 200 V VGS Gate- source Voltage ± 30 V ID (1) Drain Current (continuous) at TC = 25°C (Steady State) Drain Current (continuous) at TC = 100°C 20 12.3 A A IDM (3) Drain Current (pulsed) 80 A PTOT (2) Total Dissipation at TC = 25°C (Steady State) 2.5 W PTOT (1) Total Dissipation at TC = 25°C (Steady State) 80 W 0.02 W/°C 10 V/ns Derating Factor (2) dv/dt (4) Peak Diode Recovery voltage slope Table 4: Thermal Data Symbol Parameter Typ. Rthj-c Thermal Resistance Junction-case Rthj-pcb (2) Thermal Resistance Junction-pcb Tj Tstg 35 Max. Operating Junction Temperature Storage Temperature Max. Unit 1.56 °C/W 50 °C/W -55 to 150 °C Max. Value Unit Table 5: Avalanche Characteristics Symbol Parameter IAS Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 20 A EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAR, VDD = 35 V) 380 mJ ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 6: On/Off Symbol V(BR)DSS 2/10 Parameter Test Conditions Drain-source Breakdown Voltage ID = 1 mA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating, TC = 125 °C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 30 V VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDs(on) Static Drain-source On Resistance VGS = 10V, ID = 10 A Min. Typ. Max. 200 3 Unit V 1 10 µA µA ±100 nA 4 5 V 0.088 0.105 Ω STL20NM20N ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Dynamic Symbol gfs (5) Ciss Coss Crss Coss eq. (*) Parameter Test Conditions Forward Transconductance VDS = 15 V, ID = 10 A Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Min. Typ. Max. Unit 8 S VDS = 25 V, f = 1 MHz, VGS = 0 800 330 130 pF pF pF VGS = 0V, VDS = 0V to 160 V 225 pF ns ns ns ns td(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time VDD = 100 V, ID = 10 A RG = 4.7Ω VGS = 10 V (see Figure 16) 40 15 40 11 Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD = 160 V, ID = 20 A, VGS = 10 V (see Figure 19) 32 6 25 50 nC nC nC (*) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 8: Source Drain Diode Symbol Max. Unit Source-drain Current 20 A ISDM (3) Source-drain Current (pulsed) 80 A VSD (5) Forward On Voltage ISD = 20 A, VGS = 0 1.3 V Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 20 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 25°C (see Figure 17) 160 960 128 ns nC A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 20 A, di/dt = 100 A/µs, VDD = 100 V, Tj = 150°C (see Figure 17) 225 1642 15 ns nC A ISD trr Qrr IRRM trr Qrr IRRM Note: 1. 2. 3. 4. 5. Parameter Test Conditions Min. Typ. The value is rated according to Rthj-c. When Mounted on FR-4 Board of 1inch2, 2 oz Cu Pulse width limited by safe operating area ISD ≤ 20A, di/dt ≤ 400A/µs, VDD ≤ V(BR)DSS Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 3/10 STL20NM20N Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/10 STL20NM20N Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized On Resistance vs Temperature Figure 11: Source-Drain Diode Forward Characteristics Figure 14: Normalized BVdss vs Temperature 5/10 STL20NM20N Figure 15: Unclamped Inductive Load Test Circuit Figure 18: Unclamped Inductive Wafeform Figure 16: Switching Times Test Circuit For Resistive Load Figure 19: Gate Charge Test Circuit Figure 17: Test Circuit For Inductive Load Switching and Diode Recovery Times 6/10 STL20NM20N In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 7/10 STL20NM20N PowerFLAT™ (6x5) MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. 0.80 0.83 0.93 0.031 0.032 0.036 A1 0.02 0.05 0.0007 0.0019 A3 0.20 A b 0.35 0.47 0.013 0.015 D 5.00 0.196 D1 4.75 0.187 D2 4.15 E 4.20 4.25 5.75 3.48 3.53 E4 2.58 2.63 2.68 0.135 1.27 0.70 0.80 0.167 0.226 3.43 e 0.165 0.018 0.236 E2 L 0.163 6.00 E1 8/10 0.40 0.007 0.137 0.139 0.103 0.105 0.050 0.90 0.027 0.031 0.035 STL20NM20N Table 9: Revision History Date Revision Description of Changes 16-Feb-2005 2 New stylesheet 09-Jun-2005 20-Jun-2005 04-Nov-2005 09-Jan-2006 3 4 5 6 Some Values changed on table 6 and 8 Inserted curves Updated mechanical data Modified value on table 8, inserted ecopack indication New footprint 9/10 STL20NM20N Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 10/10