STSJ100NH3LL N-CHANNEL 30 V - 0.0032 Ω - 25 A PowerSO-8™ STripFET™ III MOSFET FOR DC-DC CONVERSION Table 1: General Features Figure 1: Package TYPE VDSS RDS(on) ID STSJ100NH3LL 30V < 0.0035Ω 25A ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.0032Ω @ 10V OPTIMAL RDS(on) x Qg TRADE-OFF @ 4.5V SWITCHING LOSSES REDUCED LOW THRESHOLD DEVICE IMPROVED JUNCTION-CASE THERMAL RESISTANCE DESCRIPTION The STSJ100NH3LL utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This process coupled to unique metallization techniques realizes the most advanced low voltage MOSFET in SO-8 ever produced. The exposed slug reduces the Rthj-c improving the current capability. PowerSO-8™ Figure 2: Internal Schematic Diagram APPLICATIONS ■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS FOR MOBILE PCs DRAIN CONTACT ALSO ON THE BACKSIDE Table 2: Order Codes SALES TYPE MARKING PACKAGE PACKAGING STSJ100NH3LL 100H3LL- PowerSO-8 TAPE & REEL Rev. 5 November 2005 1/11 STSJ100NH3LL Table 3: Absolute Maximum ratings Symbol Parameter VDS Drain-source Voltage (VGS = 0) Value Unit 30 V VGS Gate- source Voltage ± 16 V ID(2) Drain Current (continuous) at TC = 25°C 100 A ID(1) Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C 25 A 15.6 A IDM(3) Drain Current (pulsed) 100 A Ptot(2) Total Dissipation at TC = 25°C 70 W Ptot(1) Total Dissipation at TC = 25°C 3 W 1.8 42 150 -55 to 150 °C/W °C/W °C °C Max Value Unit 12.5 A 1.3 J ID Table 4: Thermal Data Rthj-c Rthj-pcb(4) Tj Tstg Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Operating Junction Temperature Storage Temperature Max Max Table 5: Avalanche Characteristics Symbol Parameter IAV Not-Repetitive Avalanche Current (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy (starting Tj = 25 °C, ID = IAV, VDD = 24 V) ELECTRICAL CHARACTERISTICS (TCASE =25°C UNLESS OTHERWISE SPECIFIED) Table 6: On /Off Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250µA, VGS = 0 Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS =Max Rating ,TC = 125°C Gate-body Leakage Current (VDS = 0) VGS = ± 16V VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA RDS(on) Static Drain-source On Resistance VGS = 10V, ID = 12.5A VGS = 4.5V, ID = 12.5A V(BR)DSS IDSS IGSS 2/11 Min. Typ. Max. 30 Unit V 1 10 µA µA ±100 nA 1 V 0.0032 0.004 0.0035 0.005 Ω Ω STSJ100NH3LL ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Dynamic Symbol gfs (5) Ciss Coss Crss RG Parameter Test Conditions Forward Transconductance VDS=10V, ID = 12.5A Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V, f = 1 MHz, VGS = 0 Gate Input Resistance f=1MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain Min. Typ. Max. Unit 30 S 4450 655 50 pF pF pF 1 2 3 Ω Min. Typ. Max. Unit Table 8: Switching On Symbol Parameter Test Conditions td(on) tr Turn-on Delay Time Rise Time VDD = 15V, ID = 12.5A RG = 4.7Ω , VGS = 10V (see Figure 15) Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD=15V, ID=25A VGS=4.5V (see Figure 17) 18 50 ns ns 30 12.5 10 40 nC nC nC Typ. Max. Unit Table 9: Switching Off Symbol td(off) tf Parameter Turn-off Delay Time Fall Time Test Conditions Min. VDD = 15V, ID = 12.5A RG = 4.7Ω , VGS = 10V (see Figure 15) 75 8 ns ns Table 10: Source Drain Diode Symbol Parameter ISD ISDM Source-drain Current Source-drain Current (pulsed) VSD(5) trr Qrr IRRM Test Conditions Forward On Voltage ISD = 25A ,VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 25A, di/dt = 100A/µs VDD = 25V, Tj = 150°C (see Figure 16) Min. Typ. 32 34 2.1 Max. Unit 25 100 A A 1.3 V ns nC A Notes 1. 2. 3. 4. 5. This value is noted according to Rthj-pcb This value is noted according to Rthj-c Pulse width limited by safe operating area When Mounted on 1 inch² FR-4 board, 2 oz Cu (t ≤ 10 sec.) Pulsed: pulse duration=300µs, duty cycle 1.5% 3/11 STSJ100NH3LL Figure 3: Safe Operating Area Figure 6: Thermal Impedance Figure 4: Output Characteristics Figure 7: Transfer Characteristics Figure 5: Transconductance Figure 8: Static Drain-source On Resistance 4/11 STSJ100NH3LL Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations Figure 10: Normalized Gate Thereshold Voltage vs Temperature Figure 13: Normalized BVDSS vs Temperature Figure 11: Normalized On Resistance vs Temperature Figure 14: Source-Drain Diode Forward Characteristics 5/11 STSJ100NH3LL Table 11: Allowable Iav vs. Time in Avalanche The previous curve gives the single pulse safe operating area for unclamped inductive loads, under the following conditions: PD(AVE) =0.5*(1.3*BVDSS *IAV ) EAS(AR) =PD(AVE) *tAV Where: IAV is the Allowable Current in Avalanche PD(AVE) is the Average Power Dissipation in Avalanche (Single Pulse) tAV isthe Time in Avalanche 6/11 STSJ100NH3LL Figure 15: Switching Times Test Circuit For Resistive Load Figure 17: Gate Charge Test Circuit Figure 16: Test Circuit For Diode Recovery Times 7/11 STSJ100NH3LL In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 8/11 STSJ100NH3LL PowerSO-8™ MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.25 a2 MAX. 0.068 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 0.196 c1 45° (typ.) D 4.8 5.0 0.188 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 3.81 0.150 e4 2.79 0.110 F 3.8 4.0 0.14 0.157 L 0.4 1.27 0.015 0.050 M S 0.6 0.023 8° (max.) 9/11 STSJ100NH3LL Table 12: Revision History Date Revision 14-Sep-2004 23-May-2005 29-Jun-2005 16-Nov-2005 2 3 4 5 10/11 Description of Changes Preliminary Data. New values on table 5 New RG value on table 6 Complete version STSJ100NH3LL Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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