STL50NH3LL N-channel 30 V - 0.011 Ω - 13 A - PowerFLAT™ (6x5) ultra low gate charge STripFET™ Power MOSFET Features Type VDSS RDS(on) ID STL50NH3LL 30V <0.013Ω 13A (4) ■ Improved die-to-footprint ratio ■ Very low profile package (1 mm max) ■ Very low thermal resistance ■ Very low gate charge ■ Low threshold device PowerFLAT™( 6x5 ) Applications ■ Switching application Figure 1. Description Internal schematic diagram This application specific Power MOSFET is the latest generation of STMicroelectronics unique “STripFET™” technology. The resulting transistor is optimized for low on-resistance and minimal gate charge. The Chip-scaled PowerFLAT™ package allows a significant board space saving, still boosting the performance. Table 1. Device summary Order code Marking Package Packaging STL50NH3LL L50NH3LL PowerFLAT™ (6x5) Tape & reel December 2007 Rev 10 1/12 www.st.com 12 Contents: STL50NH3LL Contents: 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 ................................................ 8 STL50NH3LL 1 Electrical ratings Electrical ratings Table 2. Absolute maximum ratings Symbol VDS Parameter Drain-source voltage (VGS = 0) Value Unit 30 V VGS(1) Gate-source voltage ± 16 V VGS(2) Gate-source voltage ± 18 V ID(3) Drain current (continuous) at TC = 25°C 27 A ID(4) Drain current (continuous) at TC=100°C 8.1 A (5) Drain current (pulsed) 108 A (4) Drain current (continuous) at TC = 25°C 13 A PTOT (4) Total dissipation at TC = 25°C 4 W (3) Total dissipation at TC = 25°C 60 W 0.03 W/°C -55 to 150 °C Value Unit Thermal resistance junction-case (Drain) 2.08 °C/W Thermal resistance junction-ambient 31.3 °C/W Value Unit IDM ID PTOT Derating factor TJ Operating junction temperature Storage temperature Tstg 1. Continuous mode 2. Guaranteed for test time < 15ms 3. The value is rated according Rthj-c and is limited by wire bonding 4. The value is rated according Rthj-pcb 5. Pulse width limited by safe operating area Table 3. Thermal resistance Symbol Rthj-case Rthj-pcb (1) Parameter 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10sec Table 4. Symbol Avalanche data Parameter IAV Not-repetitive avalanche current 7.5 A EAS Single pulse avalanche energy (starting Tj=25°C, Id=Iav) 150 mJ 3/12 Electrical characteristics 2 STL50NH3LL Electrical characteristics (TCASE=25°C unless otherwise specified) Table 5. Symbol V(BR)DSS On/off states Parameter Drain-source breakdown voltage Test conditions ID = 25 0µA, VGS= 0 Zero gate voltage drain current (VGS = 0) IGSS Gate body leakage current (VDS = 0) VGS = ±16 V VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA RDS(on) Static drain-source on resistance VGS= 10 V, ID= 6.5 A Symbol gfs (1) Ciss Coss Crss Qg 30 1 10 µA µA ±100 nA 1 VGS= 4.5 V, ID= 6. 5A Unit V VDS = Max rating @125°C Parameter Test conditions V 0.011 0.012 0.013 0.015 Ω Ω Min. Typ. Max. Unit Forward transconductance VDS =10 V, ID = 6.5 A 32 S Input capacitance Output capacitance Reverse transfer capacitance VDS =25 V, f=1 MHz, VGS=0 965 285 38 pF pF pF Qgd RG Gate input resistance VDD=15 V, ID = 13 A VGS =4.5 V (see Figure 8) f=1 MHz gate DC bias = 0 test signal level = 20 mV open drain 1. Pulsed: pulse duration=300 µs, duty cycle 1.5% 4/12 Max. Dynamic Total gate charge Gate-source charge Gate-drain charge Qgs Typ. VDS = Max rating, IDSS Table 6. Min. 0.5 9 3.7 3 12 nC nC nC 1.5 2.5 Ω STL50NH3LL Electrical characteristics Table 7. Symbol td(on) tr td(off) tf Table 8. Symbol Switching times Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. 15 32 18 8.5 VDD=15 V, ID= 6.5 A, RG=4.7 Ω, VGS=4.5 V (see Figure 14) Unit ns ns ns ns Source drain diode Max Unit Source-drain current 13 A ISDM(1) Source-drain current (pulsed) 52 A VSD(2) Forward on voltage 1.3 V ISD trr Qrr IRRM Parameter Reverse recovery time Reverse recovery charge Reverse recovery current Test conditions Min. Typ. ISD=13 A, VGS=0 ISD=13 A, di/dt = 100 A/µs, VDD=20 V, Tj=150 °C (see Figure 16) 24 17.4 1.45 ns nC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300 µs, duty cycle 1.5% 5/12 Electrical characteristics STL50NH3LL 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Transconductance Figure 7. Static drain-source on resistance 6/12 STL50NH3LL Figure 8. Electrical characteristics Gate charge vs. gate-source voltage Figure 9. Capacitance variations Figure 10. Normalized gate threshold voltage vs. temperature Figure 11. Normalized on resistance vs. temperature Figure 12. Source-drain diode forward characteristics Figure 13. Normalized BVDSS vs. temperature 7/12 Test circuit 3 STL50NH3LL Test circuit Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test switching and diode recovery times circuit Figure 18. Unclamped inductive waveform 8/12 Figure 19. Switching time waveform STL50NH3LL 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/12 Package mechanical data STL50NH3LL PowerFLAT™ (6x5) MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. 0.80 0.83 0.93 0.031 0.032 0.036 A1 0.02 0.05 0.0007 0.0019 A3 0.20 A b 0.35 D 0.013 4.20 0.015 0.187 4.25 0.163 0.165 E 6.00 0.236 E1 5.75 0.226 E2 3.43 E4 2.58 L 3.48 3.53 2.63 2.68 0.135 1.27 0.70 0.80 0.018 0.196 4.75 4.15 e 10/12 0.47 5.00 D1 D2 0.40 0.007 0.167 0.137 0.139 0.103 0.105 0.050 0.90 0.027 0.031 0.035 STL50NH3LL 5 Revision history Revision history Table 9. Revision history Date Revision Changes 21-Jul-2005 1 First Release 14-Apr-2005 2 Final version 20-Jun-2005 3 Updated mechanical data 22-Jun-2005 4 New Rg value on Table 7 30-Sep-2005 5 Inserted ecopack indication 04-Jan-2006 6 New footprint 30-Mar-2006 7 New template 27-Jul-2006 8 Updated Figure 2 06-Sep-2006 9 New template, no content change 11-Dec-2007 10 Updated EAS value on Table 4: Avalanche data 11/12 STL50NH3LL Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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