STMICROELECTRONICS STL8NH3LL_06

STL8NH3LL
N-channel 30V - 0.012Ω - 8A - PowerFLAT™
Ultra low gate charge STripFET™ Power MOSFET
General features
Type
VDSS
RDS(on)
ID
STL8NH3LL
30V
<0.015Ω
8A (1)
■
Improved die-to-footprint ratio
■
Very low profile package (1mm max)
■
Very low thermal resistance
PowerFLAT™(3.3x3.3)
■
Very low gate charge
(Chip Scale Package)
■
Low threshold device
■
In compliance with the 2002/95/EC Europen
directive
Description
This application specific Power MOSFET is the
latest generation of STMicroelectronics unique
“STripFET™” technology. The resulting transistor
is optimized for low on-resistance and minimal
gate charge. The Chip-scaled PowerFLAT™
package allows a significant board space saving,
still boosting the performance.
Internal schematic diagram
Applications
■
Switching application
TOP VIEW
Order codes
Sales Type
Marking
Package
Packaging
STL8NH3LL
8NH3L
PowerFLAT™ (3.3 x 3.3)
Tape & reel
March 2006
Rev 7
1/12
www.st.com
12
Contents:
STL8NH3LL
Contents:
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
Test circuit
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
................................................ 8
STL8NH3LL
1
Electrical ratings
Electrical ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
30
V
± 18
V
VDS
Drain-Source Voltage (V GS = 0)
VGS
Gate-Source Voltage
ID(1)
Drain Current (continuous) at T C = 25°C
8
A
ID (1)
Drain Current (continuous) at T C=100°C
5
A
IDM
(2)
Drain Current (pulsed)
32
A
PTOT(3)
Total Dissipation at T C = 25°C
50
W
PTOT(1)
Total Dissipation at T C = 25°C
2
W
0.4
W/°C
-55 to 150
°C
Value
Unit
Derating Factor
TJ
Operating Junction Temperature
Storage Temperature
Tstg
1. The value is rated according Rthj-pcb
2. Pulse width limited by safe operating area.
3. The vaule is rated according Rthj-c
Table 2.
Thermal resistance
Symbol
Rthj-case
Parameter
Thermal resistance junction-case (Drain)
2.5
°C/W
Rthj-pcb
(1)
Thermal resistance junction-pcb
42.8
°C/W
Rthj-pcb
(2)
Thermal resistance junction-pcb
63.5
°C/W
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10sec
2. Steady state
3/12
Electrical characteristics
2
STL8NH3LL
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 3.
Symbol
On/off states
Parameter
Test Condictions
V(BR)DSS
Drain-Source Breakdown
Voltage
IDSS
Zero Gate Voltage Drain
Current (VGS = 0)
IGSS
Gate Body Leakage Current
VGS = ±18V
(VDS = 0)
ID = 250µA, VGS= 0
VDS= V GS, ID = 250µA
RDS(on)
Static Drain-Source On
Resistance
VGS= 10V, ID= 4A
VGS= 4.5V, ID= 4A
Max.
30
Unit
V
1
10
µA
µA
±100
nA
2.5
V
0.012
0.0135
0.015
0.017
Ω
Ω
Typ.
Max.
Unit
VDS = MaxRating @125°C
Gate Threshold Voltage
1
Dynamic
Symbol
Parameter
gfs (1)
Forward Transconductance
VDS =15V, ID = 4A
30
S
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS =25V, f=1 MHz, VGS=0
965
285
38
pF
pF
pF
Ciss
Coss
Crss
Qg
Qgd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
RG
Gate Input Resistance
Qgs
Test Condictions
Min.
VDD=15V, ID = 8A
VGS =4.5V
(see Figure 7)
f=1 MHz Gate DC Bias = 0
Test Signal Level = 20mV
Open Drain
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
4/12
Typ.
VDS = Max Rating,
VGS(th)
Table 4.
Min.
0.5
9
3.7
3
12
nC
nC
nC
1.5
2.5
Ω
STL8NH3LL
Electrical characteristics
Table 5.
Symbol
td(on)
tr
td(off)
tf
Table 6.
Symbol
Switching times
Parameter
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Test Condictions
Min.
Typ.
Max.
15
32
18
8.5
VDD =15V, ID= 4A,
RG=4.7Ω, VGS=4.5V
(see Figure 13)
Unit
ns
ns
ns
ns
Source drain diode
Max
Unit
Source-drain Current
8
A
ISDM(1)
Source-drain Current (pulsed)
32
A
VSD(2)
Forward on Voltage
1.3
V
ISD
trr
Qrr
IRRM
Parameter
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Test Condictions
Min
Typ.
ISD=8A, V GS=0
ISD=8A,
di/dt = 100A/µs,
VDD=20V, Tj=150°C
(see Figure 15)
24
17.4
1.45
ns
nC
A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
5/12
Electrical characteristics
STL8NH3LL
2.1
Electrical characteristics (curves)
Figure 1.
Safe operating area
Figure 2.
Thermal impedance
Figure 3.
Output characterisics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
6/12
STL8NH3LL
Electrical characteristics
Figure 7.
Gate charge vs gate-source voltage Figure 8.
Figure 9.
Normalized gate threshold voltage
vs temperature
Figure 11. Source-drain diode forward
characteristics
Capacitance variations
Figure 10. Normalized on resistance vs
temperature
Figure 12. Normalized BVDSS vs temperature
7/12
Test circuit
3
STL8NH3LL
Test circuit
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
Figure 17. Unclamped inductive waveform
8/12
Figure 18. Switching time waveform
STL8NH3LL
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
9/12
Package mechanical data
STL8NH3LL
PowerFLAT™ (3.3 x 3.3) MECHANICAL DATA
DIM.
mm.
TYP
MAX.
MIN.
TYP.
MAX.
0.80
0.90
1.00
0.031
0.035
0.039
A1
0.02
0.05
0.0007
0.0019
A3
0.20
A
b
0.23
0.30
0.0007
0.38
0.009
0.011
C
0.328
0.012
C1
0.12
0.004
D
3.30
D2
2.50
E
E2
F
10/12
inch
MIN.
2.65
0.13
2.75
0.098
3.30
1.25
1.40
1.325
0.015
0.104
0.108
0.13
1.50
0.049
0.055
0.052
F1
0.975
0.038
G
0.850
0.033
G1
0.250
0.009
0.059
STL8NH3LL
5
Revision history
Revision history
Table 7.
Revision history
Date
Revision
Changes
21-Jul-2004
1
First Release
05-Oct-2004
2
Values Changed
19-Oct-2004
3
New value inserted
22-Nov-2004
4
Document updated
21-Feb-2005
5
Final version
18-Apr-2005
6
Modified Figure 3, Figure 5., Figure 8.,Figure 9.
14-Mar-2006
7
New template
11/12
STL8NH3LL
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