STMICROELECTRONICS STL55NH3LL

STL55NH3LL
N-channel 30 V, 0.0079 Ω, 15 A, PowerFLAT™ (6x5)
ultra low gate charge STripFET™ Power MOSFET
Features
Type
VDSS
RDS(on)
max
ID
STL55NH3LL
30 V
< 0.0088 Ω
15 A
■
Improved die-to-footprint ratio
■
Very low profile package (1mm max)
■
Very low thermal resistance
■
Very low gate charge
■
Low threshold device
PowerFLAT™(6x5)
Application
■
Switching applications
Figure 1.
Internal schematic diagram
Description
This application specific Power MOSFET is the
latest generation of STMicroelectronics unique
“STripFET™” technology. The resulting transistor
is optimized for low on-resistance and minimal
gate charge. The chip-scaled PowerFLAT™
package allows a significant board space saving,
still boosting the performance.
Table 1.
Device summary
Order code
Marking
Package
Packaging
STL55NH3LL
L55NH3LL
PowerFLAT™ (6x5)
Tape and reel
May 2008
Rev 3
1/14
www.st.com
14
Contents
STL55NH3LL
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/14
.............................................. 9
STL55NH3LL
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
VDS
Parameter
Drain-source voltage (VGS = 0)
Value
Unit
30
V
VGS(1)
Gate-source voltage
± 16
V
VGS(2)
Gate-source voltage
± 18
V
ID(3)
Drain current (continuous) at TC = 25 °C
55
A
ID(3)
Drain current (continuous) at TC=100 °C
36
A
(4)
Drain current (pulsed)
60
A
(5)
Drain current (continuous) at TC = 25 °C
15
A
ID (5)
Drain current (continuous) at TC=100 °C
9.4
A
IDM
ID
PTOT
(5)
Total dissipation at TC = 25 °C
4
W
PTOT
(3)
Total dissipation at TC = 25 °C
60
W
0.03
W/°C
-55 to 150
°C
Value
Unit
Thermal resistance junction-case (drain)
2.08
°C/W
Thermal resistance junction-ambient
31.3
°C/W
Value
Unit
Derating factor
TJ
Operating junction temperature
Storage temperature
Tstg
1. Continuous mode
2. Guaranteed for test time ≤ 15 ms
3. The value is rated according Rthj-c
4. Pulse width limited by safe operating area
5. The value is rated according Rthj-pcb
Table 3.
Thermal resistance
Symbol
Rthj-case
Rthj-pcb
(1)
Parameter
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
Table 4.
Symbol
Avalanche data
Parameter
IAV
Not-repetitive avalanche current
(pulse width limited by Tj Max)
7.5
A
EAS
Single pulse avalanche energy
(starting Tj = 25 °C, ID=IAV, VDD = 24 V, L=6 mH)
150
mJ
3/14
Electrical characteristics
2
STL55NH3LL
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 5.
Symbol
V(BR)DSS
On/off states
Parameter
Drain-source breakdown
voltage
Test conditions
ID = 250 µA, VGS= 0
Min.
IDSS
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±16 V
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
Ciss
Coss
Crss
Qg
Qgs
Qgd
Qgs1
Qgs2
RG
4/14
1
10
µA
µA
±100
nA
2.5
V
0.0079
0.0079
0.009
0.0088
0.0088
0.0115
Ω
Ω
Ω
Typ.
Max.
Unit
1
VGS= 10 V, ID= 7.5 A
VGS= 8 V, ID= 7.5 A
Unit
V
VDS = max rating @125
°C
VGS= 4.5 V, ID= 7.5 A
Symbol
Max.
30
VDS = max rating,
Zero gate voltage drain
current (VGS = 0)
Table 6.
Typ.
Dynamic
Parameter
Test conditions
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25 V, f=1 MHz,
VGS=0
Total gate charge
Gate-source charge
Gate-drain charge
Pre Vth gate-to-source
charge
Post Vth gate-to-source
charge
Gate input resistance
Min.
965
285
38
VDD=15 V, ID = 15 A
9
3.7
3
VGS =4.5 V
(see Figure 16)
VDD=15 V, ID = 15 A
VGS =4.5 V
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
0.5
pF
pF
pF
12
nC
nC
nC
2.5
nC
1.2
nC
1.5
2.5
Ω
STL55NH3LL
Electrical characteristics
Table 7.
Symbol
td(on)
tr
td(off)
tf
Table 8.
Symbol
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
Min.
Typ.
Max.
15
32
18
8.5
VDD=15 V, ID= 7.5 A,
RG=4.7 Ω, VGS=4.5 V
(see Figure 18)
Unit
ns
ns
ns
ns
Source drain diode
Max
Unit
Source-drain current
15
A
ISDM(1)
Source-drain current (pulsed)
60
A
VSD(2)
Forward on voltage
1.3
V
ISD
trr
Qrr
IRRM
Parameter
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
Min
Typ.
ISD=15 A, VGS=0
ISD=15 A,
di/dt = 100 A/µs,
VDD=20 V, Tj=150 °C
(see Figure 17)
24
17.4
1.45
ns
nC
A
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration=300 µs, duty cycle 1.5%
5/14
Electrical characteristics
STL55NH3LL
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 4.
Output characteristics
Figure 5.
Transfer characteristics
Figure 6.
Normalized BVDSS vs temperature
Figure 7.
Static drain-source on resistance
6/14
STL55NH3LL
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
Capacitance variations
Figure 10. Normalized gate threshold voltage
vs temperature
Figure 11. Normalized on resistance vs
temperature
Figure 12. Source-drain diode forward
characteristics
Figure 13. Avalanche energy vs starting tj
7/14
Electrical characteristics
STL55NH3LL
Figure 14. Allowable Iav vs time in avalanche
The previous curve gives the single pulse safe operating area for unclamped inductive
loads, under the following conditions:
PD(AVE) =0.5*(1.3*BVDSS *IAV)
EAS(AR) =PD(AVE) *tAV
Where:
IAV is the allowable current in avalanche
PD(AVE) is the average power dissipation in avalanche (single pulse)
tAV is the time in avalanche
8/14
STL55NH3LL
3
Test circuits
Test circuits
Figure 15. Switching times test circuit for
resistive load
Figure 16. Gate charge test circuit
Figure 17. Test circuit for inductive load
Figure 18. Unclamped inductive load test
switching and diode recovery times
circuit
Figure 19. Unclamped inductive waveform
Figure 20. Switching time waveform
9/14
Test circuits
STL55NH3LL
Figure 21. Gate charge waveform
Id
Vds
Vgs
Vgs(th)
Qgs1 Qgs2
10/14
Qgd
STL55NH3LL
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
11/14
Package mechanical data
STL55NH3LL
PowerFLAT™ (6x5) MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
MIN.
TYP.
MAX.
0.80
0.83
0.93
0.031
0.032
0.036
A1
0.02
0.05
0.0007
0.0019
A3
0.20
A
b
0.35
0.47
0.013
0.015
D
5.00
0.196
D1
4.75
0.187
D2
4.15
E
4.20
4.25
5.75
3.48
3.53
E4
2.58
2.63
2.68
0.135
1.27
0.70
0.80
0.167
0.226
3.43
e
0.165
0.018
0.236
E2
L
0.163
6.00
E1
12/14
0.40
0.007
0.137
0.139
0.103
0.105
0.050
0.90
0.027
0.031
0.035
STL55NH3LL
5
Revision history
Revision history
Table 9.
Document revision history
Date
Revision
Changes
18-Mar-2008
1
First release.
05-May-2008
2
Corrected Table 1: Device summary
07-May-2008
3
Update Figure 6: Normalized BVDSS vs temperature
13/14
STL55NH3LL
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