SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258J – DECEMBER 1995 – REVISED FEBRUARY 2002 D D SN54AHC138 . . . J OR W PACKAGE SN74AHC138 . . . D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) A B C G2A G2B G1 Y7 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 SN54AHC138 . . . FK PACKAGE (TOP VIEW) description The ’AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. B A NC VCC Y0 D Operating Range 2-V to 5.5-V VCC Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) C G2A NC G2B G1 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 Y1 Y2 NC Y3 Y4 Y7 GND NC Y6 Y5 D D NC – No internal connection The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258J – DECEMBER 1995 – REVISED FEBRUARY 2002 ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA PDIP – N Tube SN74AHC138N Tube SN74AHC138D Tape and reel SN74AHC138DR SOP – NS Tape and reel SN74AHC138NSR AHC138 SSOP – DB Tape and reel SN74AHC138DBR HA138 TSSOP – PW Tape and reel SN74AHC138PWR HA138 TVSOP – DGV Tape and reel SN74AHC138DGVR HA138 CDIP – J Tube SNJ54AHC138J SNJ54AHC138J CFP – W Tube SNJ54AHC138W SNJ54AHC138W LCCC – FK Tube SNJ54AHC138FK SNJ54AHC138FK SOIC – D –40°C to 85°C –55°C to 125°C TOP-SIDE MARKING SN74AHC138N AHC138 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE ENABLE INPUTS 2 SELECT INPUTS OUTPUTS G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X H X X X X H H H H H H H H X X H X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258J – DECEMBER 1995 – REVISED FEBRUARY 2002 logic diagram (positive logic) 15 A Y0 1 14 Y1 13 Select Inputs B Y2 2 12 11 3 Y3 Data Outputs Y4 C 10 9 G2A Enable Inputs G2B G1 4 7 5 Y5 Y6 Y7 6 Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258J – DECEMBER 1995 – REVISED FEBRUARY 2002 recommended operating conditions (see Note 3) SN54AHC138 VCC Supply voltage VIH VCC = 2 V VCC = 3 V High-level input voltage Low-level input voltage VI VO 2 5.5 Output voltage ∆t/∆v 5.5 2.1 V V 0.5 0.9 0.9 1.65 1.65 V 0 5.5 0 5.5 V 0 VCC –50 0 VCC –50 mA VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V Input transition rise or fall rate 2 UNIT 1.5 3.85 VCC = 2 V VCC = 3.3 V ± 0.3 V Low-level output current MAX 2.1 VCC = 5 V ± 0.5 V VCC = 2 V IOL MIN 3.85 VCC = 3 V VCC = 5.5 V High-level output current SN74AHC138 0.5 Input voltage IOH MAX 1.5 VCC = 5.5 V VCC = 2 V VIL MIN VCC = 5 V ± 0.5 V –4 –4 –8 –8 50 50 4 4 8 8 100 100 20 20 V mA mA mA ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER MIN TA = 25°C TYP MAX 2V 1.9 2 1.9 1.9 3V 2.9 3 2.9 2.9 4.5 V 4.4 4.5 4.4 4.4 IOH = –4 mA 3V 2.58 2.48 2.48 IOH = –8 mA 4.5 V 3.94 3.8 3.8 TEST CONDITIONS IOH = –50 mA VOH IOL = 50 mA VOL IOL = 4 mA II ICC Ci IOL = 8 mA VI = 5.5 V or GND VI = VCC or GND, VI = VCC or GND IO = 0 VCC MIN MAX SN74AHC138 MIN MAX UNIT V 2V 0.1 0.1 0.1 3V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 0 V to 5.5 V ±0.1 ±1* ±1 mA 4 40 40 mA 10 pF 5.5 V 5V 2 10 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. 4 SN54AHC138 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258J – DECEMBER 1995 – REVISED FEBRUARY 2002 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A B A, B, C Any Y CL = 15 pF tPLH tPHL G1 Any Y CL = 15 pF tPLH tPHL G2A G2B G2A, Any Y CL = 15 pF tPLH tPHL A B A, B, C Any Y CL = 50 pF tPLH tPHL G1 Any Y CL = 50 pF tPLH tPHL G2A G2B G2A, Any Y CL = 50 pF MIN TA = 25°C TYP MAX SN54AHC138 SN74AHC138 MIN MAX MIN MAX 8.2* 11.4* 1* 13* 1 13 8.2* 11.4* 1* 13* 1 13 8.1* 12.8* 1* 15* 1 15 8.1* 12.8* 1* 15* 1 15 8.2* 11.4* 1* 13.5* 1 13.5 8.2* 11.4* 1* 13.5* 1 13.5 10 15.8 1 18 1 18 10 15.8 1 18 1 18 10.6 16.3 1 18.5 1 18.5 10.6 16.3 1 18.5 1 18.5 10.7 14.9 1 17 1 17 10.7 14.9 1 17 1 17 UNIT ns ns ns ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE tPLH tPHL A B A, B, C Any Y CL = 15 pF tPLH tPHL G1 Any Y CL = 15 pF tPLH tPHL G2A G2B G2A, Any Y CL = 15 pF tPLH tPHL A B A, B, C Any Y CL = 50 pF tPLH tPHL G1 Any Y CL = 50 pF tPLH tPHL G2A G2B G2A, Any Y CL = 50 pF MIN TA = 25°C TYP MAX SN54AHC138 SN74AHC138 MIN MAX MIN MAX 5.7* 8.1* 1* 9.5* 1 9.5 5.7* 8.1* 1* 9.5* 1 9.5 5.6* 8.1* 1* 9.5* 1 9.5 5.6* 8.1* 1* 9.5* 1 9.5 5.8* 8.1* 1* 9.5* 1 9.5 5.8* 8.1* 1* 9.5* 1 9.5 7.2 10.1 1 11.5 1 11.5 7.2 10.1 1 11.5 1 11.5 7.1 10.1 1 11.5 1 11.5 7.1 10.1 1 11.5 1 11.5 7.3 10.1 1 11.5 1 11.5 7.3 10.1 1 11.5 1 11.5 UNIT ns ns ns ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP 13 UNIT pF 5 SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258J – DECEMBER 1995 – REVISED FEBRUARY 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL VCC Output Control Output Waveform 1 S1 at VCC (see Note B) 50% VCC 0V tPZL VOH 50% VCC VOL tPLZ ≈VCC 50% VCC tPZH tPLH 50% VCC 50% VCC Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258J – DECEMBER 1995 – REVISED FEBRUARY 2002 APPLICATION INFORMATION SN74AHC138 BIN/OCT 1 2 3 VCC 0 1 1 2 2 4 6 3 & 4 4 EN 5 5 6 7 15 14 13 12 11 10 9 7 0 1 2 3 4 5 6 7 SN74AHC138 BIN/OCT 1 A0 2 A1 3 A2 1 2 2 4 6 A3 0 1 3 & 4 4 A4 EN 5 5 6 7 15 14 13 12 11 10 9 7 8 9 10 11 12 13 14 15 SN74AHC138 BIN/OCT 1 2 3 6 0 1 1 2 2 4 3 & 4 4 5 EN 5 6 7 15 14 13 12 11 10 9 7 16 17 18 19 20 21 22 23 Figure 2. 24-Bit Decoding Scheme POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS SCLS258J – DECEMBER 1995 – REVISED FEBRUARY 2002 APPLICATION INFORMATION SN74AHC138 BIN/OCT 1 A0 2 A1 3 A2 1 1 2 2 4 6 VCC 0 3 & 4 4 A3 EN 5 A4 5 6 7 15 14 13 12 11 10 9 7 0 1 2 3 4 5 6 7 SN74AHC138 BIN/OCT 1 2 3 0 1 1 2 2 4 6 3 & 4 4 EN 5 5 6 7 15 14 13 12 11 10 9 7 8 9 10 11 12 13 14 15 SN74AHC138 BIN/OCT 1 2 3 0 1 1 2 2 4 6 3 & 4 4 EN 5 5 6 7 15 14 13 12 11 10 9 7 16 17 18 19 20 21 22 23 SN74AHC138 BIN/OCT 1 2 3 6 0 1 1 2 2 4 3 & 4 4 5 EN 5 6 7 Figure 3. 32-Bit Decoding Scheme 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 14 13 12 11 10 9 7 24 25 26 27 28 29 30 31 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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