SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
D Qualified for Automotive Applications
D EPIC (Enhanced-Performance Implanted
D OR PW PACKAGE
(TOP VIEW)
CMOS) Process
A
B
C
G2A
G2B
G1
Y7
GND
D Inputs Are TTL-Voltage Compatible
D Designed Specifically for High-Speed
D
D
D
Memory Decoders and Data-Transmission
Systems
Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
description
The SN74AHCT138Q 3-line to 8-line decoder/demultiplexer is designed to be used in high-performance
memory-decoding and data-routing applications that require very short propagation-delay times. In
high-performance memory systems, this decoder can be used to minimize the effects of system decoding.
When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and
the enable time of the memory usually are less than the typical access time of the memory. This means that
the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
ORDERING INFORMATION{
PACKAGE‡
TA
−40°C to 125°C
SOIC − D
Tape and reel
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SN74AHCT138QDRQ1
AHCT138Q
TSSOP − PW
Tape and reel
SN74AHCT138QPWRQ1
HB138Q
† For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
Copyright 2008, Texas Instruments Incorporated
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
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SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
FUNCTION TABLE
ENABLE INPUTS
G1
G2A
X
X
SELECT INPUTS
G2B
C
B
H
X
X
X
X
H
X
X
A
OUTPUTS
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
H
H
H
H
H
H
H
H
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
logic symbols (alternatives)†
A
B
C
G1
1
2
3
6
4
G2A
5
G2B
BIN/OCT
0
1
2
1
4
2
3
&
4
EN
5
6
7
15
14
13
12
11
10
9
7
Y0
Y1
Y2
A
B
C
1
G1
Y5
G2A
Y6
G2B
3
6
4
5
Y7
POST OFFICE BOX 655303
0
G
7
2
1
2
&
3
4
5
6
7
† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
0
2
Y3
Y4
DMUX
0
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15
14
13
12
11
10
9
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
logic diagram (positive logic)
15
Y0
A
1
14
Y1
13
Select
Inputs
B
Y2
2
12
Y3
11
3
Data
Outputs
Y4
C
10
Y5
9
Y6
4
G2A
Enable
Inputs
G2B
7
5
Y7
6
G1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
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SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
VO
IOH
Output voltage
IOL
∆t/∆v
MIN
MAX
4.5
5.5
High-level input voltage
2
UNIT
V
V
0.8
V
0
5.5
V
0
V
High-level output current
VCC
−8
Low-level output current
8
mA
20
ns/V
Input transition rise or fall rate
mA
TA
Operating free-air temperature
−40
125
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VOH
IOH = −50 mA
IOH = −8 mA
4.5 V
VOL
IOL = 50 mA
IOL = 8 mA
4.5 V
II
ICC
VI = 5.5 V or GND
VI = VCC or GND,
∆ICC†
One input at 3.4 V,
Other inputs at VCC or GND
MIN
TA = 25°C
TYP
MAX
4.4
4.5
MAX
UNIT
4.4
3.94
V
3.8
0.1
0.1
0.36
0.5
V
±0.1
±1
mA
5.5 V
4
40
mA
5.5 V
1.35
1.5
mA
0 V to 5.5 V
IO = 0
MIN
Ci
VI = VCC or GND
5V
2
10
† This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
4
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tPLH
tPHL
A, B, C
Any Y
CL = 15 pF
tPLH
tPHL
G1
Any Y
CL = 15 pF
tPLH
tPHL
G2A, G2B
Any Y
CL = 15 pF
tPLH
tPHL
A, B, C
Any Y
CL = 50 pF
tPLH
tPHL
G1
Any Y
CL = 50 pF
tPLH
tPHL
G2A, G2B
Any Y
CL = 50 pF
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MIN
TA = 25°C
TYP
MAX
MIN
MAX
7.6
10.4
1
12
7.6
10.4
1
12
6.6
9.1
1
10.5
6.6
9.1
1
10.5
7
9.6
1
11
7
9.6
1
11
8.1
11.4
1
13
8.1
11.4
1
13
7.1
10.1
1
11.5
7.1
10.1
1
11.5
7.5
10.6
1
12
7.5
10.6
1
12
UNIT
ns
ns
ns
ns
ns
ns
SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
TYP
f = 1 MHz
UNIT
14
pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
RL = 1 kΩ
From Output
Under Test
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
≈VCC
50% VCC
tPZH
tPLH
50% VCC
3V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
APPLICATION INFORMATION
SN74AHCT138Q
BIN/OCT
1
2
3
VCC
0
1
1
2
2
4
6
3
&
4
4
EN
5
5
6
7
15
14
13
12
11
10
9
7
0
1
2
3
4
5
6
7
SN74AHCT138Q
BIN/OCT
1
A0
2
A1
3
A2
1
2
2
4
6
A3
0
1
3
&
4
4
A4
EN
5
5
6
7
15
14
13
12
11
10
9
7
8
9
10
11
12
13
14
15
SN74AHCT138Q
BIN/OCT
1
2
3
6
0
1
1
2
2
4
3
&
4
4
5
EN
5
6
7
Figure 2. 24-Bit Decoding Scheme
6
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15
14
13
12
11
10
9
7
16
17
18
19
20
21
22
23
SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008
APPLICATION INFORMATION
SN74AHCT138Q
BIN/OCT
1
A0
2
A1
3
A2
1
1
2
2
4
6
VCC
0
3
&
4
4
A3
EN
5
A4
5
6
7
15
14
13
12
11
10
9
7
0
1
2
3
4
5
6
7
SN74AHCT138Q
BIN/OCT
1
2
3
0
1
1
2
2
4
6
3
&
4
4
EN
5
5
6
7
15
14
13
12
11
10
9
7
8
9
10
11
12
13
14
15
SN74AHCT138Q
BIN/OCT
1
2
3
0
1
1
2
2
4
6
3
&
4
4
EN
5
5
6
7
15
14
13
12
11
10
9
7
16
17
18
19
20
21
22
23
SN74AHCT138Q
BIN/OCT
1
2
3
6
0
1
1
2
2
4
3
&
4
4
5
EN
5
6
7
15
14
13
12
11
10
9
7
24
25
26
27
28
29
30
31
Figure 3. 32-Bit Decoding Scheme
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Mar-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CAHCT138QPWRG4Q1
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT138QDRG4Q1
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT138QDRQ1
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AHCT138QPWRQ1
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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