54ACT11138, 74ACT11138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A – D3266, JANUARY 1989 – REVISED APRIL 1993
•
•
•
•
•
•
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
650-mA Typical Latch-Up Immunity
at 125°C
Package Options Include Plastic
Small-Outline Packages, Plastic Thin
Shrink Small-Outline Packages, Ceramic
Chip Carriers, and Standard Plastic and
Ceramic 300-mil DIPs
54ACT11138 . . . J PACKAGE
74ACT11138 . . . D, N, OR PW PACKAGE
(TOP VIEW)
Y1
Y2
Y3
GND
Y4
Y5
Y6
Y7
t
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
Y0
A
B
C
VCC
G1
G2A
G2B
54ACT11138 . . . FK PACKAGE
(TOP VIEW)
A
Y0
NC
Y1
Y2
description
1
B
C
NC
VCC
G1
•
4
3 2 1 20 19
18
5
17
6
16
G2A
G2B
NC
Y7
Y6
Y3
GND
NC
Y4
Y5
The ′ACT11138 circuit is designed to be used in
15
7
high-performance memory-decoding or data14
8
9 10 11 12 13
routing applications requiring very short
propagation delay times. In high-performance
memory systems, this decoder can be used to
minimize the effects of system decoding. When
NC – No internal connection
employed with high-speed memories utilizing a
fast enable circuit, the delay times of this decoder
and the enable time of the memory are usually less than the typical access time of the memory. This means
that the effective system delay introduced by the decoder is negligible.
The conditions at the binary select inputs and the three enable inputs select one of eight input lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
The 54ACT11138 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
74ACT11138 is characterized for operation from – 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–1
54ACT11138, 74ACT11138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A – D3266, JANUARY 1989 – REVISED APRIL 1993
logic symbols (alternatives)†
DMUX
BIN/OCT
A
B
C
15
14
13
1
0
2
1
4
2
3
G1
G2A
G2B
11
&
4
10
9
5
EN
6
7
16
1
2
3
5
6
7
8
Y0
Y1
Y2
A
B
C
15
0
0
14
13
G
0
7
2
Y3
Y4
Y5
Y6
1
2
3
G1
G2A
G2B
11
&
4
10
5
9
6
Y7
7
† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram (positive logic)
16
A
15
1
Y0
Y1
2
Select
Inputs
B
Y2
14
3
5
C
13
6
7
Enable
Inputs
G2A
G2B
G1
10
8
9
11
Pin numbers shown are for the D, J, and N packages.
2–2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Y3
Data
Outputs
Y4
Y5
Y6
Y7
16
1
2
3
5
6
7
8
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
54ACT11138, 74ACT11138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A – D3266, JANUARY 1989 – REVISED APRIL 1993
FUNCTION TABLE
ENABLE
INPUTS
SELECT
INPUTS
OUTPUTS
G1
G2A
G2B
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
recommended operating conditions
54ACT11138
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
Dt /Dv
Low-level output current
TA
Operating free-air temperature
High-level input voltage
74ACT11138
2
2
0.8
Input transition rise or fall rate
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• DALLAS, TEXAS 75265
UNIT
V
V
0.8
V
VCC
VCC
V
– 24
– 24
mA
24
24
mA
VCC
VCC
0
0
V
0
10
0
10
ns/ V
– 55
125
– 40
85
°C
2–3
54ACT11138, 74ACT11138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A – D3266, JANUARY 1989 – REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
4.5 V
IOH = – 50 mA
VOH
IOH = – 24 mA
IOH = – 50 mA{
IOH = – 75 mA{
TA = 25°C
TYP
MAX
54ACT11138
74ACT11138
MIN
MIN
MAX
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
5.5 V
IOL = 24 mA
IOL = 50 mA{
IOL = 75 mA{
MAX
UNIT
V
3.85
5.5 V
IOL = 50 mA
VOL
MIN
3.85
4.5 V
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
5.5 V
0.1
V
1.65
5.5 V
1.65
II
ICC
VI = VCC or GND
VI = VCC or GND,
5.5 V
± 0.1
±1
±1
mA
IO = 0
5.5 V
4
80
40
mA
DICC}
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.9
1
1
mA
Ci
VI = VCC or GND
5V
3.5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
switching characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A B
A,
B, C
Any Y
tPLH
tPHL
G1
Y
tPLH
tPHL
G2A G2B
G2A,
Any Y
MIN
TA = 25°C
TYP
MAX
54ACT11138
74ACT11138
MIN
MAX
MIN
MAX
1.5
6.1
8.9
1.5
10.5
1.5
9.8
1.5
6
8.7
1.5
10.3
1.5
9.7
1.5
5.5
8
1.5
9.4
1.5
8.9
1.5
6
7.9
1.5
9.5
1.5
8.9
1.5
6.4
8.3
1.5
9.9
1.5
9.3
1.5
6
8.8
1.5
10.5
1.5
9.8
UNIT
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
2–4
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
UNIT
88
pF
54ACT11138, 74ACT11138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A – D3266, JANUARY 1989 – REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
3V
Input
(see Note B)
From Output
Under Test
CL = 50 pF
(see Note A)
1.5 V
1.5 V
0V
tPHL
500 Ω
tPLH
50% VCC
Output
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
LOAD CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2–5
54ACT11138, 74ACT11138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCAS050A – D3266, JANUARY 1989 – REVISED APRIL 1993
2–6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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