PROCESS CP318V Small Signal Transistor Central TM Semiconductor Corp. NPN - High Voltage Transistor Chip PROCESS DETAILS Process EPITAXIAL PLANAR Die Size 26 x 26 MILS Die Thickness 7.1 MILS ± 0.6 MILS Base Bonding Pad Area 5.5 x 5.5 MILS Emitter Bonding Pad Area 5.5 x 5.5 MILS Top Side Metalization Al Si - 17,000Å Back Side Metalization Au - 12,000Å GEOMETRY GROSS DIE PER 5 INCH WAFER 25,536 PRINCIPAL DEVICE TYPES MPS455 BACKSIDE COLLECTOR 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com R1 (28 -March 2005) Central TM Semiconductor Corp. 145 Adams Avenue Hauppauge, NY 11788 USA Tel: (631) 435-1110 Fax: (631) 435-1824 www.centralsemi.com PROCESS CP318V Typical Electrical Characteristics R1 (28 -March 2005)