CENTRAL CP710

PROCESS
CP710
Central
Small Signal Transistor
TM
Semiconductor Corp.
PNP - High Voltage Transistor Chip
PROCESS DETAILS
Process
EPITAXIAL PLANAR
Die Size
26 x 26 MILS
Die Thickness
9.0 MILS
Base Bonding Pad Area
6.1 x 4.9 MILS
Emitter Bonding Pad Area
5.2 x 5.2 MILS
Top Side Metalization
Al - 30,000Å
Back Side Metalization
Au - 18,000Å
GEOMETRY
GROSS DIE PER 4 INCH WAFER
16,880
PRINCIPAL DEVICE TYPES
CMPTA94
CXTA94
CZTA94
MPSA94
BACKSIDE COLLECTOR
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R2 (1-August 2002)
Central
Semiconductor Corp.
CP710
PROCESS
TM
Typical Electrical Characteristics
"ON" Voltage
1.4
1.2
V, Voltage (V)
1
VBE(S) @ IC/IB = 10
0.8
0.6
0.4
VCE(S) @ IC/IB = 10
0.2
T A = 25°C
0
1
10
100
1000
IC, Collector Current (mA)
145 Adams Avenue
Hauppauge, NY 11788 USA
Tel: (631) 435-1110
Fax: (631) 435-1824
www.centralsemi.com
R2 (1-August 2002)