CY24713 Set-top Box Clock Generator with VCXO Features Benefits • Integrated phase-locked loop (PLL) • High-performance PLL tailored for Set Top Box applications • Low-jitter, high-accuracy outputs • Meets critical timing requirements in complex system designs • VCXO with analog adjust • 3.3V Operation • Large ±150-ppm range, better linearity • 8-pin SOIC • Meet industry standard voltage platforms • Industry standard packaging saves on board space Part Number Outputs Input Frequency Range Output Frequencies CY24713 3 27-MHz pullable crystal input per Cypress specification 4.9152 MHz, 13.5 MHz, 27 MHz Logic Block Diagram Pin Configuration Cypress Semiconductor Corporation Document #: 38-07396 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 11, 2005 CY24713 Pin Description Name Number Description XIN 1 Reference Crystal Input VDD 2 3.3V Voltage Supply VCXO 3 Input Analog Control for VCXO VSS 4 Ground CLK_B 5 13.5-MHz Clock Output CLK_A 6 4.9152-MHz Clock Output CLK_C 7 27-MHz Clock Output 8 Reference Crystal Output [1] XOUT Absolute Maximum Conditions Parameter VDD Description Supply Voltage Temperature[2] TS Storage TJ Junction Temperature Min. Max. Unit –0.5 7.0 V –65 125 °C – 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V – 2000 V –0.5 7.0 V Electrostatic Discharge Analog Input Pullable Crystal Specifications Parameter Description FNOM Nominal crystal frequency Condition Parallel resonance, fundamental mode, AT cut Min. Typ. Max. Unit – 27 – MHz – 14 – pF – – 25 Ω CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) R3/R1 Ratio of third overtone mode ESR to fundamen- Ratio used because typical tal mode ESR R1 values are much less than the maximum spec. 3 – – DL Crystal drive level No external series resistor assumed – 0.5 2.0 mW F3SEPHI Third overtone separation from 3*FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 Fundamental mode pF Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for 10 years Document #: 38-07396 Rev. ** Page 2 of 6 CY24713 Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Min. Typ. Max. Unit 3.135 3.3 3.465 V 0 – 70 °C – – 15 pF 0.05 – 500 ms DC Electrical Characteristics Parameter Description Conditions Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V 12 24 – mA IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 – mA CIN Input Capacitance – – 7 pF IIZ Input Leakage Current – 5 – µA f∆XO VCXO pullability range ±150 – – ppm VVCXO VCXO input range 0 – VDD V IVDD Supply Current – 25 30 mA AC Electrical Characteristics (VDD = 3.3V) Parameter[3] Min. Typ. Max. Unit DC Output Duty Cycle Description Duty Cycle is defined in Figure 1 50% of VDD Conditions 45 50 55 % ER0 Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF Figure 2. 0.8 1.4 – V/ns EF1 Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF Figure 2. 0.8 1.4 – V/ns t9 Clock Jitter Peak-Peak period jitter maximum absolute jitter – 200 250 ps t10 PLL Lock Time – – 3 ms Notes: 3. Not 100% tested Document #: 38-07396 Rev. ** Page 3 of 6 CY24713 Test Circuit V DD CLK out 0.1 µF C LOAD OUTPUTS GND t3 t1 t2 CLK 50% t4 80% 50% Figure 1. Duty Cycle Definition; DC = t2/t1 CLK 20% Figure 2. Rise and Fall Time Definitions: ER = 0.6 x VDD/t3, EF = 0.6 x VDD/t4 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY24713SC 8-pin SOIC Commercial 3.3V CY24713SCT 8-pin SOIC Commercial 3.3V CY24713SXC 8-pin SOIC Commercial 3.3V CY24713SXCT 8-pin SOIC Commercial 3.3V Lead-free Document #: 38-07396 Rev. ** Page 4 of 6 CY24713 Package Diagram 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product and company names mentioned in this document may be trademarks of their respective holders. Document #: 38-07396 Rev. ** Page 5 of 6 CY24713 Document History Page Document Title: CY24713 Set-top Box Clock Generator with VCXO Document Number: 38-07396 REV. ECN No. Issue Date Orig. of Change ** 333175 See ECN RGL Document #: 38-07396 Rev. ** Description of Change New Data Sheet Page 6 of 6