CY2411 MediaClock™ MPEG Clock Generator with VCXO Features Benefits • Integrated phase-locked loop (PLL) Highest-performance PLL tailored for multimedia applications • Low-jitter, high-accuracy outputs Meets critical timing requirements in complex system designs • VCXO with analog adjust Large ± 150 ppm range, better linearity • 3.3V operation Part Number Outputs CY2411-1 1 Input Frequency Range 13.5-MHz Pullable Crystal per Cypress Specification Output Frequencies 1 copy of 54 MHz (3.3V) Pin Configuration Logic Block Diagram CY2411 8-pin SOIC 13.5 XIN OSC XOUT Q OUTPUT DIVIDER Φ VCO 54 MHz P VCXO PLL AVDD VDD AVSS XIN 1 8 XOUT AVDD VCXO 2 7 3 6 AVSS 4 5 VSS 54 MHz VDD VSS Pin Summary Pin Name Pin Number Pin Description AVDD 2 Analog Voltage Supply VDD 5 Output Voltage Supply AVSS 4 Analog Ground VSS 7 Output Ground XIN 1 Reference Crystal Input VCXO 3 Analog Control for VCXO [1] 8 Reference Crystal Output 54 MHz 6 54-MHz clock output XOUT Note: 1. Float XOUT if XIN is externally driven. Cypress Semiconductor Corporation Document #: 38-07193 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 CY2411 Absolute Maximum Conditions Parameter Description Supply Voltage VDD [2] TS Storage Temperature TJ Junction Temperature Min. Max. Unit –0.5 7.0 V –65 125 °C 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs Referred to VDD VSS – 0.3 VDD + 0.3 V Electro-Static Discharge 2000 V Recommended Operating Conditions Parameter Description Min. Typ. Max. Unit 3.15 3.3 3.45 V 70 °C 15 pF 13.5 MHz 500 ms VDD Operating Voltage TA Ambient Temperature CLOAD Max Load Capacitance fREF Reference Frequency 13.5 tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 0 13.5 Pullable Crystal Specifications Parameter Description Min. Crystal Load Capacitance CRload Typ. Max. Unit 12.4 pF C0/C1 240 ESR Equivalent Series Resistance To Operating Temperature Crystal Accuracy Crystal Accuracy TTs Stability over Temperature and Aging 35 0 + 20 50 Ω 70 °C + 20 ppm + 50 ppm DC Electrical Characteristics Parameter Description Conditions Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD = 3.3 V (source) 12 24 mA IOL Output Low Current VOL = 0.5, VDD = 3.3 V (sink) 12 24 mA CIN Input Capacitance IIZ Input Leakage Current f∆xo VCXO Pullability Range VVCXO VCXO Input Range IDD Supply Current 7 pF µA 5 –150 +150 ppm 0 AVDD V 20 mA VDD = 3.45V, Cload = 15pF 15 AC Electrical Characteristics (VDD = 3.3V) Parameter[3] Description Conditions Min. Typ. Max. Unit 55 % DC = t2/t1 Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD 45 50 ER0 Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, Cload = 15 pF (see Figure 2) 0.8 1.4 V/ns EF0 Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, Cload = 15 pF (see Figure 2) 0.8 1.4 V/ns t9 Clock Jitter Peak to Peak period jitter Document #: 38-07193 Rev. *B 200 ps Page 2 of 5 CY2411 AC Electrical Characteristics (VDD = 3.3V) Parameter[3] t10 Description Conditions Min. Typ. PLL Lock Time Max. Unit 3 ms Notes: 2. Rated for 10 years. 3. Not 100% tested. t1 t3 t2 54 MHz t4 80% 50% 54 MHz 20% Figure 2. Rise and Fall Time Definitions: ER = 0.6 × VDD/t3, EF = 0.6 × VDD/t4 Figure 1. Duty Cycle Definition; DC = t2/t1 Test Circuit AVDD CLK out 0.1 µF OUTPUTS CLOAD VDD 0.1 µF GND Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY2411SC-1 S8 8-pin SOIC Commercial 3.3V CY2411SC-1T S8 8-pin SOIC–Tape and Reel Commercial 3.3V Document #: 38-07193 Rev. *B Page 3 of 5 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2411 Pin Diagrams 8-lead (150-mil) SOIC S8 51-85066-A MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07193 Rev. *B Page 4 of 5 CY2411 Document Title: CY2411 54-MHz MPEG Clock Generator with VCXO Document Number: 38-07193 REV. ECN NO. Issue Date Orig. of Change ** 110594 11/07/01 DSG Change from Spec number: 38-00957 to 38-07193 *A 111572 04/30/02 CKN Changed title to “MPEG Clock Generator with VCXO” Added -1 data on pp. 1 and 3 *B 121875 12/14/02 RBI Power up requirements added to Operating Conditions Information Document #: 38-07193 Rev. *B Description of Change Page 5 of 5