CY7C09079V/89V/99V CY7C09179V/89V/99V CY24119 PRELIMINARY MediaClock™ 27-MHz VCXO Clock Generator Features Benefits • Low-jitter, high-accuracy output • Meets critical timing requirements in complex system designs • VCXO with analog adjust • Large ± 150 ppm range, better linearity • 3.3V operation Part Number Outputs Input Frequency Range Output Frequencies CY24119 1 27-MHz pullable crystal per Cypress specification One copy of 27-MHz (3.3V) positive slope VCXO curve CY24119-1 1 27-MHz pullable crystal per Cypress specification One copy of 27-MHz (3.3V) negative slope VCXO curve Pin Configuration Logic Block Diagram CY24119,-1 8-pin SOIC 27 XIN XOUT OSC 27 MHz VCXO AVDD VDD AVSS XIN 1 8 XOUT AVDD VCXO 2 7 3 6 AVSS 4 5 VSS 27 MHz VDD VSS Cypress Semiconductor Corporation Document #: 38-07200 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised October 8, 2003 PRELIMINARY CY24119 Pin Summary Name Pin Number Description AVDD 2 Analog Voltage Supply VDD 5 Output Voltage Supply AVSS 4 Analog Ground VSS 7 Output Ground XIN 1 Reference Crystal Input VCXO 3 Analog Control for VCXO XOUT 8 Reference Crystal Output 27 MHz 6 27-MHz Clock Output Absolute Maximum Conditions Parameter VDD Description Supply Voltage Temperature[1] TS Storage TJ Junction Temperature Min. Max. Unit –0.5 7.0 V –65 Electrostatic Discharge 125 °C 125 °C 2 kV Recommended Operating Conditions Parameter Description VDD, AVDD Operating Voltage TA Ambient Temperature CLOAD Max Load Capacitance fREF Reference Frequency tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Min. Typ. Max. Unit 3.14 3.3 3.47 V 0 10 70 °C 15 pF 30 MHz 500 ms 27 0.05 DC Electrical Characteristics Description Min. Typ. IOH Parameter Output HIGH Current Name VOH = VDD – 0.5, VDD = 3.3V (source) 12 24 IOL Output LOW Current VOL = 0.5, VDD = 3.3V (sink) 12 24 CIN Input Capacitance IIZ Input Leakage Current f∆xo VCXO Pullability Range VVCXO VCXO Input Range fVBW VCXO Input Bandwidth IDD Supply Current Max. Unit mA mA 7 pF +150 ppm µA 5 –150 0 AVDD V DC to 200 Sum of Core and Output Current kHz 13 mA Pullable Crystal Specifications Parameter Description FNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) Condition Parallel resonance, fundamental mode, AT cut Min. Typ. Max. 27 MHz 14 Fundamental mode Unit pF 25 Ω Note: 1. Not 100% tested. Document #: 38-07200 Rev. *B Page 2 of 5 PRELIMINARY CY24119 Pullable Crystal Specifications (continued) Parameter Description Condition Min. R3/R1 Ratio of third overtone mode ESR to fundamen- Ratio used because typical tal mode ESR R1 values are much less than the maximum spec. DL Crystal drive level No external series resistor assumed F3SEPHI Third overtone separation from 3.FNOM High side F3SEPLO Third overtone separation from 3.FNOM Low side C0 Crystal shunt capacitance C0/C1 Ratio of shunt to motional capacitance 180 C1 Crystal motional capacitance 14.4 Typ. Max. Unit 0.5 2.0 mW 3 300 ppm –150 ppm 7 pF 250 18 21.6 pF Typ. Max. Unit 55 AC Electrical Characteristics (VDD = 3.3V) Parameter[1] DC Name Description Min. Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD 45 50 t3 Rising Edge Slew Rate Output Clock Rise Time, 20% – 80% of VDD 0.8 1.4 t4 Falling Edge Slew Rate Output Clock Fall Time, 80% – 20% of VDD 0.8 1.4 t9 Clock Jitter Peak-to-Peak Period Jitter V/ns 100 t3 t1 t2 27 MHz % V/ns ps t4 80% 50% 27 MHz Figure 1. Duty Cycle Definition; DC = t2/t1 20% Figure 2. Rise and Fall Time Definitions AVDD CLK out 0.1 µF OUTPUTS CLOAD VDD 0.1 µF GND Test Circuit Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY24119SC S8 8-pin SOIC Commercial 3.3V CY24119SCT S8 8-pin SOIC – Tape and Reel Commercial 3.3V CY24119SC-1 S8 8-pin SOIC Commercial 3.3V CY24119SC-1T S8 8-pin SOIC – Tape and Reel Commercial 3.3V Document #: 38-07200 Rev. *B Page 3 of 5 CY24119 PRELIMINARY Package Diagram 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07200 Rev. *B Page 4 of 5 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY24119 Document History Page Document Title: CY24119 MediaClock™ 27-MHz VCXO Clock Generator Document Number: 38-07200 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 111551 03/22/02 CKN New Data Sheet *A 121877 12/14/02 RBI Power-up requirements added to Operating Conditions Information *B 129724 10/09/03 IJA Added -1 part, updated Crystal Spec Table Document #: 38-07200 Rev. *B Page 5 of 5