CY2412 MPEG Clock Generator with VCXO Features Benefits • Integrated phase-locked loop (PLL) Highest-performance PLL tailored for multimedia applications • Low-jitter, high-accuracy outputs Meets critical timing requirements in complex system designs • VCXO with analog adjust Large ±150-ppm range, better linearity • 3.3V operation Enables application compatibility Part Number Outputs CY2412 3 13.5-MHz pullable crystal input per Two 27-MHz outputs, one 54-MHz output (3.3V) Cypress specification Input Frequency Range Output Frequencies CY2412-2 3 13.5-MHz pullable crystal input per 27 MHz, 13.5 MHz, 54 MHz (3.3V) Cypress specification Logic Block Diagram Pin Configuration CY2412,-2 8-pin SOIC CLKC 13.5 XIN OSC XOUT Q Φ OUTPUT DIVIDERS VCO CLKB CLKA P VCXO PLL VDD Cypress Semiconductor Corporation Document #: 38-07227 Rev. *A • XIN 1 8 XOUT VDD VCXO 2 7 3 6 CLKC CLKB VSS 4 5 CLKA VSS 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised March 13, 2002 CY2412 Pin Summary Name Pin Number Description XIN 1 Reference Crystal Input VDD 2 Voltage Supply VCXO 3 Input Analog Control for VCXO VSS 4 Ground CLKA 5 54-MHz clock output CLKB 6 27-MHz clock output (-1) CLKB 6 13.5-MHz clock output (-2) CLKC 7 27-MHz clock output 8 Reference Crystal Output XOUT [1] Pullable Crystal Specifications Parameter CRload Description Min. Typ. Crystal Load Capacitance C0/C1 ESR Max. 14 Unit pF 240 Equivalent Series Resistance Ω 35 To Operating Temperature 70 °C Crystal Accuracy Crystal Accuracy 0 ± 20 ppm TTs Stability over Temperature and Aging ± 50 ppm Absolute Maximum Conditions Parameter Description Min. Max. Unit VDD Supply Voltage –0.5 7.0 V TS Storage Temperature[2] –65 125 °C 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 Junction Temperature TJ Electrostatic Discharge 2 V kV Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance fREF Reference Frequency Min. Typ. Max. Unit 3.14 3.3 3.47 V 0 13.5 70 °C 15 pF MHz Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for ten years. Document #: 38-07227 Rev. *A Page 2 of 5 CY2412 DC Electrical Characteristics Min. Typ. IOH Parameter Output High Current Description VOH = VDD – 0.5, VDD = 3.3V 12 24 IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 CIN Input Capacitance IIZ Input Leakage Current f∆XO VCXO pullability range VVCXO VCXO input range fVBW VCXO input bandwidth IDD Supply Current Test Conditions Max. Unit mA mA 7 pF +150 ppm µA 5 –150 0 VDD DC to 200 Sum of Core and Output Current V kHz 35 mA Typ. Max. Unit 55 AC Electrical Characteristics Parameter[3] Name Description Min. Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD 45 50 t3 Rising Edge Slew Rate Output Clock Rise Time, 20% – 80% of VDD 0.8 1.4 t4 Falling Edge Slew Rate Output Clock Fall Time, 80% – 20% of VDD 0.8 t9 Clock Jitter Peak to Peak period jitter t10 PLL Lock Time DC 1.4 100 % V/ns V/ns 200 ps 3 ms Test Circuit VDD CLK out 0.1 µF CLOAD OUTPUTS GND Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage CY2412SC S8 8-pin SOIC Commercial 3.3V CY2412SC-2 S8 8-pin SOIC Commercial 3.3V Note: 3. Not 100% tested. Document #: 38-07227 Rev. *A Page 3 of 5 CY2412 t1 t2 CLK 50% 50% Figure 1. Duty Cycle Definition; DC = t2/t1 t3 t4 80% CLK 20% Figure 2. Rise and Fall Time Definitions Package Diagram 8-lead (150-mil) SOIC S8 51-85066-A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07227 Rev. *A Page 4 of 5 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2412 Document Title: CY2412 MPEG Clock Generator with VCXO Document Number: 38-07227 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110492 10/28/01 SZV Change from Spec number: 38-00898 to 38-07227 *A 112457 03/14/02 CKN Added CY2412-2 to data sheet Document #: 38-07227 Rev. *A Page 5 of 5