TI TPS72618DCQ

TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403C – MAY 2002 – REVISED MARCH 2004
LOW INPUT VOLTAGE, 1-A LOW-DROPOUT LINEAR REGULATORS WITH SUPERVISOR
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
1-A Output Current
Available in 1.5-V, 1.6-V, 1.8-V, 2.5-V
Fixed-Output (For Adjustable Versions Refer
to TPS72501)
Input Voltage Down to 1.8 V
Low 170-mV Dropout Voltage at 1 A
(TPS72625)
Stable With Any Type/Value Output Capacitor
Integrated Supervisor (SVS) With 200-ms
RESET Delay Time
Low 210-µA Ground Current at Full Load
(TPS72625)
Less than 1-µA Standby Current
±2% Output Voltage Tolerance Over Line,
Load, and Temperature (-40°C to 125°C)
Integrated UVLO
Thermal and Overcurrent Protection
5-Lead SOT223-5 or DDPAK Surface-Mount
Package
APPLICATIONS
•
•
•
•
•
PCI Cards
Modem Banks
Telecom Boards
DSP, FPGA, and Microprocessor Power
Supplies
Portable, Battery-Powered Applications
DCQ PACKAGE
SOT223-5
(TOP VIEW)
ENABLE
1
IN
GND
OUT
2
RESET
5
KTT PACKAGE
DDPAK
(TOP VIEW)
3
1 2 3 4 5
These regulators are ideal for higher current applications. The family operates over a wide range of
input voltages (1.8 V to 6 V) and has very low
dropout (170 mV at 1-A).
Ground current is typically 210 µA at full load and
drops to less than 80 µA at no load. Standby current
is less than 1 µA.
Each regulator option is available in either a
SOT223-5 or DDPAK package. With a low input
voltage and properly heatsinked package, the regulator dissipates more power and achieves higher
efficiencies than similar regulators requiring 2.5 V or
more minimum input voltage and higher quiescent
currents. These features make it a viable power
supply solution for portable, battery powered equipment.
Although an output capacitor is not required for
stability, transient response and output noise are
improved with a 10-µF output capacitor.
Unlike some regulators that have a minimum current
requirement, the TPS726 family is stable with no
output load current. The low noise capability of this
family, coupled with its high current operation and
ease of power dissipation, make it ideal for telecom
boards, modem banks, and other noise sensitive
applications.
ENABLE
IN
GND
OUT
RESET
4
The TPS726xx family of 1-A low-dropout (LDO) linear
regulators has fixed voltage options available that are
commonly used to power the latest DSPs, FPGAs,
and microcontrollers. The integrated supervisory
circuitry provides an active low RESET signal when
the output falls out of regulation. The no capacitor/any capacitor feature allows the customer to tailor
output transient performance as needed. Therefore,
compared to other regulators capable of providing the
same output current, this family of regulators can
provide a stand alone power supply solution or a post
regulator for a switch mode power supply.
Note: Tab is GND for both packages
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403C – MAY 2002 – REVISED MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TJ
-40°C to 125°C
(1)
(2)
(3)
(4)
VOLTAGE (1) (2)
SOT223-5 (3)
SYMBOL
DDPAK (4)
SYMBOL
1.5 V
TPS72615DCQ
PS72615
TPS72615KTT
TPS72615
1.6 V
TPS72616DCQ
PS72616
TPS72616KTT
TPS72616
1.8 V
TPS72618DCQ
PS72618
TPS72618KTT
TPS72618
2.5 V
TPS72625DCQ
PS72625
TPS72625KTT
TPS72625
Other voltage options are available upon request from the manufacturer.
Refer to TPS72501 for adjustable version.
To order a taped and reeled part, add the suffix R to the part number (e.g., TPS72151DCQR).
To order a 50-piece reel, add the suffix T (e.g., TPS72615KTTT); to order a 500-piece reel, add the suffix R (e.g., TPS72615KTTR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
UNIT
Input voltage, VI (2)
-0.3 to 7
V
Voltage range at EN, FB
-0.3 to VI + 0.3
V
Voltage on OUT, RESET
6
V
ESD rating, HBM
2
kV
Continuous total power dissipation
See Dissipation Rating Table
Operating junction temperature range, TJ
-50 to 150
°C
MAximum junction temperature range, TJ
150
°C
-65 to 150
°C
Storage temperature, Tstg
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
MIN Nom MAX UNIT
Input voltage, VI (1)
Continuous output current, IO
Operating junction temperature, TJ
(1)
1.8
6
0
1
V
A
-40
125
°C
Minimum VI = VO(nom) + VDO.
PACKAGE DISSIPATION RATINGS
(1)
(2)
2
PACKAGE
BOARD
RΘJC
RΘJA
DDPAK
High K (1)
2 °C/W
23 °C/W
SOT223
Low K (2)
15 °C/W
53 °C/W
The JEDEC high K (2s2p) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), multilayer board with 1 ounce
internal power and ground planes and 2 ounce copper traces on top and bottom of the board.
The JEDEC low K (1s) board design used to derive this data was a 3-inch x 3-inch (7,5-cm x 7,5-cm), two-layer board with 2 ounce
copper traces on top of the board.
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403C – MAY 2002 – REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range VI = VO(typ) + 1 V, IO= 1 mA, EN = IN, Co = 1 µF, Ci = 1 µF(unless
otherwise noted)
PARAMETER
TEST CONDITIONS
Bandgap voltage reference
TPS72615
TPS72616
VO
Output voltage
TPS72618
TPS72625
I
Ground current
Standby current
0 µA < IO < 1 A
UNIT
1.177
1.220
1.263
V
1.8 V ≤ VI≤ 5.5 V
1.47
2.6 V ≤ VI≤ 5.5 V
1.568
TJ = 25°C
0 µA < IO < 1 A
TJ = 25°C
0 µA < IO < 1 A
2.8 V ≤ VI≤ 5.5 V
1.764
3.5 V ≤ VI≤ 5.5 V
2.45
2.55
75
120
IO = 1 A
210
300
TJ = 25°C
0.2
EN < 0.4 V
1
PSRR
Ripple rejection
f = 1 kHz, Co = 10 µF
TJ = 25°C
µA
µA
150
µV
60
dB
1.1
1.6
2.3
A
VO + 1 V < VI≤ 5.5 V
-0.15
0.02
0.15
%/V
0 µA < IO < 1 A
-0.25
0.05
0.25
%/A
(1)
VIH
EN high level input
1.3
VIL
EN low level input
-0.2
II
EN input current
EN = 0 V or VI
UVLO threshold
VCC rising
UVLO hysteresis
TJ = 25°C, VCC rising
UVLO deglitch
UVLO delay
(2)
1.836
IO = 0 µA
EN < 0.4 V
V
2.5
Co = 10 µF,IO = 1
mA
(1)
1.632
1.8
TJ = 25°C
0 µA < IO < 1 A
1.53
1.6
BW = 200 Hz to 100 kHz,
TJ = 25°C,
Output voltage load regulation
MAX
1.5
Output noise voltage
Output voltage line regulation
(∆VO/VO) (2)
TYP
TJ = 25°C
Vn
Current limit
MIN
1.45
0.4
0.01
100
1.57
1.70
V
nA
V
50
mV
TJ = 25°C, VCC rising
10
µs
TJ = 25°C, VCC rising
100
µs
Test condition includes, output voltage VO = VO - 15% and pulse duration = 10 ms.
VImin = (VO + 1) or 1.8 V whichever is greater.
Line regulation (mV) (%V) VO(5.5 V VImin)
1000
100
3
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403C – MAY 2002 – REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range VI = VO(typ) + 1 V, IO= 1 mA, EN = IN, Co = 1 µF, Ci = 1 µF(unless
otherwise noted)
PARAMETER
VDO
TEST CONDITIONS
TPS72625
(3)
TPS72618
(3)
IO = 1 A
MIN
TJ = 25°C
280
IO = 1 A
TJ = 25°C
210
IO = 1 A
UNIT
mV
320
Minimum input voltage for valid
RESET
1.3
Trip threshold voltage
90
Hysteresis voltage
V
93
96
10
t(RESET) delay time
100
Rising edge deglitch
200
-0.3
Leakage current
%VO
mV
300
10
Output low voltage (at 700 µA)
(3)
MAX
170
IO = 1 A
Dropout voltage
RESET
TYP
ms
µs
0.4
V
100
nA
Dropout voltage is defined as the differential voltage between VO and VI when VO drops 100 mV below the value measured withVI = VO
+ 1 V.
FUNCTIONAL BLOCK DIAGRAM
TPS72615/16/18/25
IN
OUT
EN
Current Limit
/ Thermal
Protection
1.220
Vref
GND
Deglitch
and
Delay
RESET
0.93 × Vref
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
GND
3
ENABLE
1
I
Enable input
IN
2
I
Input supply voltage
RESET
5
O/I
This terminal is the RESET output terminal. When used with a pullup resistor, this open-drain output provides
the active low RESET signal when the regulator output voltage drops more than 5% below its nominal output
voltage. The RESET delay time is typically 200 ms.
OUT
4
O
Regulated output voltage
4
Ground
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403C – MAY 2002 – REVISED MARCH 2004
RESET TIMING DIAGRAM
IN
VRES
(see Note A)
VRES
t
OUT
VIT +(see Note B)
VIT +(see Note B)
Threshold
Voltage
VIT (see Note B)
VIT (see Note B)
t
RESET
Output
Output
Undefined
200 ms
Delay
200 ms
Delay
Output
Undefined
t
NOTES:A. VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for
semiconductor symbology.
B. VIT -Trip voltage is typically 7% lower than the output voltage (93%VO) VIT- to VIT+ is the hysteresis voltage.
5
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403C – MAY 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS
TPS72618 OUTPUT VOLTAGE
vs
OUTPUT CURRENT
TPS72618 OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
1.805
1.8015
250
1.8
1.7995
Ground Current − µ A
V O − Output Voltage − V
1.8005
1.800
IO = 0 mA
1.795
IO = 1 A
1.790
200
0
0.2
0.4
0.8
0.6
1
IO − Output Current − A
1.785
−40−25 −10 5 20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
0
−40 −25 −10 5
20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
Figure 1.
Figure 2.
Figure 3.
TPS72618 GROUND CURRENT
vs
OUTPUT CURRENT
TPS72625 DC DROPOUT VOLTAGE
vs
OUTPUT CURRENT
TPS72618 DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
300
200
300
VO = 1.7 V
Co = 1 µF
VO = 2.5 V (nom)
175
150
125
100
75
50
25
0
0.01
V DO − Dropout Voltage − mV
250
V DO − Dropout Voltage − mV
TJ = 125°C
200
TJ = 25°C
150
100
TJ = −40°C
50
250
150
100
0
0.1
1
10
100
0
1000
IO − Output Current − mA
0.2
0.4
0.6
0.8
IO − Output Current − A
IO = 1 A
200
50
IO = 10 mA
0
−40 −25 −10 5
1
20 35 50 65 80 95 110 125
TJ − Junction Temperature − °C
Figure 5.
Figure 6.
MINIMUM REQUIRED INPUT VOLTAGE
vs
OUTPUT VOLTAGE
TPS72618 LINE TRANSIENT
RESPONSE
TPS72618 LOAD TRANSIENT
RESPONSE
4
VI − Input Voltage − V
4.5
TJ = 125°C
3.5
TJ = 25°C
IO = 1 A
Co = 10 µF
3.8
2.8
∆VO − Change in
Output Voltage − mV
Figure 4.
VO = 2.8 V
Co = 10 µF
Ci = 1 µF
100
0
−100
2.5
TJ = −40°C
2
1.5
1.5
2
2.5
3
3.5
VO − Output Voltage − V
Figure 7.
4
4.5
VO − Output Voltage − mV
3
100
0
−100
0
50 100 150 200 250 300 350 400 450 500
t − Time − µs
Figure 8.
I O − Output Current − A
Ground Current − µ A
IO = 0 mA
100
50
1.7985
V I − Minimum Required Input Voltage − V
IO = 1 A
150
1.799
6
VI = 2.8 V
Co = 1 µF
TJ = 25° C
VI = 2.8 V
Co = 1 µF
VI = 2.8 V
Co = 1 µF
TJ = 25° C
1.801
V O − Output Voltage − V
TPS72618 GROUND CURRENT
vs
JUNCTION TEMPERATURE
1
0.5
0
0
5
10 15 20 25 30 35 40 45 50
t − Time − µs
Figure 9.
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403C – MAY 2002 – REVISED MARCH 2004
TYPICAL CHARACTERISTICS (continued)
TPS72618 OUTPUT VOLTAGE,
ENABLE VOLTAGE
vs
TIME (START-UP)
1
0.5
0
0
5
10
15 20 25 30 35 40
t − Time − µs
45 50
1
0
2
1.5
1
0.5
0
0
80 100 120 140 160 180 200
t − Time − µs
20 40 60
RL = 1.8 Ω
Co = 1 µF
Ci = 1 µF
5
4
3
VI
2
1
0
VO
0 100 200 300 400 500 600 700 800 900 1000
t − Time − µs
Figure 11.
Figure 12.
TPS72618 OUTPUT SPECTRAL
NOISE DENSITY
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
TPS72618 RIPPLE REJECTION
vs
FREQUENCY
10
2
IO = 1 A
1.5
1
0.5
100
0
10
100
1k
10 k
f − Frequency − Hz
0.1
VI = 2.8 V
Co = 10 µF
TJ = 25° C
0.01
80
70
60
10 µF / 1mA
50
40
30
10 µF / 1A
20
10
0
0
10
100 k
IO = 1 mA
1
IO = 1 mA
VI= 2.8 V,
VO = 1.8 V,
CO = 10 µF
90
IO = 1 A
Ripple Rejection − dB
VI = 2.8 V
Co = 10 µF
Z o − Output Impedance − Ω
µ V/
Output Spectral Noise Density −
2.5
VI = 2.8 V
IO = 1 A
Co = 10 µF
2
Figure 10.
3.5
3
3
VI − Input Voltage − V
VI = 2.8 V
Co = 1 µF
CI = 1 µF
TPS72618 POWER UP/POWER
DOWN
VO − Output Voltage − V
0
−100
Hz
Enable Voltage − V
100
V − Output Voltage − V
O
∆VO − Change in
I O − Output Current − A Output Voltage − mV
TPS72618 LOAD TRANSIENT
RESPONSE
100
1k
10 k
100 k
1M
10
100
f − Frequency − Hz
10 k
100 k
Figure 13.
Figure 14.
Figure 15.
CURRENT LIMIT
vs
INPUT VOLTAGE
TPS72615 GROUND CURRENT
vs
INPUT VOLTAGE
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
2000
600
300
500
250
Ground Current − µ A
TJ = 125°C
1800
1700
1600
1500
TJ = 25°C
1400
TJ = −40°C
1300
V DO − Dropout Voltage − mV
1900
Current Limit − A
1k
400
300
I=1A
200
I=0A
1200
1M
f − Frequency − Hz
100
TJ = 125°C
TJ = 25°C
200
150
100
TJ = −40°C
50
1100
1000
1.5
0
0
2
2.5
3
3.5
4
4.5
VI − Input voltage − V
Figure 16.
5
5.5
0
1
2
3
4
VI − Input Voltage − V
Figure 17.
5
6
1.5
2
2.5 3
3.5 4
4.5
VI − Input Voltage − V
5
5.5
Figure 18.
7
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403C – MAY 2002 – REVISED MARCH 2004
APPLICATION INFORMATION
The TPS726xx family of low-dropout (LDO) regulators have numerous features that make it apply to a wide
range of applications. The family operates with very low input voltage (≥1.8 V) and low dropout voltage (typically
200 mV at full load), making it an efficient stand-alone power supply or post regulator for battery or switch mode
power supplies. Both the active low RESET and 1-A output current, make the TPS726xx family ideal for
powering processor and FPGA supplies. The TPS726xx family also has low output noise (typically 150 µVRMS
with 10-µF output capacitor), making it ideal for use in telecom equipment.
External Capacitor Requirements
A 1-µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS725xx, is required for stability. To improve transient response, noise rejection, and ripple rejection, an
additional 10-µF or larger, low ESR capacitor is recommended. A higher-value, low ESR input capacitor may be
necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the
power source, especially if the minimum input voltage of 1.8 V is used.
Although an output capacitor is not required for stability, transient response and output noise are improved with a
10-µF output capacitor.
Regulator Protection
The TPS726xx pass element has a built-in back diode that safely conducts reverse current when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be
appropriate.
The TPS726xx also features internal current limiting and thermal protection. During normal operation, the
TPS726xx limits output current to approximately 1.6 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the
device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled down to below
145°C, regulator operation resumes.
THERMAL INFORMATION
The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it
dissipates during operation. All integrated circuits have a maximum allowable junction temperature (TJmax)
above which normal operation is not assured. A system designer must design the operating environment so that
the operating junction temperature (TJ) does not exceed the maximum junction temperature (TJmax). The two
main environmental variables that a designer can use to improve thermal performance are air flow and external
heatsinks. The purpose of this information is to aid the designer in determining the proper operating environment
for a linear regulator that is operating at a specific power level.
In general, the maximum expected power (PD(max)) consumed by a linear regulator is computed as:
P max V
V
I
V
xI
D
I(avg)
O(avg)
O(avg)
I(avg) (Q)
(1)
Where:
• VI(avg) is the average input voltage.
• VO(avg) is the average output voltage.
• O(avg) is the average output current.
• I(Q) is the quiescent current.
For most TI LDO regulators, the quiescent current is insignificant compared to the average output current;
therefore, the term VI(avg) x I(Q) can be neglected. The operating junction temperature is computed by adding the
ambient temperature (TA) and the increase in temperature due to the regulator's power dissipation. The
temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal
resistances between the junction and the case (RΘJC), the case to heatsink (RΘCS), and the heatsink to ambient
(RΘSA). Thermal resistances are measures of how effectively an object dissipates heat. Typically, the larger the
device, the more surface area available for power dissipation and the lower the object's thermal resistance.
8
TPS72615, TPS72616
TPS72618, TPS72625
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SLVS403C – MAY 2002 – REVISED MARCH 2004
THERMAL INFORMATION (continued)
Figure 19 illustrates these thermal resistances for (a) a SOT223 package mounted in a JEDEC low-K board, and
(b) a DDPAK package mounted on a JEDEC high-K board.
A
TJ
RθJC
CIRCUIT BOARD COPPER AREA
C
B
B
A
B
TC
RθCS
A
C
RθSA
SOT223 Package
(a)
TA
DDPAK Package
(b)
C
Figure 19. Thermal Resistances
Equation 2 summarizes the computation:
T
J
T PDmax x R
R
R
A
θJC
θCS
θSA
(2)
The RΘJC is specific to each regulator as determined by its package, lead frame, and die size provided in the
regulator's data sheet. The RΘSA is a function of the type and size of heatsink. For example, black body radiator
type heatsinks can have RΘCS values ranging from 5°C/W for very large heatsinks to 50°C/W for very small
heatsinks. The RΘCS is a function of how the package is attached to the heatsink. For example, if a thermal
compound is used to attach a heatsink to a SOT223 package, RΘCSof 1°C/W is reasonable.
Even if no external black body radiator type heatsink is attached to the package, the board on which the
regulator is mounted provides some heatsinking through the pin solder connections. Some packages, like the
DDPAK and SOT223 packages, use a copper plane underneath the package or the circuit board's ground plane
for additional heatsinking to improve their thermal performance. Computer-aided thermal modeling can be used
to compute very accurate approximations of an integrated circuit's thermal performance in different operating
environments (e.g., different types of circuit boards, different types and sizes of heatsinks, and different air flows,
etc.). Using these models, the three thermal resistances can be combined into one thermal resistance between
junction and ambient (RΘJA). This RΘJAis valid only for the specific operating environment used in the computer
model.
Equation 2 simplifies into Equation 3:
T T PDmax x R
J
A
θJA
Rearranging Equation 3 gives Equation 4:
T –T
R
J A
θJA
P max
D
(3)
(4)
Using Equation 3 and the computer model generated curves shown in Figure 20 and Figure 23, a designer can
quickly compute the required heatsink thermal resistance/board area for a given ambient temperature, power
dissipation, and operating environment.
DDPAK Power Dissipation
The DDPAK package provides an effective means of managing power dissipation in surface mount applications.
The DDPAK package dimensions are provided in the Mechanical Data section at the end of the data sheet. The
addition of a copper plane directly underneath the DDPAK package enhances the thermal performance of the
package.
9
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403C – MAY 2002 – REVISED MARCH 2004
THERMAL INFORMATION (continued)
To illustrate, the TPS72625 in a DDPAK package was chosen. For this example, the average input voltage is 5
V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55°C, the air flow is
150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current,
the maximum average power is:
P Dmax (5 2.5) V x 1 A 2.5 W
(5)
Substituting TJmax for TJ into Equation 4 gives Equation 6:
R
max (125 55)°C2.5 W 28°CW
θJA
(6)
2
From Figure 20, DDPAK Thermal Resistance vs Copper Heatsink Area, the ground plane needs to be 1 cm for
the part to dissipate 2.5 W. The operating environment used in the computer model to construct Figure 20
consisted of a standard JEDEC High-K board (2S2P) with a 1 oz. internal copper plane and ground plane. The
package is soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane.
Figure 21 shows the side view of the operating environment used in the computer model.
40
Rθ JA − Thermal Resistance −
° C/W
No Air Flow
35
150 LFM
30
250 LFM
25
20
15
0.1
1
10
Copper Heatsink Area − cm2
100
Figure 20. DDPAK Thermal Resistance vs Copper Heatsink Area
2 oz. Copper Solder Pad
with 25 Thermal Vias
1 oz. Copper
Power Plane
1 oz. Copper
Ground Plane
Thermal Vias, 0,3 mm
Diameter, 1,5 mm Pitch
Figure 21. DDPAK Thermal Resistance
10
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403C – MAY 2002 – REVISED MARCH 2004
THERMAL INFORMATION (continued)
From the data in Figure 22 and rearranging Equation 4, the maximum power dissipation for a different ground
plane area and a specific ambient temperature can be computed.
TJM − Maximum Junction Temperature − 125 °C
5
PD − Maximum Power Dissipation − W
TA = 55°C
4
250 LFM
150 LFM
3
No Air Flow
2
1
0.1
1
10
Copper Heatsink Area − cm2
100
Figure 22. Maximum Power Dissipation vs Copper Heatsink Area
SOT223 Power Dissipation
The SOT223 package provides an effective means of managing power dissipation in surface mount applications.
The SOT223 package dimensions are provided in the Mechanical Data section at the end of the data sheet. The
addition of a copper plane directly underneath the SOT223 package enhances the thermal performance of the
package.
To illustrate, the TPS72625 in a SOT223 package was chosen. For this example, the average input voltage is
3.3 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55°C, no air flow is
present, and the operating environment is the same as documented below. Neglecting the quiescent current, the
maximum average power is:
P Dmax (3.3 2.5) V x 1 A 800 mW
(7)
Substituting TJmax for TJ into Equation 4 gives Equation 8:
R
max (125 55)°C800 mW 87.5°CW
θJA
(8)
2
From Figure 23, RΘJA vs PCB Copper Area, the ground plane needs to be 0.55 in for the part to dissipate 800
mW. The operating environment used to construct Figure 23 consisted of a board with 1 oz. copper planes. The
package is soldered to a 1 oz. copper pad on the top of the board. The pad is tied through thermal vias to the 1
oz. ground plane.
11
TPS72615, TPS72616
TPS72618, TPS72625
www.ti.com
SLVS403C – MAY 2002 – REVISED MARCH 2004
THERMAL INFORMATION (continued)
Rθ JA − Thermal Resistance −
° C/W
180
No Air Flow
160
140
120
100
80
60
40
20
0
0.1
1
PCB Copper Area − in2
10
Figure 23. SOT223 Thermal Resistance vs PCB AREA
From the data in Figure 23 and rearranging Equation 4, the maximum power dissipation for a different ground
plane area and a specific ambient temperature can be computed (as shown in Figure 24).
6
PD − Maximum Power Dissipation − W
TA = 25°C
5
4
4 in2 PCB Area
3
0.5 in2 PCB Area
2
1
0
0
25
50
75
100
125
TA − Ambient Temperature − °C
Figure 24. SOT223 Power Dissipation
12
150
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