MCP6231/1R/1U/2/4 20 µA, 300 kHz Rail-to-Rail Op Amp Features Description • • • • • • The Microchip Technology Inc. MCP6231/1R/1U/2/4 operational amplifiers (op amps) provide wide bandwidth for the quiescent current. The MCP6231/1R/ 1U/2/4 family has a 300 kHz gain bandwidth product and 65°C (typical) phase margin. This family operates from a single supply voltage as low as 1.8V, while drawing 20 µA (typical) quiescent current. In addition, the MCP6231/1R/1U/2/4 family supports rail-to-rail input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS – 300 mV. These op amps are designed in one of Microchip’s advanced CMOS processes. Gain Bandwidth Product: 300 kHz (typical) Supply Current: IQ = 20 µA (typical) Supply Voltage: 1.8V to 6.0V Rail-to-Rail Input/Output Extended Temperature Range: -40°C to +125°C Available in 5-Pin SC70 and SOT-23 packages Applications • • • • • • Automotive Portable Equipment Transimpedance amplifiers Analog Filters Notebooks and PDAs Battery-Powered Systems Package Types MCP6231 5 VDD VOUT 1 VSS 2 4 VIN– RG2 – 7 VDD VIN+ 3 + 6 VOUT SOT-23-5 MSOP, PDIP, SOIC 5 VSS VOUT 1 VDD 2 5 NC MCP6232 MCP6231R VOUTA 1 VINA_ 2 – 4 VIN– MCP6231U SC70-5, SOT-23-5 RG1 VINA+ 3 8 VDD 7 VOUTB - + 6 VINB_ + - RF VSS 2 VINA_ 2 4 VOUT VINA+ 3 VSS 4 VOUT MCP6231 DFN * + RZ NC 1 VIN– 2 VIN+ 3 Summing Amplifier Circuit VSS 4 EP 9 8 VDD VOUTA 1 – VIN– 3 – MCP6231 5 VDD VIN+ 1 5 VINB+ MCP6232 2x3 TDFN * + VIN1 RX 8 NC VSS 4 VIN2 VDD NC 1 VIN– 2 VSS 4 VIN+ 3 Typical Application RY – VIN+ 3 + SPICE Macro Models FilterLab® Software Mindi™ Circuit Designer & Simulator Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes + Design Aids • • • • • • MCP6231 MSOP, PDIP, SOIC SOT-23-5 EP 9 7 VOUTB 6 VINB_ 5 VINB+ MCP6234 PDIP, SOIC, TSSOP 8 NC VOUTA 1 7 VDD VINA– 2 - + + - 13 VIND– 6 VOUT VINA+ 3 VDD 4 12 VIND+ VINB+ 5 VINB– 6 10 VINC+ - + +- 9 V – INC VOUTB 7 8 VOUTC 5 NC 14 VOUTD 11 VSS * Includes Exposed Thermal Pad (EP); see Table 3-1. © 2009 Microchip Technology Inc. DS21881E-page 1 MCP6231/1R/1U/2/4 NOTES: DS21881E-page 2 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 1.0 ELECTRICAL CHARACTERISTICS VDD – VSS ........................................................................7.0V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Current at Analog Input Pins (VIN+, VIN–).....................±2 mA †† See Section 4.1.2 “Input Voltage and Current Limits”. Absolute Maximum Ratings † Analog Inputs (VIN+, VIN–) †† ........ VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD – VSS| Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ............................±30 mA Storage Temperature ................................... –65°C to +150°C Maximum Junction Temperature (TJ)......................... .+150°C ESD Protection On All Pins (HBM; MM) .............. ≥ 4 kV; 300V DC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, RL = 100 kΩ to VDD/2 and VOUT ≈ VDD/2. Sym Min Typ Max Units Conditions Input Offset Voltage VOS -5.0 — +5.0 mV VCM = VSS Extended Temperature VOS -7.0 — +7.0 mV TA = -40°C to +125°C, VCM = VSS (Note 1) ΔVOS/ΔTA — ±3.0 — µV/°C TA= -40°C to +125°C, VCM = VSS PSRR — 83 — dB Input Bias Current: IB — ±1.0 — pA At Temperature IB — 20 — pA TA = +85°C At Temperature IB — 1100 — pA TA = +125°C IOS — ±1.0 — pA Parameters Input Offset Input Offset Drift with Temperature Power Supply Rejection Ratio VCM = VSS Input Bias Current and Impedance Input Offset Current Common Mode Input Impedance ZCM — 1013||6 — Ω||pF Differential Input Impedance ZDIFF — 1013||3 — Ω||pF Common Mode Input Range VCMR VSS – 0.3 — VDD + 0.3 V Common Mode Rejection Ratio CMRR 61 75 — dB VCM = -0.3V to 5.3V, VDD = 5V AOL 90 110 — dB VOUT = 0.3V to VDD – 0.3V, VCM = VSS VOL, VOH VSS + 35 — VDD – 35 mV RL =10 kΩ, 0.5V Input Overdrive ISC — ±6 — mA VDD = 1.8V ISC — ±23 — mA VDD = 5.5V VDD 1.8 — 6.0 V IQ 10 20 30 µA Common Mode Open-Loop Gain DC Open-Loop Gain (large signal) Output Maximum Output Voltage Swing Output Short-Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: 2: IO = 0, VCM = VDD – 0.5V The SC70 package is only tested at +25°C. All parts with date codes February 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 1.8V and 5.5V © 2009 Microchip Technology Inc. DS21881E-page 3 MCP6231/1R/1U/2/4 AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF. Parameters Sym Min Typ Max Units Conditions GBWP — 300 — kHz Phase Margin PM — 65 — ° Slew Rate SR — 0.15 — V/µs Input Noise Voltage Eni — 6.0 — µVP-P Input Noise Voltage Density eni — 52 — nV/√Hz f = 1 kHz Input Noise Current Density ini — 0.6 — fA/√Hz f = 1 kHz AC Response Gain Bandwidth Product G = +1 V/V Noise f = 0.1 Hz to 10 Hz TEMPERATURE CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Conditions Temperature Ranges Extended Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 5L-SC70 θJA — 331 — °C/W Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W Thermal Resistance, 8L-DFN θJA — 84.5 — °C/W Thermal Resistance, 8L-MSOP θJA — 206 — °C/W Thermal Resistance, 8L-TDFN θJA — 41 — °C/W Thermal Resistance, 8L-PDIP θJA — 85 — °C/W Thermal Resistance, 8L-SOIC θJA — 163 — °C/W Thermal Resistance, 14L-PDIP θJA — 70 — °C/W Thermal Resistance, 14L-SOIC θJA — 120 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W Note Thermal Package Resistances Note: 1.1 The internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C. Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-1 and Figure 1-1. The bypass capacitors are laid out according to the rules discussed in Section 4.6 “PCB Surface Leakage”. VDD VDD/2 RN 0.1 µF 1 µF VOUT MCP623X CL VDD VIN 0.1 µF 1 µF VIN RG RL RF VL RN VOUT MCP623X CL VDD/2 RG RL FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions. RF VL FIGURE 1-1: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. DS21881E-page 4 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 90 CMRR, PSRR (dB) 630 Samples VCM = VSS 85 PSRR (VCM = VSS) 80 75 CMRR (VCM = -0.3V to +5.3V, VDD = 5.0V) -25 0 25 50 75 Ambient Temperature (°C) Input Offset Voltage (mV) FIGURE 2-4: Temperature. 100 120 30 1.E+02 10 1.E+03 100 1.E+04 1k 100k Frequency (Hz) PSRR, CMRR vs. -180 30% 25% 20% 15% 10% 5% 0% Input Bias Current (pA) FIGURE 2-3: Input Bias Current at +85°C. © 2009 Microchip Technology Inc. Open-Loop Gain, Phase vs. 632 Samples VCM = VDD/2 TA = +125°C 0.0 Percentage of Occurrences 42 36 30 24 18 12 -150 0 FIGURE 2-5: Frequency. 630 Samples VCM = VDD/2 TA = +85°C 6 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 0 Percentage of Occurrences FIGURE 2-2: Frequency. 20 -20 -210 0.1 1.E+ 1 1.E+ 10 1.E+ 100 1.E+ 1k 1.E+ 10k 100k 1M 1.E+ 10M 1.E1.E+ 1.E+ 01 00 01 Frequency 02 03 (Hz) 04 05 06 07 1.E+05 10k -120 0.6 20 1.E+01 -90 Phase 2.0 40 -60 40 0.4 50 60 -30 1.8 PSRR+ 0 1.6 CMRR 60 Gain 80 0.2 70 100 1.0 80 RL = 10 kΩ VCM = VDD/2 0.8 PSRR- Open-Loop Gain (dB) PSRR, CMRR (dB) 90 125 CMRR, PSRR vs. Ambient 1.4 Input Offset Voltage. 1.2 FIGURE 2-1: 100 Open-Loop Phase (°) -50 5 4 3 2 1 0 -1 -2 -3 -4 70 -5 Percentage of Occurrences Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF. Input Bias Current (nA) FIGURE 2-6: +125°C. Input Bias Current at DS21881E-page 5 MCP6231/1R/1U/2/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF. FIGURE 2-7: vs. Frequency. VDD = 1.8V TA = -40°C TA = +25°C TA = +85°C TA = +125°C 450 350 250 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 150 FIGURE 2-10: 50 0 -50 -100 -150 Common Mode Input Voltage (V) FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -200 DS21881E-page 6 12 10 8 6 4 2 0 0 -50 -100 VDD = 5.5V -150 -200 VDD = 1.8V -250 -300 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Short-Circuit Current (mA) TA = +125°C TA = +85°C TA = +25°C TA = -40°C 100 -2 VCM = VSS 50 FIGURE 2-11: Output Voltage. VDD = 5.5 V 150 Input Offset Voltage Drift. Output Voltage (V) FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. 200 -4 Input Offset Voltage Drift (µV/°C) Common Mode Input Voltage (V) Input Offset Voltage (µV) -6 -8 -10 628 Samples VCM = VSS TA = -40°C to +125°C 100 550 Input Offset Voltage (µV) Input Noise Voltage Density 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% -12 10 0.1 1.E+0 1 10 100 1.E+0 1k 10k 1.E+0 100k 1.E-01 1.E+0 1.E+0 1.E+0 0 1Frequency 2 (Hz)3 4 5 Percentage of Occurrences 100 Input Offset Voltage (µV) Input Noise Voltage Density (nV/√Hz) 1,000 30 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 Input Offset Voltage vs. +ISC TA = +125°C TA = +85°C TA = +25°C TA = -40°C -ISC 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature. © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF. VDD = 5.5V 0.25 Falling Edge 0.20 0.15 0.10 Rising Edge VDD = 1.8V 0.05 -50 -25 0 25 50 75 100 Ambient Temperature (°C) FIGURE 2-13: Temperature. 125 Slew Rate vs. Ambient Time (2 µs/div) FIGURE 2-16: Pulse Response. 1,000 VDD = 5.0V G = +1 V/V 4.5 100 VDD – VOH VOL – VSS 10 1 10µ 1.E-02 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 100µ 1m 1.E-01 1.E+00 Output Current Magnitude (A) 10m 1.E+01 0.0 Time (20 µs/div) FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-17: Pulse Response. 30 10 VDD = 5.5V 1 Quiescent Current per Amplifier (µA) Max. Output Voltage Swing (VP-P ) Small-Signal, Non-Inverting 5.0 Output Voltage (V) Output Voltage Headroom (mV) G = +1 V/V RL = 10 kΩ Output Voltage (10 mV/div) Slew Rate (V/µs) 0.30 VDD = 1.8V 0.1 1k 1.E+03 Large-Signal, Non-Inverting VCM = 0.9VDD 25 20 15 10 5 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 0 10k 100k 1.E+04 1.E+05 Frequency (Hz) 1M 1.E+06 FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. © 2009 Microchip Technology Inc. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. DS21881E-page 7 MCP6231/1R/1U/2/4 6.0 +125°C +85°C +25°C -40°C -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS). DS21881E-page 8 Input, Output Voltages (V) Input Current Magnitude (A) 1.E-02 10m 1.E-03 1m 1.E-04 100µ 1.E-05 10µ 1.E-06 1µ 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12 VOUT 5.0 4.0 VDD = 5.0V G = +2 V/V VIN 3.0 2.0 1.0 0.0 -1.0 Time (1 ms/div) FIGURE 2-20: The MCP6231/1R/1U/2/4 Show No Phase Reversal. © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps). TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6231 MCP6231R MCP6231U DFN, MSOP, PDIP, SOIC SOT-23-5 SOT-23-5 SOT-23-5 SC70 6 1 1 4 Analog Output 4 4 3 VIN– Inverting Input 3 3 1 VIN+ Non-inverting Input 7 5 2 5 VDD Positive Power Supply 4 2 5 2 VSS Negative Power Supply 1, 5, 8 — — — NC No Internal Connection 9 — — — EP Exposed Thermal Pad (EP); must be connected to VSS. PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6232 MCP6234 MSOP, PDIP, SOIC, TDFN PDIP, SOIC, TSSOP 1 1 VOUTA Analog Output (op amp A) 2 2 VINA– Inverting Input (op amp A) 3 3 VINA+ Non-inverting Input (op amp A) 8 4 VDD 5 5 VINB+ Non-inverting Input (op amp B) 6 6 VINB– Inverting Input (op amp B) Analog Output (op amp B) Symbol Description Positive Power Supply 7 7 VOUTB — 8 VOUTC Analog Output (op amp C) — 9 VINC– Inverting Input (op amp C) — 10 VINC+ 4 11 VSS — 12 VIND+ Non-inverting Input (op amp D) — 13 VIND– Inverting Input (op amp D) — 14 VOUTD 9 — — Analog Outputs Analog Inputs The non-inverting and inverting inputs are high-impedance CMOS inputs with low bias currents. 3.3 VOUT 2 The output pins are low-impedance voltage sources. 3.2 Description 3 TABLE 3-2: 3.1 Symbol Power Supply (VSS and VDD) The positive power supply (VDD) is 1.8V to 6.0V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. © 2009 Microchip Technology Inc. Non-inverting Input (op amp C) Negative Power Supply Analog Output (op amp D) Exposed Thermal Pad (EP); must be connected to VSS. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. 3.4 Exposed Thermal Pad (EP) There is an internal electrical connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). DS21881E-page 9 MCP6231/1R/1U/2/4 NOTES: DS21881E-page 10 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 4.0 APPLICATION INFORMATION The MCP6231/1R/1U/2/4 family of op amps is manufactured using Microchip’s state-of-the-art CMOS process and is specifically designed for low-cost, low-power and general-purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6231/1R/1U/2/4 ideal for battery-powered applications. 4.1 VIN+ Bond Pad Rail-to-Rail Inputs 4.1.1 PHASE REVERSAL 6.0 VOUT 5.0 4.0 Bond V – IN Pad Input Stage VSS Bond Pad The MCP6231/1R/1U/2/4 op amp is designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 4-1 shows the input voltage exceeding the supply voltage without any phase reversal. Input, Output Voltages (V) VDD Bond Pad VDD = 5.0V G = +2 V/V VIN 3.0 2.0 1.0 0.0 -1.0 FIGURE 4-2: Structures. Simplified Analog Input ESD In order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the currents and voltages at the VIN+ and VIN– pins (see Absolute Maximum Ratings † at the beginning of Section 1.0 “Electrical Characteristics”). Figure 4-3 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN–) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN–) from going too far above VDD, and dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. Time (1 ms/div) VDD FIGURE 4-1: The MCP6231/1R/1U/2/4 Show No Phase Reversal. D1 4.1.2 INPUT VOLTAGE AND CURRENT LIMITS The ESD protection on the inputs can be depicted as shown in Figure 4-2. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. D2 V1 R1 MCP623X V2 R2 R3 VSS – (minimum expected V1) 2 mA VSS – (minimum expected V2) R2 > 2 mA R1 > FIGURE 4-3: Inputs. Protecting the Analog It is also possible to connect the diodes to the left of resistors R1 and R2. In this case, current through the diodes D1 and D2 needs to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN–) should be very small. © 2009 Microchip Technology Inc. DS21881E-page 11 MCP6231/1R/1U/2/4 4.1.3 1k 1,000 NORMAL OPERATION The input stage of the MCP6231/1R/1U/2/4 op amps use two differential CMOS input stages in parallel. One operates at low common mode input voltage (VCM), while the other operates at high VCM. WIth this topology, the device operates with VCM up to 0.3V above VDD and 0.3V below VSS. 4.2 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity-gain buffer (G = +1) is the most sensitive to capacitive loads, but all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 60 pF when G = +1), a small series resistor at the output (RISO in Figure 4-4) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. – VIN MCP623X + GN = 1 V/V GN = 2 V/V GN ≥ 4 V/V 100 100 10p 10 100p 1n 10n 100 1000 10000 Normalized Load Capacitance; CL/GN (F) FIGURE 4-5: Recommended RISO Values for Capacitive Loads. Rail-to-Rail Output The output voltage range of the MCP6231/1R/1U/2/4 op amps is VDD – 35 mV (maximum) and VSS + 35 mV (minimum) when RL = 10 kΩ is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-14 for more information. 4.3 10,000 10k Recommended RISO (Ω) A significant amount of current can flow out of the inputs when the common mode voltage (VCM) is below ground (VSS); see Figure 2-19. Applications that are high impedance may need to limit the usable voltage range. RISO After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Evaluation on the bench and simulations with the MCP6231/1R/1U/2/4 SPICE macro model are very helpful. Modify RISO’s value until the response is reasonable. 4.4 Supply Bypass With this op amp, the power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. It can use a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other nearby analog parts. 4.5 Unused Op Amps An unused op amp in a quad package (MCP6234) should be configured as shown in Figure 4-6. Both circuits prevent the output from toggling and causing crosstalk. Circuit A can use any reference voltage between the supplies, provides a buffered DC voltage and minimizes the supply current draw of the unused op amp. Circuit B minimizes the number of components, but may draw a little more supply current for the unused op amp. VOUT CL ¼ MCP6234 (A) ¼ MCP6234 (B) VDD FIGURE 4-4: Output resistor, RISO stabilizes large capacitive loads. R1 Figure 4-5 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit’s noise gain. For non-inverting gains, GN and the signal gain are equal. For inverting gains, GN is 1 + |Signal Gain| (e.g., –1 V/V gives GN = +2 V/V). R2 VDD VDD R2 V REF = V DD ⋅ -------------------R1 + R2 FIGURE 4-6: DS21881E-page 12 VREF Unused Op Amps. © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 4.6 PCB Surface Leakage 4.7 In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6231/1R/1U/2/4 family’s bias current at +25°C (1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-7. VIN– VIN+ Application Circuits 4.7.1 MATCHING THE IMPEDANCE AT THE INPUTS To minimize the effect of input bias current in an amplifier circuit (this is important for very high sourceimpedance applications, such as pH meters and transimpedance amplifiers), the impedances at the inverting and non-inverting inputs need to be matched. This is done by choosing the circuit resistor values so that the total resistance at each input is the same. Figure 4-8 shows a summing amplifier circuit. RG2 VIN2 RG1 VIN1 VSS RF VDD – RX MCP623X VOUT + RY Guard Ring FIGURE 4-7: for Inverting Gain. 1. 2. Example Guard Ring Layout Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN–). This biases the guard ring to the common mode input voltage. Inverting Gain and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. RZ FIGURE 4-8: Summing Amplifier Circuit. To match the inputs, set all voltage sources to ground and calculate the total resistance at the input nodes. In this summing amplifier circuit, the resistance at the inverting input is calculated by setting VIN1, VIN2 and VOUT to ground. In this case, RG1, RG2 and RF are in parallel. The total resistance at the inverting input is: EQUATION 4-1: 1 R VIN – = ---------------------------------------------1 + ----1-⎞ 1 + --------⎛ --------⎝R ⎠ R R G1 G2 F Where: RVIN– = total resistance at the inverting input At the non-inverting input, VDD is the only voltage source. When VDD is set to ground, both Rx and Ry are in parallel. The total resistance at the non-inverting input is: EQUATION 4-2: 1 R VIN + = ------------------------- + RZ 1- + ----1-⎞ ⎛ ----⎝R R ⎠ X Y Where: RVIN+ © 2009 Microchip Technology Inc. = total resistance at the inverting input DS21881E-page 13 MCP6231/1R/1U/2/4 To minimize output offset voltage and increase circuit accuracy, the resistor values need to meet the conditions: EQUATION 4-3: R VIN + = R VIN – 4.7.2 COMPENSATING FOR THE PARASITIC CAPACITANCE In analog circuit design, the PCB parasitic capacitance can compromise the circuit behavior; Figure 4-9 shows a typical scenario. If the input of an amplifier sees parasitic capacitance of several picofarad (CPARA, which includes the common mode capacitance of 6 pF, typical), and large RF and RG, the frequency response of the circuit will include a zero. This parasitic zero introduces gain-peaking and can cause circuit instability. + VAC MCP623X – RG VOUT RF VDC CPARA CF RG C F = C PARA • ------RF FIGURE 4-9: Effect of Parasitic Capacitance at the Input. One solution is to use smaller resistor values to push the zero to a higher frequency. Another solution is to compensate by introducing a pole at the point at which the zero occurs. This can be done by adding CF in parallel with the feedback resistor (RF). CF needs to be selected so that the ratio CPARA:CF is equal to the ratio of RF:RG. DS21881E-page 14 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 5.0 DESIGN AIDS Microchip provides the basic design tools needed for the MCP6231/1R/1U/2/4 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6231/1R/ 1U/2/4 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab® Software Microchip’s FilterLab® software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 Mindi™ Circuit Designer & Simulator Microchip’s Mindi™ Circuit Designer & Simulator aids in the design of various circuits useful for active filter, amplifier and power-management applications. It is a free online circuit designer & simulator available from the Microchip web site at www.microchip.com/mindi. This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, simulate circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation. 5.4 5.5 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip web site at: www.microchip.com/analogtools Two of our boards that are especially useful are: • P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board • P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board 5.6 Application Notes The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. • ADN003: “Select the Right Operational Amplifier for your Filtering Circuits”, DS21821 • AN722: “Operational Amplifier Topologies and DC Specifications”, DS00722 • AN723: “Operational Amplifier AC Specifications and Applications”, DS00723 • AN884: “Driving Capacitive Loads With Op Amps”, DS00884 • AN990: “Analog Sensor Conditioning Circuits – An Overview”, DS00990 These application notes and others are listed in the design guide: • “Signal Chain Design Guide”, DS21825 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip web site at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase, and Sampling of Microchip parts. © 2009 Microchip Technology Inc. DS21881E-page 15 MCP6231/1R/1U/2/4 NOTES: DS21881E-page 16 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SC70 (MCP6231U Only) Example: XXNN AS25 Example: 5-Lead SOT-23 5 XXNN 1 Device 4 2 3 Code MCP6231 BJNN MCP6231R BKNN MCP6231U BLNN Note: 8-Lead DFN (2 x 3) (MCP6231) XXX YWW NNN Applies to 5-Lead SOT-23. 5 4 BJ25 1 2 3 Example: AER 929 256 8-Lead TDFN (2 x 3) (MCP6232) Example: AAE 929 256 XXX YWW NNN Example: 8-Lead MSOP XXXXXX 6232E YWWNNN 929256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS21881E-page 17 MCP6231/1R/1U/2/4 Package Marking Information (Continued) 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN 14-Lead PDIP (300 mil) (MCP6234) Example: MCP6232 E/P256 0929 MCP6232 E/P e3 256 0929 OR Example: MCP6232 E/SN0929 256 MCP6232E SN e3 0929 256 OR Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP6234) MCP6234 e3 E/P^^ 0929256 Example: MCP6234 e3 E/SL^^ 0929256 XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP6234) Example: XXXXXXXX YYWW 6234E 0929 NNN 256 DS21881E-page 18 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ D b 3 1 2 E1 E 4 5 e A e A2 c A1 L 3# 4# 5$8 %1 44"" 5 5 56 7 ( 1# 6,:# ; 9()* < !!1// ; < #! %% < 6,=!# " ; !!1/=!# " ( ( ( 6,4# ; ( . #4# 4 9 4!/ ; < 9 4!=!# 8 ( < !"! #$! !% #$ !% #$ #&! ! !# "'( )*+ ) #&#,$ --# $## - *9) © 2009 Microchip Technology Inc. DS21881E-page 19 MCP6231/1R/1U/2/4 . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ DS21881E-page 20 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 ! . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ b N E E1 3 2 1 e e1 D A2 A c φ A1 L L1 3# 4# 5$8 %1 44"" 5 56 7 5 ( 4!1# ()* 6$# !4!1# 6,:# < !!1// ; < #! %% < ( 6,=!# " < !!1/=!# " < ; 6,4# < )* ( . #4# 4 < 9 . ## 4 ( < ; . # I > < > 4!/ ; < 9 4!=!# 8 < ( !"! #$! !% #$ !% #$ #&! ! !# "'( )*+ ) #&#,$ --# $## - *) © 2009 Microchip Technology Inc. DS21881E-page 21 MCP6231/1R/1U/2/4 " # $ %&'() *!*+,-.#$ . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ e D b N N L K E2 E EXPOSED PAD NOTE 1 NOTE 1 2 1 1 2 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 3# 4# 5$8 %1 44"" 5 5 56 7 ; 1# 6,:# ; #! %% ( * ##/ ". 6,4# )* 6,=!# " "& !1!4# < "& !1!=!# " ( < ( 8 ( * ##4# 4 ( * ### "& !1! ? < < * ##=!# ()* )* 1, $!&%#$,08$#$ #8 #!-###! 1/, & !#8 #! 1/ - $#! !# "'( )*+ ) #&#,$ --# $## ".+ % 0$ $-# $## 0% % # $ (( - ** DS21881E-page 22 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 " # $ %&'() *!*+,-.#$ . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ © 2009 Microchip Technology Inc. DS21881E-page 23 MCP6231/1R/1U/2/4 " # $ %&'() *!*+-.#$ . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ DS21881E-page 24 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 " # $ %&'() *!*+-.#$ . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ © 2009 Microchip Technology Inc. DS21881E-page 25 MCP6231/1R/1U/2/4 " ( &'(( . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 3# 4# 5$8 %1 44"" 5 5 56 7 ; 1# 6,:# < 9()* < !!1// ( ;( ( #! %% < ( 6,=!# " !!1/=!# " )* 6,4# )* . #4# 4 . ## 4 )* 9 ; (". . # I > < ;> 4!/ ; < 4!=!# 8 < 1, $!&%#$,08$#$ #8 #!-###! !"! #$! !% #$ !% #$ #&!( ! !# "'( )*+ ) #&#,$ --# $## ".+ % 0$ $-# $## 0% % # $ - *) DS21881E-page 26 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009 Microchip Technology Inc. DS21881E-page 27 MCP6231/1R/1U/2/4 " # /)! -.#/ . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 3# 4# 5$8 %1 5*:" 5 5 56 7 ; 1# # #1 < < !!1// ( ( ) # #1 ( < < $!# $!=!# " ( !!1/=!# " ( ; 6,4# ; 9( # #1 4 ( ( 4!/ ; ( 8 9 8 ; ) < < 34!=!# 4 -4!=!# 6, -@ )* 1, $!&%#$,08$#$ #8 #!-###! @%#*# # !"! #$! !% #$ !% #$ #&!A ! !# "'( )*+) #&#,$ --# $## - *;) DS21881E-page 28 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 " )0%!+,-./ . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 β L1 3# 4# 5$8 %1 44"" 5 5 56 7 ; 1# 6,:# < )* < !!1// ( < < #! %%@ < ( 6,=!# " !!1/=!# " )* 6,4# )* ( 9)* *%B # C ( < ( . #4# 4 < . ## 4 ". . # I > < ;> 4!/ < ( 4!=!# 8 < ( !%# D (> < (> !%#) ## E (> < (> 1, $!&%#$,08$#$ #8 #!-###! @%#*# # !"! #$! !% #$ !% #$ #&!( ! !# "'( )*+ ) #&#,$ --# $## ".+ % 0$ $-# $## 0% % # $ - *() © 2009 Microchip Technology Inc. DS21881E-page 29 MCP6231/1R/1U/2/4 " )0%!+,-./ . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ DS21881E-page 30 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 12 # /)! -.#/ . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 3# 4# 5$8 %1 5*:" 5 5 56 7 1# # #1 < < !!1// ( ( ) # #1 ( < < $!# $!=!# " ( !!1/=!# " ( ; 6,4# ( ( ( # #1 4 ( ( 4!/ ; ( 8 ( 9 8 ; ) < < 34!=!# 4 -4!=!# 6, -@ )* 1, $!&%#$,08$#$ #8 #!-###! @%#*# # !"! #$! !% #$ !% #$ #&!A ! !# "'( )*+) #&#,$ --# $## - *() © 2009 Microchip Technology Inc. DS21881E-page 31 MCP6231/1R/1U/2/4 12 )0%!+,-./ . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ D N E E1 NOTE 1 1 2 3 e h b α h A A2 c φ L A1 β L1 3# 4# 5$8 %1 44"" 5 5 56 7 1# 6,:# < )* < !!1// ( < < #! %%@ < ( 6,=!# " !!1/=!# " )* 6,4# ;9()* ( 9)* *%B # C ( < ( . #4# 4 < . ## 4 ". . # I > < ;> 4!/ < ( 4!=!# 8 < ( !%# D (> < (> !%#) ## E (> < (> 1, $!&%#$,08$#$ #8 #!-###! @%#*# # !"! #$! !% #$ !% #$ #&!( ! !# "'( )*+ ) #&#,$ --# $## ".+ % 0$ $-# $## 0% % # $ - *9() DS21881E-page 32 © 2009 Microchip Technology Inc. MCP6231/1R/1U/2/4 . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ © 2009 Microchip Technology Inc. DS21881E-page 33 MCP6231/1R/1U/2/4 12 33& )2+2-. . # #$#/!- 0 # 1/%# #!# ##+22--- 2/ D N E E1 NOTE 1 1 2 e b c φ A2 A A1 3# 4# 5$8 %1 L L1 44"" 5 5 56 7 1# 6,:# < 9()* < !!1// ; ( #! %% ( < ( 6,=!# " !!1/=!# " 9)* !!1/4# ( ( . #4# 4 ( 9 ( . ## 4 ( ". . # I > < ;> 4!/ < 4!=!# 8 < 1, $!&%#$,08$#$ #8 #!-###! !"! #$! !% #$ !% #$ #&!( ! !# "'( )*+ ) #&#,$ --# $## ".+ % 0$ $-# $## 0% % # $ - *;) DS21881E-page 34 © 2009 Microchip Technology Inc. MCP6231/2/4 APPENDIX A: REVISION HISTORY Revision E (August 2009) The following is the list of modifications: 1. 2. 3. 4. 5. 6. Added the 2x3 TDFN package for MCP6232. Updated the 2x3 DFN package information for MCP6231. Updated the “Temperature Characteristics” table. Updated Section 3.0 “Pin Descriptions”. Updated the Package Outline Drawings in Section 6.0 “Packaging Information”. Updated the Product Identification Systems section. Revision C (March 2005) The following is the list of modifications: 1. 2. 3. 4. 5. Added the MCP6234 quad op amp. Corrected plots in Section 2.0 “Typical Performance Curves”. Added Section 3.0 “Pin Descriptions”. Added new SC-70 package markings. Added PDIP-14, SOIC-14, and TSSOP-14 packages and corrected package marking information (Section 6.0 “Packaging Information”). Added Appendix A: “Revision History”. Revision B (August 2004) • Undocumented changes. Revision D (May 2008) Revision A (March 2004) The following is the list of modifications: • Original Release of this Document. 1. Changed Heading “Available Tools” to “Design Aids”. 2. Design Aids: Name change for Mindi Simulator Tool. 3. Package Types: Added DFN to MCP6231 Device. 4. Absolute Maximum Ratings: Numerous changes in this section. 5. Updated notes to Section 1.0 “Electrical Characteristics”. 6. Added Test Circuits to Section 1.0 “Electrical Characteristics”. 7. Corrected Figure 2-7. 8. Added Figure 2-19. 9. Numerous changes to Section 3.0 “Pin Descriptions”. 10. Added Section 4.1.1 “Phase Reversal”, Section 4.1.2 “Input Voltage and Current Limits”, and Section 4.1.3 “Normal Operation”. 11. Replaced Section 5.0 “Design Aids” with additional information. 12. Updated Section 6.0 “Packaging Information” with updated Package Outline Drawings. © 2009 Microchip Technology Inc. DS21881E-page 35 MCP6231/2/4 NOTES: DS21881E-page 36 © 2009 Microchip Technology Inc. MCP6231/2/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X Device Tape and Reel and/or Alternate Pinout Device: -X /XX Temperature Package Range MCP6231: MCP6231T: MCP6231RT: MCP6231UT: MCP6232: MCP6232T: MCP6234: MCP6234T: Single Op Amp (MSOP, PDIP, SOIC) Single Op Amp (Tape and Reel) (MSOP, SOIC, SOT-23) Single Op Amp (Tape and Reel) (SOT-23) Single Op Amp (Tape and Reel) (SC70, SOT-23, TDFN) Dual Op Amp Dual Op Amp (Tape and Reel) (MSOP, SOIC) Quad Op Amp Quad Op Amp (Tape and Reel) (TSSOP, SOIC) Temperature Range: E = -40° C to +125° C Package: LT = Plastic Package (SC70), 5-lead (MCP6231U only) MC = Plastic Dual Flat No-Lead (DFN) 2x3, 8-lead (MCP6231 only) MNY= Plastic Dual Flat No-Lead (TDFN) 2x3, 8-lead (MCP6232 only) MS = Plastic Micro Small Outline (MSOP), 8-lead P = Plastic DIP (300 mil Body), 8-lead, 14-lead OT = Plastic Small Outline Transistor (SOT-23), 5-lead (MCP6231, MCP6231R, MCP6231U) SN = Plastic SOIC (150 mil Body), 8-lead SL = Plastic SOIC (150 mil Body), 14-lead ST = Plastic TSSOP (4.4 mil Body), 14-lead Examples: a) MCP6231-E/MC: Extended Temperature 8LD DFN package. b) MCP6231-E/MS: Extended Temperature 8LD MSOP package. c) MCP6231UT-E/LT: Tape and Reel, Extended Temperature 5LD SC70 package. d) MCP6231-E/P: Extended Temperature 8LD PDIP package. e) MCP6231RT-E/OT: Tape and Reel, Extended Temperature 5LD SOT-23 package f) MCP6231UT-E/OT: Tape and Reel, Extended Temperature 5LD SOT-23. g) MCP6231-E/SN: Extended Temperature 8LD SOIC package. a) MCP6232-E/SN: b) c) d) e) Extended Temperature 8LD SOIC package. MCP6232-E/MS: Extended Temperature 8LD MSOP package. MCP6232-E/P: Extended Temperature 8LD PDIP package. MCP6232T-E/SN: Tape and Reel, Extended Temperature 8LD SOIC package. MCP6232T-E/MNY: Tape and Reel, Extended Temperature 8LD TDFN package. a) MCP6234-E/P: b) MCP6234-E/SL: c) MCP6234-E/ST: d) MCP6234T-E/SL: e) MCP6234T-E/ST: © 2009 Microchip Technology Inc. Extended Temperature 14LD PDIP package. Extended Temperature 14LD SOIC package. Extended Temperature, 14LD TSSOP package Tape and Reel, Extended Temperature 14LD SOIC package. Tape and Reel, Extended Temperature 14LD TSSOP package. DS21881E-page 37 MCP6231/2/4 NOTES: DS21881E-page 38 © 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009 Microchip Technology Inc. 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