TI THS4052ID

THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
D
D
D
D
D
D
D
THS4051
D, DGN, AND JG PACKAGE
(TOP VIEW)
High Speed
– 70 MHz Bandwidth (G = 1, –3 dB)
– 240 V/µs Slew Rate
– 60-ns Settling Time (0.1%)
High Output Drive, IO = 100 mA (typ)
Excellent Video Performance
– 0.1 dB Bandwidth of 30 MHz (G = 1)
– 0.01% Differential Gain
– 0.01° Differential Phase
Very Low Distortion
– THD = –82 dBc (f = 1 MHz, RL = 150 Ω)
– THD = –89 dBc (f = 1 MHz, RL = 1 kΩ)
Wide Range of Power Supplies
– VCC = ±5 V to ±15 V
Available in Standard SOIC, MSOP
PowerPAD, JG or FK Package
Evaluation Module Available
NULL
IN –
IN +
VCC–
1
8
2
7
3
6
4
5
NULL
VCC+
OUT
NC
NC – No internal connection
THS4052
D AND DGN† PACKAGE
(TOP VIEW)
1OUT
1IN –
1IN +
–VCC
1
8
2
7
3
6
4
5
VCC+
2OUT
2IN–
2IN+
description
Cross Section View Showing
PowerPAD Option (DGN)
† This device is in the Product Preview stage of development.
Please contact your local TI sales office for availability.
NC
NULL
20 19
NC
NULL
1
18 NC
IN–
5
17 VCC+
NC
6
16 NC
IN+
7
15 OUT
NC
8
14 NC
10 11 12 13
NC
9
NC
DESCRIPTION
290-MHz Low Distortion High-Speed Amplifiers
100-MHz Low Noise High-Speed Amplifiers
175-MHz Low Power High-Speed Amplifiers
2
4
VCC–
NC
DEVICE
3
NC
RELATED DEVICES
THS4011/2
THS4031/2
THS4081/2
NC
THS4051
FK PACKAGE
(TOP VIEW)
NC
The THS4051 and THS4052 are general-purpose, single/dual, high-speed voltage feedback
amplifiers ideal for a wide range of applications
including video, communication, and imaging.
The devices offer very good ac performance with
70-MHz bandwidth, 240-V/µs slew rate, and
60-ns settling time (0.1%). The THS4051/2 are
stable at all gains for both inverting and noninverting configurations. These amplifiers have a
high output drive capability of 100 mA and draw
only 8.5-mA supply current per channel. Excellent
professional video results can be obtained with
the low differential gain/phase errors of 0.01%/
0.01° and wide 0.1 dB flatness to 30 MHz. For
applications requiring low distortion, the
THS4051/2 is ideally suited with total harmonic
distortion of –82 dBc at 1 MHz.
CAUTION: The THS4051 and THS4052 provide ESD protection circuitry. However, permanent damage can still occur if this device
is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance
degradation or loss of functionality.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
THD - Total Harmonic Distortion - dBc
–40
–50
VCC = ± 15 V
Gain = 2
VO(PP) = 2 V
–60
RL = 150 Ω
–70
–80
RL = 1 kΩ
–90
–100
100k
1M
f - Frequency - Hz
10M
20M
AVAILABLE OPTIONS
PACKAGED DEVICES
NUMBER
OF
CHANNELS
TA
0°C to 70°C
– 40°C to 85°C
PLASTIC
SMALL
OUTLINE†
(D)
PLASTIC MSOP†
(DGN)
DEVICE
SYMBOL
CERAMIC DIP
(JG)
CHIP
CARRIER
(FK)
EVALUATION
MODULE
1
THS4051CD
—
—
THS4051EVM
THS4052CD
THS4051CDGN
THS4052CDGN‡
ACQ
2
ACE
—
—
THS4052EVM
1
THS4051ID
THS4051IDGN
ACR
—
—
—
2
THS4052ID
THS4052IDGN‡
ACF
—
—
—
– 55°C to 125°C
1
—
—
—
THS4051MJG
THS4051MFK
† The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4051CDGN).
‡ This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
—
functional block diagram
VCC
1IN–
1OUT
1IN+
Null
2IN–
IN–
IN+
2
2OUT
1
2IN+
8
6
3
OUT
–VCC
Figure 1. THS4051 – Single Channel
2
POST OFFICE BOX 655303
Figure 2. THS4052 – Dual Channel
• DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VCC
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
Differential input voltage, VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Operating free-air temperature, TA: C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package . . . . . . . . . . . . . . . . . . . . 300°C
Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
θJA
(°C/W)
θJC
(°C/W)
TA = 25°C
POWER RATING
D
167‡
38.3
740 mW
DGN§
58.4
4.7
2.14 W
JG
119
28
1050 mW
FK
87.7
20
1375 mW
‡ This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed High-K
test PCB, the θJA is 95°C/W with a power rating at TA = 25°C of 1.32 W.
§ This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in. PC.
For further information, refer to Application Information section of this data sheet.
recommended operating conditions
MIN
Supply voltage
voltage, VCC+
CC and VCC–
CC
Operating free-air temperature, TA
NOM
MAX
±4.5
±16
Single supply
9
32
C-suffix
0
70
Dual supply
I-suffix
–40
85
M-suffix
–55
125
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
°C
3
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted)
dynamic performance
MIN
TYP
VCC = ±15 V
VCC = ±5 V
Gain = 1
VCC = ±15 V
VCC = ±5 V
Gain = 2
0 1 dB flatness
Bandwidth for 0.1
VCC = ±15 V
VCC = ±5 V
Gain = 1
Full power bandwidth§
VO(pp) = 20 V,
VO(pp) = 5 V,
VCC = ±15 V
VCC = ±5 V
Slew rate‡
VCC = ±15 V,
VCC = ±5 V,
20-V step,
Gain = 5
240
5-V step
Gain = –1
200
Settling time to 0.1%
0 1%
VCC = ±15 V,
VCC = ±5 V,
5-V step
Settling time to 0
0.01%
01%
VCC = ±15 V,
VCC = ±5 V,
5-V step
Dynamic
y
performance small-signal
g
bandwidth
(–3 dB)
BW
SR
THS405xC, THS405xI
TEST CONDITIONS†
PARAMETER
ts
2-V step
2-V step
MAX
70
MHz
70
38
MHz
38
30
MHz
30
3.8
MHz
12.7
V/µs
60
Gain = –1
1
ns
60
130
Gain = –1
1
UNIT
ns
140
† Full range = 0°C to 70°C for C suffix and – 40°C to 85°C for I suffix
‡ Slew rate is measured from an output level range of 25% to 75%.
§ Full power bandwidth = slew rate/2 πVO(Peak).
noise/distortion performance
THD
Vn
In
Total harmonic distortion
Input voltage noise
Input current noise
Differential gain error
VO(
O(pp)) = 2 V,,
f = 1 MHz, Gain = 2
VCC = ±15 V
VCC = ±5 V
MIN
TYP
RL = 150 Ω
–82
RL = 1 kΩ
–89
RL = 150 Ω
–78
RL = 1 kΩ
–87
MAX
UNIT
dBc
VCC = ±5 V or ±15 V,
VCC = ±5 V or ±15 V,
f = 10 kHz
14
nV/√Hz
f = 10 kHz
0.9
pA/√Hz
Gain = 2,,
40 IRE modulation,
NTSC,,
±100 IRE ramp
VCC = ±15 V
VCC = ±5 V
0.01%
VCC = ±15 V
VCC = ±5 V
0.01°
Differential phase error
Gain = 2,,
40 IRE modulation,
NTSC,,
±100 IRE ramp
Channel-to-channel crosstalk
(THS4052 only)
VCC = ±5 V or ±15 V,
f = 1 MHz
† Full range = 0°C to 70°C for C suffix and – 40°C to 85°C for I suffix.
4
THS405xC, THS405xI
TEST CONDITIONS†
PARAMETER
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.01%
0.03°
–57
dB
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) (continued)
dc performance
MIN
TYP
9
VCC = ±15 V,
V RL = 1 kΩ
VO = ±10 V
TA = 25°C
TA = full range
5
VCC = ±5 V
V, RL = 250 Ω
VO = ±2
±2.5
5V
TA = 25°C
TA = full range
2.5
Open loop gain
Input offset voltage
VCC = ±5 V or ±15 V
Offset voltage drift
VCC = ±5 V or ±15 V
IIB
Input bias current
VCC = ±5 V or ±15 V
IOS
Input offset current
VCC = ±5 V or ±15 V
VOS
THS405xC, THS405xI
TEST CONDITIONS†
PARAMETER
MAX
V/mV
3
6
V/mV
2
TA = 25°C
TA = full range
2.5
TA = full range
TA = 25°C
15
10
12
2.5
TA = full range
TA = 25°C
35
6
250
400
Offset current drift
TA = full range
† Full range = 0°C to 70°C for C suffix and – 40°C to 85°C for I suffix
mV
µV/°C
8
TA = full range
UNIT
0.3
µA
nA
nA/°C
input characteristics
THS405xC, THS405xI
TEST CONDITIONS†
PARAMETER
VICR
Common mode input voltage range
Common-mode
VCC = ±15 V
VCC = ±5 V
CMRR
Common mode rejection ratio
VCC = ±15 V,
VCC = ±5 V,
ri
Input resistance
VICR = ±12 V
VICR = ±2.5 V
TA = full range
MIN
TYP
±13.8
±14.3
± 3.8
± 4.3
70
100
70
100
Ci
Input capacitance
† Full range = 0°C to 70°C for C suffix and – 40°C to 85°C for I suffix
MAX
UNIT
V
dB
1
MΩ
1.5
pF
output characteristics
TEST CONDITIONS†
PARAMETER
VO
Output voltage swing
VCC = ±15 V
VCC = ±5 V
±11.5
±13
±3.2
±3.5
RL = 20 Ω
VCC = ±15 V
VCC = ±5 V
ISC
Short-circuit current‡
VCC = ±15 V
TYP
RL = 150 Ω
RL = 1 kΩ
Output current‡
MIN
RL = 250 Ω
VCC = ±15 V
VCC = ±5 V
IO
THS405xC, THS405xI
±13
±13.6
±3.5
±3.8
80
100
50
75
150
MAX
UNIT
V
V
mA
mA
RO
Output resistance
Open loop
13
Ω
† Full range = 0°C to 70°C for C suffix and – 40°C to 85°C for I suffix
‡ Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or
shorted. See the absolute maximum ratings section of this data sheet for more information.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted) (continued)
power supply
VCC
ICC
PSRR
THS405xC, THS405xI
TEST CONDITIONS†
PARAMETER
MIN
Dual supply
Supply voltage operating range
Single supply
MAX
±4.5
±16.5
9
33
VCC = ±15 V
TA = 25°C
TA = full range
8.5
VCC = ±5 V
TA = 25°C
TA = full range
7.5
VCC = ±5 V or ±15 V
TA = 25°C
TA = full range
Supply current (per amplifier)
Power supply rejection ratio
TYP
UNIT
V
10.5
11.5
mA
9.5
10.5
70
84
dB
68
† Full range = 0°C to 70°C for C suffix and – 40°C to 85°C for I suffix
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
dynamic performance
VCC = ±15 V,
VCC = ±15 V
Unity gain bandwidth
Dynamic
y
performance small-signal
g
bandwidth
(–3 dB)
Closed loop
Bandwidth for 0.1
0 1 dB flatness
VCC = ±5 V
VO(pp) = 20 V,
Full power bandwidth‡
VO(pp) = 5 V,
VCC = ±15 V,
Slew rate
0 1%
Settling time to 0.1%
ts
Settling time to 0
0.01%
01%
30
30
3.8
2-V step
VCC = ±5 V,
2-V step
5-V step
5-V step
• DALLAS, TEXAS 75265
Gain = –1
1
Gain = –1
Gain = –1
1
MAX
UNIT
MHz
MHz
38
12.7
RL = 1 kΩ
VCC = ±5 V,
VCC = ±15 V,
POST OFFICE BOX 655303
38
VCC = ±15 V
VCC = ±5 V
5-V step
70
70
Gain = 1
VCC = ±5 V,
VCC = ±15 V,
TYP
70
Gain = 2
† Full range = –55°C to 125°C for the THS4051M.
‡ Full power bandwidth = slew rate/2 πVO(Peak).
§ This parameter is not tested.
6
RL = 1 kΩ
MIN
50§
Gain = 1
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
BW
SR
THS4051M
TEST CONDITIONS†
PARAMETER
240§
300
200
60
60
130
140
MHz
MHz
V/µs
ns
ns
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
noise/distortion performance
THD
Total harmonic distortion
THS4051M
TEST CONDITIONS†
PARAMETER
VCC = ±15 V
VO(pp) = 2 V,
f = 1 MHz,
MHz Gain = 2,
2
TA = 25
25°C
C
VCC = ±5 V
MIN
TYP
RL = 150 Ω
–82
RL = 1 kΩ
–89
RL = 150 Ω
–78
RL = 1 kΩ
–87
MAX
UNIT
dBc
Vn
Input voltage noise
VCC = ±5 V or ±15 V,
TA = 25°C
f = 10 kHz,
RL = 150 Ω
14
nV/√Hz
In
Input current noise
VCC = ±5 V or ±15 V,
TA = 25°C
f = 10 kHz,
RL = 150 Ω
0.9
pA/√Hz
Gain = 2,
40 IRE modulation,
modulation
TA = 25°C,
NTSC,
±100 IRE ramp,
ramp
RL = 150 Ω
VCC = ±15 V
0.01%
Differential gain error
VCC = ±5 V
0.01%
Gain = 2,
40 IRE modulation,
modulation
TA = 25°C,
NTSC,
±100 IRE ramp,
ramp
RL = 150 Ω
VCC = ±15 V
0.01°
VCC = ±5 V
0.03°
Differential phase error
† Full range = –55°C to 125°C for the THS4051M.
dc performance
MIN
TYP
9
V VO = ±10 V
VCC = ±15 V,
TA = 25°C
TA = full range
5
VCC = ±5 V
V, VO = ±2
±2.5
5V
TA = 25°C
TA = full range
2.5
Input offset voltage
VCC = ±5 V or ±15 V
TA = 25°C
TA = full range
Offset voltage drift
VCC = ±5 V or ±15 V
Open loop gain
VIO
THS4051M
TEST CONDITIONS†
PARAMETER
IIB
Input bias current
VCC = ±5 V or ±15 V
IIO
Input offset current
VCC = ±5 V or ±15 V
MAX
V/mV
3
6
V/mV
2
2.5
10
13
TA = full range
TA = 25°C
TA = full range
TA = 25°C
6
8
35
TA = full range
250
400
Offset current drift
TA = full range
† Full range = –55°C to 125°C for the THS4051M.
mV
µV/°C
15
2.5
UNIT
0.3
µA
nA
nA/°C
input characteristics
THS4051M
TEST CONDITIONS†
PARAMETER
VICR
Common mode input voltage range
Common-mode
VCC = ±15 V
VCC = ±5 V
CMRR
Common mode rejection ratio
VCC = ±15 V,
VCC = ±5 V,
ri
Input resistance
VICR = ±12 V
VICR = ±2.5 V
TA = full range
Ci
Input capacitance
† Full range = –55°C to 125°C for the THS4051M.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
TYP
±13.8
±14.3
± 3.8
± 4.3
70
100
70
100
MAX
UNIT
V
dB
1
MΩ
1.5
pF
7
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
electrical characteristics at TA = full range, VCC = ±15 V, RL = 1 kΩ (unless otherwise noted)
(continued)
output characteristics
TEST CONDITIONS†
PARAMETER
VO
VCC = ±15 V
VCC = ±5 V
Output voltage swing
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V,
TA = full range
Output current‡
±12
±13
±3.2
±3.5
RL = 1 kΩ
RL = 20 Ω
±13
±13.6
±3.5
±3.8
80
100
MAX
50
UNIT
V
V
mA
70
VCC = ±15 V
Short-circuit current‡
TYP
RL = 150 Ω
VCC = ±5 V
ISC
MIN
RL = 250 Ω
VCC = ±15 V,
TA = 25°C
IO
THS4051M
75
150
mA
RO
Output resistance
Open loop
13
Ω
† Full range = –55°C to 125°C for the THS4051M.
‡ Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or
shorted. See the absolute maximum ratings section of this data sheet for more information.
power supply
VCC
ICC
MIN
Dual supply
Supply voltage operating range
Single supply
TYP
±16.5
9
33
TA = 25°C
TA = full range
8.5
VCC = ±5 V
TA = 25°C
TA = full range
7.5
VCC = ±5 V or ±15 V
TA = full range
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
±4.5
VCC = ±15 V
Supply current (per amplifier)
PSRR Power supply rejection ratio
† Full range = –55°C to 125°C for the THS4051M.
8
THS4051M
TEST CONDITIONS†
PARAMETER
UNIT
V
10.5
11.5
9.5
mA
10.5
70
84
dB
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
2.8
–1.0
–1.5
–2.0
–2.5
VCC = ± 15 V
–20
0
20
40
60
80
TA - Free-Air Temperature - °C
2.5
2.4
5
15
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
11
13.5
11
9
7
10
13
VCC = ± 15 V
RL = 1 kΩ
12.5
VCC = ± 15 V
RL = 250 Ω
12
VCC = ± 5 V
RL = 1 kΩ
4.5
4
3.5
VCC = ± 5 V
RL = 150 Ω
5
3
2.5
–40
3
7
9
11
13
±VCC - Supply Voltage - V
15
TA=25°C
8
7
TA=–40°C
6
5
–20
0
20
40
60
80
100
5
7
9
11
13
± VCC - Supply Voltage - V
Figure 7
VCC = ± 15 V and ± 5V
TA = 25°C
100
VN
10
IN
100k
0
POWER SUPPLY REJECTION
RATIO
vs
FREQUENCY
–10
CMRR
vs
FREQUENCY
VCC = ±15 V & ±5 V
–20
–VCC
–30
–40
–50
+VCC
–60
–70
–80
–90
100k
1M
10M
f - Frequency - Hz
100M
Figure 10
POST OFFICE BOX 655303
15
Figure 8
CMRR – Common-Mode Rejection Ratio – dB
PSRR - Power Supply Rejection Ratio - dB
VOLTAGE & CURRENT NOISE
vs
FREQUENCY
Figure 9
TA=85°C
9
TA – Free-Air Temperature – _C
Figure 6
100
1k
10k
f - Frequency - Hz
I CC – Supply Current – mA
V
13
0.10
10
7
9
11
13
±VCC - Supply Voltage - V
Figure 5
14
TA=25°C
VO - Output Voltage -
V ICR - Common-Mode Input Voltage – ± V
100
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
15
1
RL = 150 Ω
6
Figure 4
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
1000
8
2
–20
0
20
40
60
80
TA - Free-Air Temperature - °C
Figure 3
5
RL = 1 kΩ
10
4
2.2
–40
100
12
V
2.6
2.3
–3.0
–3.5
–40
TA=25°C
2.7
VO - Output Voltage -
IB Input Bias Current – µ A
VCC = ± 5 V
–0.5
14
VCC = ± 5 V & ±15 V
I
V IO – Input Offset Voltage – mV
0.0
V n – Voltage Noise – nV/ Hz
I n – Current Noise – pA/ Hz
OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
• DALLAS, TEXAS 75265
–20
VCC = ±15 V or ±5 V
RF = 1 kΩ
VI(PP) = 2 V
–30
–40
–50
–60
–70
–80
–90
–100
10k
100k
1M
10M
100M
f – Frequency – Hz
Figure 11
9
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
TYPICAL CHARACTERISTICS
OPEN LOOP GAIN AND
PHASE RESPONSE
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
30
VCC = ± 5 V & ±15 V
80
Open Loop Gain – dB
–30
Crosstalk – dB
100
VCC = ± 15 V
Gain = 2
RF = 3.6 kΩ
RL = 150 Ω
–40
–50
–60
0
Gain
60
–30
40
–60
20
–90
Phase
0
–70
–80
100k
–120
–20
100M
10M
1M
100k
Figure 12
Figure 13
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
–50
–50
VCC = ± 15 V
RL = 1 kΩ
G=5
f = 1 MHz
–55
–60
RL = 150 Ω
–70
–60
–66
–70
2nd Harmonic
–75
–60
–66
2nd Harmonic
–70
–75
–80
3rd Harmonic
–80
–80
RL = 1 kΩ
3rd Harmonic
–90
–85
–85
–100
100k
–90
–90
1M
f - Frequency - Hz
10M
0
20M
5
15
0
20
5
–60
–70
2nd Harmonic
–40
VCC = ± 5 V
RL = 1 kΩ
G=2
VO(PP) = 2 V
–50
Distortion – dBc
Distortion – dBc
–50
–60
–70
2nd Harmonic
–80
–80
–90
–90
20
DISTORTION
vs
FREQUENCY
–40
VCC = ± 15 V
RL = 1 kΩ
G=2
VO(PP) = 2 V
15
Figure 16
DISTORTION
vs
FREQUENCY
–40
10
VO – Output Voltage – V
Figure 15
DISTORTION
vs
FREQUENCY
–50
10
VO – Output Voltage – V
Figure 14
Distortion – dBc
VCC = ± 15 V
RL = 150 Ω
G=5
f = 1 MHz
–55
Distortion – dBc
VCC = ± 15 V
Gain = 2
VO(PP) = 2 V
DISTORTION
vs
OUTPUT VOLTAGE
DISTORTION
vs
OUTPUT VOLTAGE
Distortion – dBc
THD - Total Harmonic Distortion - dBc
–50
–150
100M
1M
10M
f - Frequency - Hz
f – Frequency – Hz
–40
Phase
–20
VCC = ± 15 V
RL = 150 Ω
G=2
VO(PP) = 2 V
–60
–70
2nd Harmonic
–80
3rd Harmonic
3rd Harmonic
–90
3rd Harmonic
–100
–100
100k
10
1M
10M
100M
–100
100k
1M
10M
100M
100k
1M
10M
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 17
Figure 18
Figure 19
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100M
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
TYPICAL CHARACTERISTICS
OUTPUT AMPLITUDE
vs
FREQUENCY
DISTORTION
vs
FREQUENCY
–40
2
RF = 750 Ω
1
Output Amplitude – dB
–60
2nd Harmonic
–70
3rd Harmonic
–80
RF = 620 Ω
–1
–2
RF = 0 Ω
–3
VCC = ± 15 V
Gain = 1
RL = 150 Ω
VO(PP) = 62 mV
–4
–90
–5
–100
1M
10M
–6
100k
100M
f – Frequency – Hz
Figure 20
0.4
0.3
RF = 750 Ω
Output Amplitude – dB
Output Amplitude – dB
0.2
0.1
–0.0
–0.1
RF = 620 Ω
–0.2
–0.3
–0.4
100k
RF = 0 Ω
1M
10M
f - Frequency - Hz
0.2
0.1
0
100k
RF = 620 Ω
–0.2
6.3
Output Amplitude – dB
RF = 1 kΩ
VCC = ±5 V
Gain = 2
RL = 150 Ω
VO(PP) = 125 mV
Figure 26
RF = 3.6 kΩ
6
5
RF = 2.7 kΩ
4
3
RF = 1 kΩ
2
1
1M
10M
f - Frequency - Hz
0
100k
100M
6.2
6.3
RF = 3.6 kΩ
5.9
5.7
100M
6.4
6.0
5.8
5.6
100k
RF = 2.7 kΩ
100M
Figure 27
POST OFFICE BOX 655303
100M
6.2
VCC = ±5 V
Gain = 2
RL = 150 Ω
VO(PP) = 125 mV
6.1
• DALLAS, TEXAS 75265
RF = 3.6 kΩ
6.0
5.9
RF = 2.7 kΩ
5.8
5.7
RF = 1 kΩ
1M
10M
f - Frequency - Hz
1M
10M
f - Frequency - Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
VCC = ±15 V
Gain = 2
RL = 150 Ω
VO(PP) = 125 mV
6.1
VCC = ±15 V
Gain = 2
RL = 150 Ω
VO(PP) = 125 mV
Figure 25
OUTPUT AMPLITUDE
vs
FREQUENCY
RF = 2.7 kΩ
1M
10M
f - Frequency - Hz
7
Figure 24
RF = 3.6 kΩ
100M
8
–0.1
6.4
1M
10M
f - Frequency - Hz
OUTPUT AMPLITUDE
vs
FREQUENCY
–0.0
–0.4
100k
100M
5
1
–4
RF = 0 Ω
6
2
VCC = ± 5 V
Gain = 1
RL = 150 Ω
VO(PP) = 62 mV
Figure 22
–0.3
8
3
RF = 0 Ω
–3
–6
100k
100M
RF = 750 Ω
OUTPUT AMPLITUDE
vs
FREQUENCY
4
1M
10M
f - Frequency - Hz
VCC = ± 5 V
Gain = –1
RL = 150 Ω
VO(PP) = 62 mV
Figure 23
7
RF = 620 Ω
–2
OUTPUT AMPLITUDE
vs
FREQUENCY
0.4
0.3
–1
Figure 21
OUTPUT AMPLITUDE
vs
FREQUENCY
VCC = ± 15 V
Gain = 1
RL = 150 Ω
VO(PP) = 62 mV
0
–5
Output Amplitude – dB
100k
RF = 750 Ω
1
0
Output Amplitude – dB
Distortion – dBc
2
Output Amplitude – dB
VCC = ± 5 V
RL = 150 Ω
G=2
VO(PP) = 2 V
–50
Output Amplitude – dB
OUTPUT AMPLITUDE
vs
FREQUENCY
5.6
100k
RF = 1 kΩ
1M
10M
f - Frequency - Hz
100M
Figure 28
11
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
TYPICAL CHARACTERISTICS
OUTPUT AMPLITUDE
vs
FREQUENCY
OUTPUT AMPLITUDE
vs
FREQUENCY
8
OUTPUT AMPLITUDE
vs
FREQUENCY
2
2
1
6
0
5
RL = 1 kΩ
4
RL = 150 Ω
3
VCC = ±15 V
Gain = 2
RL = 2.7 k Ω
VO(PP) = 125 mV
2
1
0
100k
RF = 5.6 kΩ
–1
RF = 3.9 kΩ
–2
RF = 1 kΩ
–3
VCC = ± 15 V
Gain = –1
RL = 150 Ω
VO(PP) = 62 mV
–4
–5
1M
10M
f - Frequency - Hz
–6
100k
100M
Figure 29
–10
VCC = ± 15 V
Gain = 2
RF = 2.7 kΩ
RL = 150 Ω
–25
100
VCC = ± 15 V
0.1%
80
VCC = ± 5 V
0.1%
40
RF = 360 Ω
VCC = ± 15 V
0.06
0.04
2
3
4
VO - Output Step Voltage - V
1
5
0.6°
Gain = 2
RF = 1 kΩ
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
0.3°
VCC = ± 15 V
0.2°
VCC = ± 5 V
0.1°
0
3
Number of 150-Ω Loads
Figure 35
4
VCC = ± 15 V
0.4°
0.3°
VCC = ± 5 V
0.2°
0.1°
0°
2
Gain = 2
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
0.5°
Differential Phase
0.4°
VCC = ± 5 V
0.04
4
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.5°
VCC = ± 15 V
3
Figure 34
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
0.08
2
Number of 150-Ω Loads
Figure 33
0.12
VCC = ± 5 V
0
1
Gain = 2
40 IRE-PAL Modulation
Worst Case ± 100 IRE Ramp
1
0.08
0.02
20
100M
Differential Phase
Differential Gain – %
0.10
VCC = ± 15 V
0.01%
120
Gain = 2
40 IRE-NTSC Modulation
Worst Case ± 100 IRE Ramp
60
1M
10M
f - Frequency - Hz
100M
0.12
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
0.16
1M
10M
f - Frequency - Hz
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
VCC = ± 5 V
0.01%
Figure 32
0.2
VCC = ± 5 V
Gain = –1
RL = 150 Ω
VO(PP) = 62 mV
–4
Figure 31
Differential Gain – %
VO(PP)=0.4 V
–20
RF = 1 kΩ
–3
–6
100k
100M
140
Settling Time – ns
V O(PP) - Output Voltage - dBV
0
–30
100k
12
1M
10M
f - Frequency - Hz
160
VO(PP)=2.25 V
VO(PP)=125 mV
RF = 3.9 kΩ
–2
–5
180
–15
–1
SETTING TIME
vs
OUTPUT STEP
10
–5
0
Figure 30
OUTPUT AMPLITUDE
vs
FREQUENCY
5
RF = 5.6 kΩ
1
Output Amplitude – dB
7
Output Amplitude – dB
Output Amplitude – dB
CL= 10 pF
0°
1
2
3
4
1
2
3
Number of 150-Ω Loads
Number of 150-Ω Loads
Figure 36
Figure 37
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
4
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
TYPICAL CHARACTERISTICS
1-V STEP RESPONSE
5-V STEP RESPONSE
–0.0
–0.2
–0.4
0.6
2
0.4
1
0
–1
VCC = ± 5 V
Gain = –1
RF = 3.9 kΩ
RL = 150 Ω
–2
–0.6
50
100 150 200 250 300 350 400
t - Time - ns
VCC = ± 15 V
Gain = 2
RF = 2.7 kΩ
RL = 150 Ω
0.2
–0.0
–0.2
–0.4
–3
0
–0.6
0
50
100 150 200 250 300 350 400
t - Time - ns
Figure 38
Figure 39
0
50
100 150 200 250 300 350 400
t - Time - ns
Figure 40
20-V STEP RESPONSE
15
VCC = ± 15 V
Gain = 5
RF = 2.7 kΩ
RL = 150 & 1 kΩ
10
V O – Output Voltage – V
V O – Output Voltage – V
0.2
1-V STEP RESPONSE
3
V O – Output Voltage – V
VCC = ± 5 V
Gain = 2
RF = 2.7 kΩ
RL = 150 Ω
0.4
V O – Output Voltage – V
0.6
5
0
–5
–10
–15
0
100
200
300
t - Time - ns
400
500
Figure 41
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• DALLAS, TEXAS 75265
13
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
theory of operation
The THS405x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built
using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing
fTs of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high
slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 42.
(7) VCC +
(6) OUT
IN – (2)
IN + (3)
(4) VCC –
NULL (1)
NULL (8)
Figure 42. THS4051 Simplified Schematic
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true when amplifying small signals, where
signal-to-noise ratio (SNR) is very important. The noise model for the THS405x is shown in Figure 43. This
model includes all of the noise sources as follows:
•
•
•
•
14
en = Amplifier internal voltage noise (nV/√Hz)
IN+ = Noninverting current noise (pA/√Hz)
IN– = Inverting current noise (pA/√Hz)
eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx )
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THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
noise calculations and noise figure (continued)
eRs
RS
en
Noiseless
+
_
eni
IN+
eno
eRf
RF
eRg
IN–
RG
Ǹǒ Ǔ
Figure 43. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
e
Where:
+
ni
en
2
ǒ
) IN )
Ǔ )ǒ ǒ
2
R
S
IN–
R
ǓǓ
ǒ
Ǔ
ø RG ) 4 kTRs ) 4 kT RF ø RG
F
2
k = Boltzmann’s constant = 1.380658 × 10–23
T = Temperature in degrees Kelvin (273 +°C)
RF || RG = Parallel resistance of RF and RG
ǒ Ǔ
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
e no
+ eni AV + e
ni
1
) RR
F
(noninverting case)
G
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, please refer to the Noise Analysis section in Operational Amplifier
Circuits Applications Report (literature number SLVA043).
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15
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
noise calculations and noise figure (continued)
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
NF
+ 10log
ȱȧ
Ȳǒ
ȳȧ
Ǔȴ
e 2
ni
2
e
Rs
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
ȱȧ ȡȧǒ
ȧȧ )Ȣ
ȧȲ
e
NF
+ 10log
Ǔ )ǒ )
2
n
IN
1
4 kTR
Ǔ ȣȧȤȳȧ
2
R
S
S
ȧȧ
ȧȴ
Figure 44 shows the noise figure graph for the THS405x.
NOISE FIGURE
vs
SOURCE RESISTANCE
40
f = 10 kHz
TA = 25°C
35
Noise Figure (dB)
30
25
20
15
10
5
0
10
100
1k
10k
Source Resistance - Ω
100k
Figure 44. Noise Figure vs Source Resistance
16
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• DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS405x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 45. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
1 kΩ
1 kΩ
Input
_
20 Ω
Output
THS405x
+
CLOAD
Figure 45. Driving a Capacitive Load
offset nulling
The THS405x has very low input offset voltage for a high-speed amplifier. However, if additional correction is
required, an offset nulling function has been provided on the THS4051. The input offset can be adjusted by
placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply. This
is shown in Figure 46.
VCC+
0.1 µF
+
THS4051
_
10 kΩ
0.1 µF
VCC –
Figure 46. Offset Nulling Schematic
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17
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
RF
IIB–
RG
+
–
VI
VO
+
RS
ǒ ǒ ǓǓ ǒ ǒ ǓǓ
IIB+
V
OO
+ VIO 1 )
R
R
F
G
" IIB) RS
1
)
R
R
F
G
" IIB– RF
Figure 47. Output Offset Voltage Model
optimizing unity gain response
Internal frequency compensation of the THS405x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
for the G=+1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 620 Ω should
be used as shown in Figure 48. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
Input
+
Output
THS406x
_
620 Ω
Figure 48. Noninverting, Unity Gain Schematic
18
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THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 49).
RG
RF
–
VO
+
VI
R1
C1
f
–3dB
V
O
V
I
ǒ Ǔǒ
+ 1 ) RRF
G
1
Ǔ
) sR1C1
1
1
+ 2pR1C1
Figure 49. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
+
_
VI
R1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
R2
f
C2
RG
RF
–3dB
RG =
+ 2p1RC
(
RF
1
2–
Q
)
Figure 50. 2-Pole Low-Pass Sallen-Key Filter
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THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high frequency performance of the THS405x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS405x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
D
D
D
D
D
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
Surface-mount passive components – Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
general PowerPAD design considerations
The THS405x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die
is mounted [see Figure 51(a) and Figure 51(b)]. This arrangement results in the lead frame being exposed as
a thermal pad on the underside of the package [see Figure 51(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away
from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
20
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THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 51. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 52. PowerPAD PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 52. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS405xDGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS405xDGN package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS405xDGN IC is simply placed in position and run through
the solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
POST OFFICE BOX 655303
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21
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The actual thermal performance achieved with the THS405xDGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θJA, is about 58.4°C/W. For comparison, the non-PowerPAD version
of the THS405x IC (SOIC) is shown. For a given θJA, the maximum power dissipation is shown in Figure 53 and
is calculated by the following formula:
P
Where:
+
D
ǒ Ǔ
T
–T
MAX A
q JA
PD = Maximum power dissipation of THS405x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA
= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
Maximum Power Dissipation – W
3.5
DGN Package
θJA = 58.4°C/W
2 oz. Trace And Copper Pad
With Solder
3
2.5
SOIC Package
High-K Test PCB
θJA = 98°C/W
2
TJ = 150°C
DGN Package
θJA = 158°C/W
2 oz. Trace And
Copper Pad
Without Solder
1.5
1
0.5
SOIC Package
Low-K Test PCB
θJA = 167°C/W
0
–40
–20
60
80
0
20
40
TA – Free-Air Temperature – °C
100
NOTE A: Results are with no air flow and PCB size = 3”× 3”
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal management techniques can be
found in the Texas Instruments Technical Brief, PowerPAD  Thermally Enhanced Package. This document can
be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also
be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially devices with multiple amplifiers. Because these devices have linear output stages (Class
A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 54 to Figure 57 show
this effect, along with the quiescent heat, with an ambient air temperature of 50°C. Obviously, as the ambient
temperature increases, the limit lines shown will drop accordingly. The area under each respective limit line is
considered the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure
may result. When using VCC = ±5 V, there is generally not a heat problem, even with SOIC packages. But, when
using VCC = ±15 V, the SOIC package is severely limited in the amount of heat it can dissipate. The other key
factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are
extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use
the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent
on how it is mounted on the PCB. As more trace and copper area is placed around the device, θJA decreases
and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total
package. For the dual amplifier package (THS4052), the sum of the RMS output currents and voltages should
be used to choose the proper package. The graphs shown assume that both amplifier’s outputs are identical.
THS4051
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
VCC = ± 5 V
Tj = 150°C
TA = 50°C
180
1000
Maximum Output
Current Limit Line
| IO | – Maximum RMS Output Current – mA
| IO | – Maximum RMS Output Current – mA
200
160
140
Package With
θJA < = 120°C/W
120
100
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
80
60
40
Safe Operating
Area
20
4
1
2
3
| VO | – RMS Output Voltage – V
TJ = 150°C
TA = 50°C
VCC = ± 15 V
DGN Package
θJA = 58.4°C/W
Maximum Output
Current Limit Line
100
SO-8 Package
θJA = 98°C/W
High-K Test PCB
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
Safe Operating
Area
10
0
0
THS4051
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
5
0
3
6
9
12
| VO | – RMS Output Voltage – V
15
Figure 55
Figure 54
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
THS4052
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
180
1000
Maximum Output
Current Limit Line
Package With
θJA ≤ 60°C/W
| IO | – Maximum RMS Output Current – mA
| IO | – Maximum RMS Output Current – mA
200
160
140
120
100
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
80
60
Safe Operating Area
40
SO-8 Package
θJA = 98°C/W
High-K Test PCB
20
0
0
VCC = ± 5 V
TJ = 150°C
TA = 50°C
Both Channels
4
1
2
3
| VO | – RMS Output Voltage – V
THS4052
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
VCC = ± 15 V
TJ = 150°C
TA = 50°C
Both Channels
100
SO-8 Package
θJA = 98°C/W
High-K Test PCB
10
DGN Package
θJA = 58.4°C/W
Safe Operating Area
5
1
0
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
3
6
9
12
| VO | – RMS Output Voltage – V
Figure 57
Figure 56
24
Maximum Output
Current Limit Line
POST OFFICE BOX 655303
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15
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
APPLICATION INFORMATION
evaluation board
An evaluation board is available for the THS4051 (literature number SLOP220) and THS4052 (literature number
SLOP234). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the evaluation board is shown in Figure 58. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. For more
information, please refer to the THS4051 EVM User’s Guide or the THS4052 EVM User’s Guide. To order the
evaluation board, contact your local TI sales office or distributor.
VCC+
+
C5
0.1 µF
R4
2 kΩ
IN +
C2
6.8 µF
NULL
R5
49.9 Ω
+
R3
49.9 Ω
OUT
THS4051
_
NULL
R2
2 kΩ
+
C4
0.1 µF
C1
6.8 µF
IN –
VCC –
R1
49.9 Ω
Figure 58. THS4051 Evaluation Board
POST OFFICE BOX 655303
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25
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
1
Gage Plane
7
A
0.010 (0,25)
0°– 8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
0.004 (0,10)
4040047 / D 10/96
NOTES: A.
B.
C.
D.
26
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
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THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
MECHANICAL INFORMATION
DGN (S-PDSO-G8)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
8
0,25 M
5
Thermal Pad
(See Note D)
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
1
0°– 6°
4
3,05
2,95
0,69
0,41
Seating Plane
1,07 MAX
0,15
0,05
0,10
4073271/A 01/98
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions include mold flash or protrusions.
The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments.
POST OFFICE BOX 655303
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27
THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
25
5
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
28
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
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THS4051, THS4052
70-MHz HIGH-SPEED AMPLIFIERS
SLOS238C– MAY 1999 – REVISED MAY 2000
MECHANICAL INFORMATION
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE PACKAGE
0.400 (10,20)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.063 (1,60)
0.015 (0,38)
0.100 (2,54)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
Falls within MIL-STD-1835 GDIP1-T8
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Copyright  2000, Texas Instruments Incorporated